VSC9188
F E A T U R E S :
Bidirectional 2.5 Gb/s VT1.5 Pointer Processor, Path Terminator
and Column Aligner
VT1.5 Pointer Processing on 4 x 336 VT1.5 Groups within
4 x STS-12 Backplane Signals
Path Termination and Generation of STS-1 Traffic
4 x 622 Mb/s STS-12 LVDS Backplane Interface Inputs with
Integrated CDR and Realignment
Two 4 x 622 Mb/s STS-12 LVDS Backplane Interface Outputs
for Working and Protection Fan-out
Interfaces with VSC9186 10 Gb/s Pointer Processor and
VSC9187 3024 x 3024 VT1.5 TSI
Generates In-band VT Signalling of UPSR Performance
Monitoring Information for Hardware-based Protection
Switching in VSC9187 3024 x 3024 VT1.5 TSI
VSC9188 Stratton - 2.5 Gb/s VT1.5 Pointer Processor Path Terminator and Column Aligner
2.5V/1.8V Power Supply, 0.18
m Technology
Compliant with SONET Requirements as Stated in ANSI T1.105 and
Telcordia GR-253-CORE
Facilitates Hardware-based UPSR Switching in Accordance with
Telcordia GR-1400-CORE
Provides JTAG TAP Controller Conforming to the IEEE 1149.1 Standard
Thermally-enhanced 552-pin CCGA Package
S P E C I F I C A T I O N S :
2.5V/1.8V power supply, 0.18
m technology
A P P L I C A T I O N S :
VT1.5 Pointer Processing
Column Aligning
Performance Monitoring
Interface to a Large-scale VT1.5 Crossconnect.
B E N E F I T S :
Low Cost
Low Power
High Functionality
TIMESTREAM
TM
PRODUCT FAMILY
PB-VSC9188-001
K E Y S P E C I F I C A T I O N S :
PARAMETERS
DESCRIPTION
Min
Max
Conditions
Vdd_core
Vdd_IO
Voltage for Core
Voltage of IO cells
2.97V
2.3V
3.63V
2.7V
Recommended 3.3V
Recommended 2.5V
POWER DISSIPATION
IDD_2.5
PD_typical
PD_peak
Peak power supply current from 2.5V VDD
Typical power dissipation
Peak power dissipation
5 W
3 W
0.3A
Nominal
Nominal
Nominal
Backplane Data I/Os
622 Mb/s LVDS
For more information on Vitesse Products visit the Vitesse web site
at www.vitesse.com or contact Vitesse Sales at (800) VITESSE
or sales@vitesse.com
2002 Vitesse Semiconductor Corporation
741 Calle Plano
Camarillo, CA 93012, USA
Tel: +1 805.388.3700
Fax: +1 805.987.5896
www.vitesse.com
The VSC9188 is a VT1.5 Pointer Processor
and Column Aligner. The primary application
for this device is to provide column alignment
and performance monitoring for VT1.5
payloads and interface these tributaries
to a large-scale VT1.5 crossconnect.
The VSC9188 receives four serial STS-12 622 Mb/s
signals from a VSC9186 10Gb/s Pointer Processor or
VSC9182 STS-1 grooming crossconnect. These signals are
terminated at the path level, monitored at the VT1.5 level, and
G E N E R A L D E S C R I P T I O N :
VSC9188 Stratton - 2.5 Gb/s VT1.5 Pointer Processor Path Terminator and Column Aligner
column-aligned at the VT1.5 level in a deterministic fashion to
a local SYNC signal. GR-1400 UPSR performance information
is aggregated and placed in the VT overhead for use in the VT
crossconnect. The four processed serial STS-12 622 Mb/s
signals are duplicated on working and protection STS-12 622
Mb/s outputs for fan-out to protected VT fabrics. Four serial
STS-12 622 Mb/s signals are received from the switch and the
Path Overhead (POH) is reconstructed prior to transmission.
Various loopback and test modes are also available.
VSC9188
4 x 622Mb/s
STS-12
Serial
Backplane
Outputs
DL12I[3:0]
Line Side Backplane
Switch Side Backplane
DL12O[3:0]
DS12I[3:0]
DS12O[3:0]
DS12O[3:0]
4 x 622Mb/s
STS-12
Serial
Backplane
Inputs
JTAG Interface
System Interface and PLL
HS-CLK LS-CLK SYNC M-SYNC
TDO
TDI
TCK
TMS
TRSTB
CLKREF
SYNCREF
TRIST
PLLBYP
ISCEN
SHOR
T
R
TSN
CIRDO
CICDI
RD_R
WN
DS_WR
AS_ALE
CICLK
CI_MODE[1:0]
CS
DT
ACK_RDY
INTRPT
A[15:0]
D[7:0]
GPO[7:0]
GPI[7:0]
CPU Interface
STS-12 Line
Loopback
VT PP
Loopback
Switch
Loopback
GR-1400 UPSR
Performance Information
4 x 622Mb/s
STS-12
Serial
Backplane
Inputs
Rx Direction
Tx Direction
VSC9188
(2)
4 x 622Mb/s
STS-12
Serial
Backplane
Outputs
STS-1 Pointer
Interpreter
VT Pointer
Processor and
Column Aligner
M-SYNC
STS-1 Path
Overhead
Monitoring
VT1.5 Path
Overhead
Monitoring
Alarm
Status
Byte
Insertion
STS-1 Path
Overhead
Insertion
FEBE & RDI
V S C 9 1 8 8 B L O C K D I A G R A M :
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