Revision 1.0

Subject to Change without Notice

SiI 201

C Intelligent Panel Controller

PanelLink

Digital

March 1999

General Description

Features

The

SiI 201

C Intelligent Panel Controller (IPC) uses PanelLink Digital

technology to support displays ranging from VGA to XGA (25-68 MHz), which is
ideal for LCD notebook and desktop monitor applications. With a flexible single
or dual pixel out interface and selectable output drive, the

SiI 201

C IPC supports

up to true color panels (24 bit/pixel, 16.7M colors) in 1 or 2 pixels/clock mode.
The

SiI 201

C is highly programmable to support multiple column and row drivers

and to optimize display quality. PanelLink also features an inter-pair skew
tolerance up to 1 full input clock cycle and a highly jitter tolerant PLL design.

PanelLink Digital technology simplifies PC design by resolving many of the

system level issues associated with high-speed digital design, providing the
system designer with a digital interface solution that is quicker to market and
lower in cost.

Scaleable Bandwidth: 25-68 MHz (VGA to XGA)

Low Power: 3.3V core operation & power-down mode

High Skew Tolerance: 1 full input clock cycle (15ns at 65
MHz)

Highly programmable: supports multiple column drivers

Sync Detect: for Plug & Display "Hot Plugging"

Cable Distance Support: over 5m with twisted-pair, fiber-
optics ready

Compliant with DVI 1.0 (DVI is backwards compatible
with VESA® P&D

and DFP)

SiI 201

C Pin Diagram

Reserved

PGND

PVCC

EXT_RES

RXC-

RXC+

AGND

RX0-

RX0+

AVCC

RX1-

RX1+

AGND

RX2-

RX2+

AVCC

GND

OVCC

VCC

CK_B

W 4 8

S C A L E _ I N

R O F F _ T ( 2 )

R O F F _ T ( 1 )

R O F F _ T ( 0 )

R O E _ T ( 1 )

R O E _ T ( 0 )

V C C

G N D

C V _ P

C O N V

P O L

O G N D

S C D T

/POL /

C D A T A 0

O V C C

Reserved /

C D A T A 1

C D A T A 2

C D A T A 3

C D A T A 4

C D A T A 5

C D A T A 6

C D A T A 7

Reserved /

C D A T A 8

PL_T /

C D A T A 9

C D A T A 3 1

C D _ E /

C D A T A 3 2

PIX_O /

C D A T A 3 3

C D A T A 3 4

C D A T A 3 5

C D A T A 3 6

C D A T A 3 7

C D A T A 3 8

C D A T A 3 9

O G N D

C D A T A 4 0

/ DINV

C D A T A 4 1
/ ST

C D A T A 4 2

C D A T A 4 3

C D A T A 4 4

C D A T A 4 5

C D A T A 4 6

V C C

C D A T A 4 7

CIN

C L T 1 /

C D I R

C L T 2 /

C I N 2

RIN

R O E

R C K

CDATA29

CDATA30

CDATA28

CDATA27

CDATA26

CK_P /

CDATA25

OGND

CCK

CV_W /

CDATA24

CDATA23

CDATA22

CDATA21

GND

CDATA20

CDATA19

CDATA18

CK_D /

CDATA17

CK_T /

CDATA16

OVCC

CDATA15

CDATA14

CDATA13

CDATA12

CDATA11

CDATA10

PDO

VCC

GND

2 5

1 0 0

7 5

SiI201C

1 0 0 P i n T Q F P

5 0

Silicon Image, Inc.

SiI 201C

SiI/DS-0005-C

Revision 1 0

Subject to Change without Notice

Functional Block Diagram

The SiI 201C consists of four major blocks: the Functional PanelLink Interface, Sync Detection and the Row and Column
Interface.

PanelLink

Interface: The SiI 201C accepts the

PanelLink

interface of 4 low swing, differential input signals. One

pair contains the pixel clock, the other three pairs are the serialized and encoded red, green and blue channels. Each of the
color channels also contain two encoded control signals. The

PanelLink

technology de-serializes and decodes the input

data to recover the original panel interface, labeled PPI in the block diagram. This interface is a one color pixel per clock
interface at 24 bits per pixel, the recovered input clock is ICK.

Column Interface(CIN, CCK, CONV, CDTA): The column interface block is programmed so that the column drive
outputs are set to match the desired column drivers. By programming the pins CK_P, CK_B, CK_D, CK_T, CV_W,
CV_P, PL_T and DINV a wide variety of column drivers can be addressed.

Row Interface(RIN, RCK, ROE): The row driving signals are output from this block. While the row signals require no
programmability, their timing with respect to the column drive signals is critical, and varies with panel size and processing
parameters. Sufficient time must be allowed for the row select signals to be fully switched off before the column driver's
analog outputs are allowed to change. This time T

OFF

, can be set over a wide range of values through the ROFF_T[2:0]

programming input bits. If the row driver chosen has an output enable, the width of the output enable pulse can be set
using ROE_T[1:0].

Sync Detect: This block monitors the state of HSYNC. If HSYNC becomes inactive the output signal SCDT will be set
low. This signal can be used to control driver and backlight supplies enabling panel protection and power savings.

IDTA

R X C

R X 0
R X 1
R X 2

P a n e l L i n k

Interface

P P I

C C K

C O N V

CIN

C D T A

2 4 / 4 8

V S Y N C

H S Y N C

I C K

D E

IDTA

2 4

C o l u m n C o n t r o l

CK_P

CV_W

CK_B

R o w T i m i n g

ROFF_T

ROE_T

CD_E

Polarity

PL_T

P o w e r C o n t r o l

PDO

CV_P

V S Y N C

D E

H S Y N C

I C K

C D I R

S y n c

D e t e c t

H S Y N C

S C D T

P O L

R C K

R O E

RIN

C C K

C O N V

CIN

C D T A

2 4 / 4 8

C T L 1 / C D I R

P O L

S C D T

C T L 2 / C I N 2

C T L

2 4

/ P O L

PIX_O

I / 0

CK_D

CK_T

S C A L E _ I N

W48

SCALE_IN

DINV

P e r i p h e r y
Controller

PanelLink

Technology

Silicon Image, Inc.

SiI 201C

SiI/DS-0005-C

Revision 1 0

Subject to Change without Notice

Absolute Maximum Conditions

Note: Permanent device damage may occur if absolute maximum conditions are exceeded.

Functional operation should be restricted to the conditions described under Normal Operating Conditions

Symbol

Parameter

Min

Typ

Max

Units

Supply

Voltage

-0.3 -

6.0

Input

Voltage

-0.3 - V

+ 0.3

Output Voltage

-0.3

+ 0.3

Ambient Temperature
(with power applied)

-25 -

STG

Storage

Temperature

-40 -

125

Package Power Dissipation

Normal Operating Conditions

Symbol

Parameter

Min

Typ

Max

Units

Supply

Voltage

3.0 3.3

3.6

CCN

Supply Voltage Noise

100

P-P

Ambient Temperature
(with power applied)

25 70

Note:

Guaranteed by design.

DC Digital I/O Specifications

Under normal operating conditions unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Units

High-level Input Voltage

Low-level Input Voltage

0.8

High-level Output Voltage

2.4

Low-level Output Voltage

0.4

CINL

Input Clamp Voltage

= -18mA

GND -0.8

CIPL

Input Clamp Voltage

= 18mA

IVCC + 0.8

CONL

Output Clamp Voltage

= -18mA

GND -0.8

COPL

Output Clamp Voltage

= 18mA

OVCC + 0.8

Input Leakage Current

-10

Note:

Guaranteed by design.

DC Specifications

Under normal operating conditions unless otherwise specified. Low drive strength values, when ST=0, are shown in brackets.

Symbol

Parameter

Conditions

Min

Typ

Max

Units

(ST=0) Output High Drive (CCK)

(ST=1)

OUT

= V

16.5

10.5

(ST=0) Output Low Drive (CCK)

(ST=1)

OUT

= V

-8.5

-19

-12
-24

-15.4

-27

(ST=0) Output High Drive (All Others)
(ST=1)

OUT

= V

5.5

(ST=0) Output Low Drive (All Others)
(ST=1)

OUT

= V

-5.6

-9

-8

-16

-10
-11

Differential Input Voltage Single Ended
Amplitude

250

1000

Power-down

Current

PDL

Output leakage current to ground in high
impedance mode (PD, PDO = LOW)

CCR

Supply Current @ 3.3V V

Output is one pixel per clock mode.

DLCK = 65 MHz
C

LOAD

= 10pF

EXT_SWING

= 680

Typical Pattern

137 157 mA

DCLK = 65 MHz
C

LOAD

= 10pF

EXT_SWING

= 680

Worst Case Pattern

153 185 mA

Notes:

The transmitter must be in power-down mode, powered off, or disconnected for the current to be under this maximum.

For worst case I/O power consumption.

The Typical Pattern contains a gray scale area, checkerboard area, and text.

Black and white checkerboard pattern, each checker is one pixel wide.

Silicon Image, Inc.

SiI 201C

SiI/DS-0005-C

Revision 1 0

Subject to Change without Notice

AC Specifications

Under normal operating conditions unless otherwise specified. Low drive strength values, when ST=0, are shown in brackets.

Symbol

Parameter

Conditions

Min

Typ

Max

Units

DPS

Intra-Pair (+ to -) Differential Input Skew

200

CCS

Channel to Channel Differential Input Skew

CIP

IJIT

Worst Case Differential Input Clock Jitter tolerance

1,2

2 ns

LHT

Low-to-High Transition Time: Data and Controls

ST=1 [ST=0]
C

= 10pF [5pF]

1.9

[1.9]

CCK

1.6

[1.4]

HLT

High-to-Low Transition Time: Data and Controls

ST=1 [ST=0]
C

= 10pF [5pF]

1.6

[1.6]

CCK

1.4

[1.2]

SOF

Data/Control Setup Time to CCK:

65 MHz, One Pixel / Clock, PIXS = 0

ST=1 [ST=0]
C

= 10pF [5pF]

CK_T = 0

6.0

[5.8]

ST=1 [ST=0]
C

= 10pF [5pF]

CK_T = 1

1.8 [2.1]

HOF

Data/Control Hold Time to CCK

65 MHz, One Pixel / Clock, PIXS = 0

ST=1 [ST=0]
C

= 10pF [5pF]

CK_T = 0

4.9

[4.5]

ST=1 [ST=0]
C

= 10pF [5pF]

CK_T = 1

8.9 [9.0]

CIP

CCK Cycle Time (1 pixel/clock)

14.7

CIP

CCK Frequency (1 pixel/clock)

MHz

CIP

CCK Cycle Time (2 pixels/clock)

29.4

100

CIP

CCK Frequency (2 pixels/clock)

MHz

CIH

CCK High Time
65 MHz, One Pixel / Clock, PIXS = 0

ST=1 [ST=0]
C

= 10pF [5pF]

5.3

[4.9]

CIL

CCK Low Time
65 MHz, One Pixel / Clock, PIXS = 0

ST=1 [ST=0]
C

= 10pF [5pF]

6.9

[6.7]

HSC

Link disabled (HSYNC inactive) to SCDT low

FSC

Link enabled (HSYNC active) to SCDT high

PDL

Delay from PD/ PDO Low to high impedance outputs

Notes:

Jitter can be estimated by: 1) triggering a digital scope at the rising of input clock, and 2) measuring the peak to peak time

spread of the rising edge of the input clock 1

s after the trigger.

Actual jitter tolerance may be higher depending on the frequency of the jitter.

Output clock duty cycle is independent of the differential input clock duty cycle and the IDCK duty cycle.

The setup and hold timing for the data and controls is measured relative to CCK rising edge.

Silicon Image, Inc.

SiI 201C

SiI/DS-0005-C

Revision 1 0

Subject to Change without Notice

1.1 Data Bus Mapping

18-bpp

24-bpp

36-bit

48-bit

Pin #

Name

1-pixel/clock

2-pixel/clock

CDATA0

B0/E

CDATA1

B1/E

CDATA2 B0

B0/E

B2/E

CDATA3 B1

B1/E

B3/E

CDATA4 B2

B2/E

B4/E

CDATA5 B3

B3/E

B5/E

CDATA6 B4

B4/E

B6/E

CDATA7 B5

B5/E

B7/E

CDATA8

G0/E

CDATA9

G1/E

CDATA10

G0 G2 G0/E

G2/E

CDATA11

G1 G3 G1/E

G3/E

CDATA12

G2 G4 G2/E

G4/E

CDATA13

G3 G5 G3/E

G5/E

CDATA14

G4 G6 G4/E

G6/E

CDATA15

G5 G7 G5/E

G7/E

CDATA16

R0/E

CDATA17

R1/E

CDATA18

R0 R2 R0/E

R2/E

CDATA19

R1 R3 R1/E

R5/E

CDATA20

R2 R4 R2/E

R4/E

CDATA21

R3 R5 R5/E

R5/E

CDATA22

R4 R6 R4/E

R6/E

CDATA23

R5 R7 R5/E

R7/E

CDATA24

B0/O

CDATA25

B1/O

CDATA26

B0/O

B2/O

CDATA27

B1/O

B3/O

CDATA28

B2/O

B4/O

CDATA29

B3/O

B5/O

CDATA30

B4/O

B6/O

CDATA31

B5/O

B7/O

CDATA32

G0/O

CDATA33

G1/O

CDATA34

G0/O

G2/O

CDATA35

G1/O

G3/O

CDATA36

G2/O

G4/O

CDATA37

G3/O

G5/O

CDATA38

G4/O

G6/O

CDATA39

G5/O

G7/O

CDATA40

R0/O

CDATA41

R1/O

CDATA42

R0/O

R2/O

CDATA43

R1/O

R3/O

CDATA44

R2/O

R4/O

CDATA45

R3/O

R5/O

CDATA46

R4/O

R6/O

CDATA47

R5/O

R7/O

Legend :

1. R = RED Channel, G = GREEN Channel, B = BLUE Channel.
2. /E = EVEN (first) pixel data (P0, P2, P4, etc.)
3. /O = ODD (second) pixel data (P1, P3, P5, etc.)

Assumptions on how

PanelLink

is connected :

1. Bits 7:0 mapped MSB:LSB.
2. Tx0/Rx0 transmits BLUE (B) data.
3. Tx1/Rx1 transmits GREEN (G) data.
4. Tx2/Rx2 transmits RED (R) data

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SII201C

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SII201C