Subject to Change without Notice
Si
I
151
PanelLink
Digital Receiver
July
1999
General Description
Features
The Si
I
151 uses PanelLink Digital technology to support displays ranging
from VGA to SXGA (25-112 MHz) which is ideal for desktop and specialty
applications. The Si
I
151 receiver supports up to true color panels (24 bit/pixel,
16.7M colors) in 1 or 2 pixels/clock mode, and also features an inter-pair skew
tolerance up to 1 full input clock cycle. In addition, the receiver data output is time
staggered to reduce ground bounce which affects EMI. Since all PanelLink
products are designed on scaleable CMOS architecture to support future
performance requirements while maintaining the same logical interface, system
designers can be assured that the interface will be fixed through a number of
technology and performance generations.
PanelLink Digital technology simplifies PC design by resolving many of the
system level issues associated with high-speed digital design, providing the
system designer with a digital interface solution that is quicker to market and
lower in cost.
Scaleable Bandwidth: 25-112 MHz (VGA to SXGA)
Low Power: 3.3V core operation & power-down mode
High Skew Tolerance: 1 full input clock cycle (9ns at
108 MHz)
Time staggered data output for reduced ground bounce
Sync Detect: for Plug & Display "Hot Plugging"
Cable Distance Support: over 5m with twisted-pair,
fiber-optics ready
Compliant with DVI 1.0 (DVI is backwards compatible
with VESA P&D
TM
and DFP)
Si
I
151 Pin Diagram
Functional Block Diagram
DFO
1
SiI151
100-Pin TQFP
(Top View)
PD
2
ST
3
PIXS
4
GND
5
VCC
6
STAG_OUT
7
SCDT
8
PDO
9
QE0
10
QE1
11
QE2
12
QE3
13
QE4
14
QE5
15
QE6
16
QE7
17
OVCC
18
OGND
19
QE8
20
QE9
21
QE10
22
QE11
23
QE12
24
QE13
25
QE14
26
QE15
27
OGND
28
OVCC
29
QE16
30
QE17
31
QE18
32
QE19
33
QE20
34
QE21
35
QE22
36
QE23
37
VCC
38
GND
39
CTL1
40
CTL2
41
CTL3
42
OVCC
43
ODCK
44
OGND
45
DE
46
VSYNC
47
HSYNC
48
QO0
49
QO1
50
75
QO21
74
QO20
73
QO19
72
QO18
71
QO17
70
QO16
69
GND
68
VCC
67
QO15
66
QO14
65
QO13
64
QO12
63
QO11
62
QO10
61
QO9
60
QO8
59
OGND
58
OVCC
57
QO7
56
QO6
55
QO5
54
QO4
53
QO3
52
QO2
51
QO22
OCK_INV
100
RESERVED
99
PGND
98
PVCC
97
EXT_RES
96
AVCC
95
RXC-
94
RXC+
93
AGND
92
RX0-
91
RX0+
90
AGND
89
AVCC
88
AGND
87
RX1-
86
RX1+
85
AVCC
84
AGND
83
AVCC
82
RX2-
81
RX2+
80
AGND
79
OVCC
78
QO23
77
OGND
76
DIFFERNTIAL
SIGNAL
ODD 8-bits RED
EVEN 8-bits RED
ODD 8-bits GREEN
EVEN 8-bits GREEN
ODD 8-bits BLUE
EVEN 8-bits BLUE
CONFIG. PINS
PLL
PWR
MANAGEMENT
GPO
OUTPUT CLOCK
CONTROLS
CTL3
RX2+
RX2-
RX1+
RX1-
RX0+
RX0-
RXC+
RXC-
SYNC2
EXT_RES
PDO
ST
ODCK
PIXS
DF0
OCK_INV
STAG_OUT
Data Recovery
CH2
VCR
Termination
Control
Data Recovery
CH1
VCR
Data Recovery
CH0
VCR
PLL
VCR
SYNC1
SYNC0
Channel
SYNC
SYNC2
SYNC1
SYNC0
Decoder
CTL2
CTL1
VSYNC
HSYNC
Panel
Inter-
face
Logic
QE[23:0]
24
QO[23:0]
24
DE
HSYNC
VSYNC
CTL3
CTL2
CTL1
SCDT
DATA
DATA
DATA
Silicon Image, Inc.
SiI151
SiI/DS-0007-E
2
Subject to Change without Notice
Absolute Maximum Conditions
Note: Permanent device damage may occur if absolute maximum conditions are exceeded.
Functional operation should be restricted to the conditions described under Normal Operating Conditions.
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Supply Voltage 3.3V
-0.3
4.0
V
V
I
Input Voltage
-0.3
V
CC
+ 0.3
V
V
O
Output Voltage
-0.3
V
CC
+ 0.3
V
T
A
Ambient Temperature (with power applied)
-25
105
C
T
STG
Storage Temperature
-40
125
C
P
PD
Package Power Dissipation
1
W
Normal Operating Conditions
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Supply Voltage
3.00
3.3
3.6
V
V
CCN
Supply Voltage Noise
1
100
mV
P-P
T
A
Ambient Temperature (with power applied)
0
25
70
C
Note:
1
Guaranteed by design.
DC Digital I/O Specifications
Under normal operating conditions unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
V
IH
High-level Input Voltage
2
V
V
IL
Low-level Input Voltage
0.8
V
V
OH
High-level Output Voltage
2.4
V
V
OL
Low-level Output Voltage
0.4
V
V
CINL
Input Clamp Voltage
1
I
CL
= -18mA
GND -0.8
V
V
CIPL
Input Clamp Voltage
1
I
CL
= 18mA
IVCC + 0.8
V
V
CONL
Output Clamp Voltage
1
I
CL
= -18mA
GND -0.8
V
V
COPL
Output Clamp Voltage
1
I
CL
= 18mA
OVCC + 0.8
V
I
OL
Output Leakage Current
High Impedance
-10
10
A
Note:
1
Guaranteed by design.
DC Specifications
Under normal operating conditions unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
I
OHD
Output High Drive
Data and Controls
V
OUT
= V
OH
;
ST = 1
ST = 0
4.2
2.1
8
4
18
9
mA
I
OLD
Output Low Drive
Data and Controls
V
OUT
= V
OL
;
ST = 1
ST = 0
5.2
2.6
5.5
2.75
11
5.5
mA
I
OHC
ODCK High Drive
V
OUT
= V
OH
;
ST = 1
ST = 0
8.5
4.2
17
9
37
18
mA
I
OLC
ODCK Low Drive
V
OUT
= V
OL
;
ST = 1
ST = 0
10.4
5.2
16
8
23
11
mA
V
ID
Differential Input Voltage
Single Ended Amplitude
75
1000
mV
I
PD
Power-down Current
2
10
mA
I
CCR
Receiver Supply Current
DCLK=112MHz, 1-pixel/clock mode
C
LOAD
= 10pF
R
EXT_SWING
= 680
Typical Pattern
3
215
235
mA
DCLK=112MHz, 1-pixel/clock mode
C
LOAD
= 10pF
R
EXT_SWING
= 680
Worse Case Pattern
4
240
265
mA
Note:
1
Guaranteed by design.
2
The transmitter must be in power-down mode, powered off, or disconnected for the current to be under this maximum.
3
The Typical Pattern contains a gray scale area, checkerboard area, and text.
4
Black and white checkerboard pattern, each checker is two pixel wide.
Silicon Image, Inc.
SiI151
SiI/DS-0007-E
3
Subject to Change without Notice
AC Specifications
Under normal operating conditions unless otherwise specified. Low drive strength values, when ST=0, are given below.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
T
DPS
Intra-Pair (+ to -) Differential Input Skew
1
112 MHz
One Pixel / Clock
360
ps
T
CCS
Channel to Channel Differential Input Skew
1
112 MHz
One Pixel / Clock
6
ns
T
IJIT
Worst Case Differential Input Clock Jitter tolerance
2,3
65 MHz, One Pixel / Clock
465
ps
112 MHz, One Pixel / Clock
270
D
LHT
Low-to-High Transition Time
Data and Controls
C
L
= 10pF; ST = 1
C
L
= 5pF;
ST = 0
5.5
3.1
ns
ODCK
C
L
= 10pF; ST = 1
C
L
= 5pF;
ST = 0
2.75
D
HLT
High-to-Low Transition Time
Data and Controls
C
L
= 10pF; ST = 1
C
L
= 5pF;
ST = 0
3
2.5
ns
ODCK
C
L
= 10pF; ST = 1
C
L
= 5pF;
ST = 0
2
T
SOF
Data/Control Setup Time to ODCK falling edge
4
(OCK_INV = 0)
65MHz, 1-pixel/clock, PIXS = 0
C
L
= 10pF; ST = 1
C
L
= 5pF;
ST = 0
3
3
ns
56MHz, 2-pixel/clock, PIXS = 1
C
L
= 10pF; ST = 1
C
L
= 5pF;
ST = 0
5
3.5
T
HOF
Data/Control Hold Time to ODCK falling edge
4
(OCK_INV = 0)
65MHz, 1-pixel/clock, PIXS = 0
C
L
= 10pF; ST = 1
C
L
= 5pF;
ST = 0
8
8
ns
56MHz, 2-pixel/clock, PIXS = 1
C
L
= 10pF; ST = 1
C
L
= 5pF;
ST = 0
8
7
R
CIP
ODCK Cycle Time
1
(1-pixels/clock)
8.9
50
ns
F
CIP
ODCK Frequency
1
(1-pixel/clock)
20
112
MHz
R
CIP
ODCK Cycle Time
1
(2-pixels/clock)
17.8
100
ns
F
CIP
ODCK Frequency
1
(2-pixel/clock)
10
56
MHz
R
CIH
ODCK High Time
1,5
65MHz, 1-pixel/clock, PIXS = 0
C
L
= 10pF; ST = 1
C
L
= 5pF;
ST = 0
3
ns
56MHz, 1-pixel/clock, PIXS = 1
C
L
= 10pF; ST = 1
C
L
= 5pF;
ST = 0
R
CIL
ODCK Low Time
1,5
65MHz, 1-pixel/clock, PIXS = 0
C
L
= 10pF; ST = 1
C
L
= 5pF;
ST = 0
3
ns
56MHz, 1-pixel/clock, PIXS = 1
C
L
= 10pF; ST = 1
C
L
= 5pF;
ST = 0
T
PDL
Delay from PD Low to high impedance outputs
1
10
ns
T
HSC
Link disabled (DE inactive) to SCDT low
1
100
ms
Link disabled (Tx power down) to SCDT low
6
250
T
FSC
Link enabled (DE active) to SCDT high
1
25
DE edges
T
ST
ODCK high to even data output
1
0.25
R
CIP
Notes:
1
Guaranteed by design.
2
Jitter defined as per DVI 1.0 Specification, Section 4.6 Jitter Specification.
3
Jitter measured with Clock Recovery Unit as per DVI 1.0 Specification, Section 4.7 Electrical Measurement Procedures.
4
The setup and hold timing for the data and controls relative to the ODCK rising edge (OCK_INV=1) is by design the same
as the falling edge timing.
5
Output clock duty cycle is independent of the differential input clock duty cycle and the IDCK duty cycle.
6
Measured when transmitter was powered down (see Si
I
/AN-0005 "PanelLink Basic Design/Application Guide," Section 2.4).
Silicon Image, Inc.
SiI151
SiI/DS-0007-E
4
Subject to Change without Notice
Timing Diagrams
10pF
SiI151
D
LHT
D
HLT
80%
80%
20%
20%
Figure 1. Digital Output Transition Times
R
CIH
R
CIL
R
CIP
V
IH
V
IH
V
IL
V
IL
Figure 2. Receiver Clock Cycle/High/Low Times
RX0
RX1
RX2
T
CCS
V
DIFF=0V
V
DIFF=0V
Figure 3. Channel-to-Channel Skew Timing
Output Timing
QE[23:0]/QO[23:0],
DE, HSYNC, VSYNC,
CTL[3:1]
ODCK
T
SOF
T
HOF
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
Figure 4. Output Data, DE, and Control Signals Setup/Hold Times to ODCK Falling Edge
PD
T
PDL
QE[23:0]/QO[23:0],
DE,
VSYNC,HSYNC,
CTL[3:1],PLLCK
V
IL
Figure 5. Output Signals Disabled Timing from PD Active
Silicon Image, Inc.
SiI151
SiI/DS-0007-E
5
Subject to Change without Notice
Output Timing (continued)
DE
SCDT
DE
SCDT
T
HSC
T
FSC
Figure 6. SCDT Timing from DE Inactive/Active
ODCK
DE
QE[23:0]
QO[23:0]
FIRST DATA
THIRD DATA
Internal
ODCK * 2
SECOND DATA
FOURTH DATA
T
ST
Figure 7. TFT 2-Pixels/Clock Staggered Output Timing Diagram
Output Pin Description
Pin Name
Pin #
Type
Description
QE23-
QE0
See
Si
I
151 Pin
Diagram
Out
Output Even Data[23:0] corresponds to 24-bit pixel data for 1-pixel/clock input mode and to the first 24-bit pixel
data for 2-pixels/clock mode.
Output data is synchronized with output data clock (ODCK).
Refer to the TFT and DSTN Signal Mapping application notes (Si
I
/AN-0007-A and Si
I
/AN-0008-A) which
tabulates the relationship between the input data to the transmitter and output data from the receiver.
A low level on PD or PDO will put the output drivers into a high impedance (tri-state) mode. A weak internal
pull-down device brings each output to ground.
QO23-
QO0
See
Si
I
151 Pin
Diagram
Out
Output Odd Data[23:0] corresponds to the second 24-bit pixel data for 2-pixels/clock mode.
During 1-pixel/clock mode, these outputs are driven low.
Output data is synchronized with output data clock (ODCK).
Refer to the TFT and DSTN Signal Mapping application notes (Si
I
/AN-0007-A and Si
I
/AN-0008-A) which
tabulates the relationship between the input data to the transmitter and output data from the receiver.
A low level on PD or PDO will put the output drivers into a high impedance (tri-state) mode. A weak internal
pull-down device brings each output to ground.
ODCK
44
Out
Output Data Clock. A low level on PD or PDO will put the output driver into a high impedance (tri-state) mode.
A weak internal pull-down device brings the output to ground.
DE
46
Out
Output Data Enable. This signal qualifies the active data area. A low level on PD or PDO will put the output
driver into a high impedance (tri-state) mode. A weak internal pull-down device brings the output to ground.
HSYNC
VSYNC
CTL1
CTL2
CTL3
48
47
40
41
42
Out
Out
Out
Out
Out
Horizontal Sync input control signal.
Vertical Sync input control signal.
General output control signal 1. This output is not powered down by PDO.
General output control signal 2.
General output control signal 3.
A low level on PD or PDO will put the output drivers (except CTL1 by PDO) into a high impedance (tri-state)
mode. A weak internal pull-down device brings each output to ground.
Silicon Image, Inc.
SiI151
SiI/DS-0007-E
6
Subject to Change without Notice
Configuration Pin Description
Pin Name
Pin #
Type
Description
OCK_INV
100
In
ODCK Polarity. A low level selects normal ODCK output. A high level (3.3V) selects inverted ODCK output. All
other outputs signals are not affected by this pin. They will maintain the same timing no matter the setting of
OCK_INV pin.
PIXS
4
In
Pixel Select. A low level indicates one pixel (up to 24-bits) per clock mode using QE[23:0]. A high level (3.3V)
indicates two pixels (up to 48-bits) per clock mode using QE[23:0] for first pixel and QO[23:0] for second pixel.
DFO
1
In
Output Data Format. This pin controls clock output format. A low level indicates that ODCK runs continuously for
TFT panel support. A high level indicates that ODCK is stopped (LOW) when DE is low for DSTN panel
support. Refer to the TFT and/or DSTN Signal Mapping application notes (Si
I
/AN-0007-A and Si
I
/AN-0008-A)
for a table on TFT or DSTN panel support.
STAG_OUT
7
In
A high level selects normal simultaneous outputs on all odd and even data lines. A low level selects staggered
output drive. This function is only available in 2-pixels per clock mode.
ST
3
In
Output Drive. A high level selects HIGH output drive strength. A low level selects LOW output drive strength.
Power Management Pin Description
Pin Name
Pin #
Type
Description
SCDT
8
Out
Sync Detect. A high level is outputted when DE is actively toggling indicating that the link is alive. A low level is
outputted when DE is inactive, indicating the link is down. Can be connected to PDO to power down the outputs
when DE is not detected. The SCDT output itself, however, remains in the active mode at all times.
PDO
9
In
Output Driver Power Down (active low). A high level indicates normal operation. A low level puts all the output
drivers only (except SCDT and CTL1) into a high impedance (tri-state) mode. A weak internal pull-down device
brings each output to ground. PDO is a sub-set of the PD description. The chip is not in power-down mode with this
pin.
There is an internal pull-up resistor that defaults the chip to normal operation if left unconnected. SCDT and CTL1
are not tri-stated by this pin.
PD
2
In
Power Down (active low). A high level (3.3V) indicates normal operation and a low level indicates power down
mode. During power down mode, all output buffers are disabled and brought low, all analog logic is powered down,
and all inputs are disabled.
Differential Signal Data Pin Description
Pin Name
Pin #
Type
Description
RX0+
RX0-
RX1+
RX1-
RX2+
RX2-
90
91
85
86
80
81
Analog
Analog
Analog
Analog
Analog
Analog
TMDS Low Voltage Differential Signal input data pairs.
RXC+
RXC-
93
94
Analog
Analog
TMDS Low Voltage Differential Signal input data pairs.
EXT_RES
96
Analog
Impedance Matching Control. Resistor value should be ten times the characteristic impedance of the cable. In the
common case of 50
transmission line, an external 500
resistor must be connected between AVCC and this
pin.
Reserved Pin Description
Pin Name
Pin #
Type
Description
RESERVED
99
In
Must be tied high for normal operation.
Power and Ground Pin Description
Pin Name
Pin #
Type
Description
VCC
6,38,67
Power
Digital Core VCC, must be set to 3.3V.
GND
5,39,68
Ground
Digital Core GND.
OVCC
18,29,43,57,78
Power
Output VCC, must be set to 3.3V.
OGND
19,28,45,58,76
Ground
Output GND.
AVCC
82,84,88,95
Power
Analog VCC must be set to 3.3V.
AGND
79,83,87,89,92
Ground
Analog GND.
PVCC
97
Power
PLL Analog VCC must be set to 3.3V.
PGND
98
Ground
PLL Analog GND.
Application Information
To obtain the most updated Application Notes and other useful information for your design application, please visit the Silicon Image web site
at www.siimage.com, or contact your local Silicon Image sales office.
Silicon Image, Inc.
SiI151
SiI/DS-0007-E
7
Subject to Change without Notice
Package Dimensions
100-pin TQFP Package Dimensions
Copyright Notice
This manual is copyrighted by Silicon Image, Inc. Do not reproduce, transform to any other format, or send/transmit any part of this documentation
without the express written permission of Silicon Image, Inc.
Trademark Acknowledgment
PanelLink and the PanelLink Digital Image Logo are registered trademarks of Silicon Image, Inc. Silicon Image, the Silicon Image Logo, and TMDS
are trademarks of Silicon Image, Inc. VESA is a registered trademark of Video Electronics Standards Association.
All other trademarks are the property of their respective holders.
Disclaimer
This document provides technical information for the user. Silicon Image, Inc. reserves the right to modify the information in this document as
necessary. The customer should make sure that they have the most recent data sheet version. Silicon Image, Inc. holds no responsibility for any
errors that may appear in this document. Customers should take appropriate action to ensure their use of the products does not infringe upon any
patents. Silicon Image, Inc. respects valid patent rights of third parties and does not infringe upon or assist others to infringe upon such rights.
Ordering Information
Part Number: Si
I
151CT100
1999 Silicon Image, Inc. 7/99 Si
I
/DS-0007-E
Silicon Image, Inc.
Tel:
408-873-3111
10131 Bubb Road
Fax:
408-873-0446
Cupertino, CA 95014
E-Mail: salessupport@siimage.com
USA
Web:
www.siimage.com
www.panellink.com
100-pin Plastic TQFP
SiINNN CT NNN
LNNNNN.NLLL
XXYY
X.XX
Lead Length
1.00mm
Lead Width
0.20mm
Lead Pitch
0.50mm
Body Thickness
1.05 mm max.
Package Height
1.20mm max.
Clearance
0.15mm max.
Body Size 14.00mm
Footprint 16.00mm
Body Size 14.00mm
Footprint 16.00mm
Device #
Lot #
Date Code #
SiI Rev. #
12.00mm
12.00mm
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