DB08-000200-00
April 2003
1 of 18
Copyright 2003 by LSI Logic Corporation. All rights reserved.
RapidChipTM L79301
StreamSliceTM Configurable
10 Gbit/s Platform
Advance Datasheet
The StreamSlice L79301 (
Figure 1
) is the first platform of the LSI Logic
RapidChip configurable-logic family. It greatly reduces the NRE and
development costs usually associated with cell-based logic, while
maintaining a significant cost advantage over FPGAs. The L79301
provides the diffused cores needed for high-speed networking
applications along with a large amount of customer-configurable logic.
There are 12 GigaBlaze
channels operating at 1.0625 Gbit/s to 3.1875
Gbit/s each, 40 HyperPHY channels operating at 622 Mbits/s to 832
Mbits/s each, and an 80-bit DDR interface. The device also contains 2.2
Mbits of embedded memory and 3 million gates of customer-configurable
logic.
LSI Logic Corporation provides RapidReadyTM CoreWare
and IP blocks
that combine the diffused-embedded cores with the configurable logic to
address a number of high-performance and standards-based
applications. These include the10 Gbit Ethernet XGXS, SPI4.2 interface,
DDR-SDRAM controller, and others. In addition, customers can add their
own IP for differentiation. The combination of diffused and soft IP, along
with LSI Logic sophisticated RapidChip methodology makes it easy to
generate a set of metal layers implementing a customer's unique system
on a chip.
Figure 1
L79301 StreamSlice Configurable Platform
2 of 18
RapidChipTM L79301 StreamSliceTM Configurable 10 Gbit/s Platform
DB08-000200-00
April 2003
Copyright 2003 by LSI Logic Corporation. All rights reserved.
The StreamSlice platform provides a basis for a wide range of
differentiated designs. As shown in
Figure 2
, StreamSlice can be
configured for specific roles on different linecards within the same
system. These applications are suitable to any high-throughput data
communication system (Router, Switch, or Aggregation System).
Figure 2
Typical L79301 StreamSlice Applications
StreamSlice Features
ASIC performance
Quick turnaround to market
Three million gates of configurable logic. Configuration is in five
layers of metal
12 Ultra-high speed GigaBlaze SERDES serial interfaces
Data rate: 1.0625 Gbit/s to 3.1875 Gbit/s each
Point to point full duplex
10 Gigabit
Ethernet
Backplane Interconnect
XENPAK
Receiver
10 Gigabit
Ethernet
WAN-PHY
L79301
StreamSlice
10Gbit/s
Switch Fabric
3.2 Gigabit
Crosspoint
Packet
Traffic
OC192c
PoS
Backplane Interconnect
OC192
Network
Processor
L79301
StreamSlice
10Gbit/s
10 Gigabit
Ethernet
XAUI Interface
XENPAK
Receiver
L79301
StreamSlice
10 Gigabit
Network
Processor
10Gbit/s
OC192
TDM Backplane Interface
OC192
Receiver
Mux/Demux
L79301
StreamSlice
OC192
Framer
OC192
Receiver
Mux/Demux
OC192
Grooming
Switch
TDM
Traffic
10Gbit/s
RapidChipTM L79301 StreamSliceTM Configurable 10 Gbit/s Platform
3 of 18
DB08-000200-00
April 2003
Copyright 2003 by LSI Logic Corporation. All rights reserved.
Programmable internal impedance for matching to external
devices
XAUI, Gigabit Ethernet, and Fibre Channel compliant
40 HyperPHY high-speed interfaces
622-Mbits/s to 832 Mbits/s each
Full duplex operation
Typical 85 mW per channel @ 622 Mbits/s
Receives data reliably even with long sequences of data without
transitions
Supports SPI4 Phase 2
80-Bit DDR SDRAM interface
High-performance 333 Mbits/s per pin
Delay-time settings in increments of 20 ps
Internal scan
Supports point to point and Multi-drop configurations
6 PLLs
Four @ 100 MHz to 500 MHz
Two @ 600 MHz to 1250 MHz
2.2 Mbit Diffused SRAM
333 user configurable I/Os
0.18-micron process: 1.8 V
1509-pin FPBGA FlipChipTM
Overview
The L79301 consists of three million usable gates of configurable logic
embedded with a set of diffused cores. The cores are
12 GigaBlaze high-speed serial channels operating between 1.0625
Gbits/s and 3.1875 Gbits/s
40 HyperPHY channels operating at 622-Mbits/s to 832-Mbits/s
an 80-bit DDR interface
4 of 18
RapidChipTM L79301 StreamSliceTM Configurable 10 Gbit/s Platform
DB08-000200-00
April 2003
Copyright 2003 by LSI Logic Corporation. All rights reserved.
dual-port SRAM
single-port SRAM
6 PLLs
The cores are not configurable.
Customizable Logic Fabric
The Transistor Fabric provides the basis for the implementation of the
user's logic. An R-Cell is the basic unit within the Transistor Fabric; it is
made up of specially sized "N" and "P" type transistors for maximum
flexibility and performance. R-Cells are diffused in a regular pattern
throughout the slice and can implement memory as well as logic
structures efficiently. They are configured in up to five layers of metal to
create the full range of logic functions available within the RapidChip
logic cell library. The library contains over 400 cells, with a range of drive
strengths. R-Cells can also be configured efficiently as small memory
blocks, further adding flexibility to a designer's memory implementation.
Transistors within the Fabric are activated only when they are part of the
implementation of a function used in the design, ensuring the most
power-efficient solution.
The L79301 contains 3 million gates of user-configurable logic. The
maximum frequency for user logic is 166 MHz.
Configurable I/Os
The L79301 provides designers with access to a broad range of user-
configurable I/O types. Configured by patterning of metal interconnect,
the I/O buffers are compact yet address the majority of industry-standard
applications without overheads associated with reprogrammability.
Through optimization of package power domains and slice-specific
VDD/VSS placements, the configuration I/O resources enable designers
to assign buffers with fine granularity. The I/O power plane grouping are
partitioned to a set a banks as illustrated in
Figure 3
. All I/Os within a
bank share the same VDD.
Table 1
lists the available I/O bus types and
drive strengths for I/Os
RapidChipTM L79301 StreamSliceTM Configurable 10 Gbit/s Platform
5 of 18
DB08-000200-00
April 2003
Copyright 2003 by LSI Logic Corporation. All rights reserved.
.
Table 1
I/O Configuration List
I/O Signaling
Standard
Type
VDD
Drive Strength
(CMOS) LVTTL
Bidirectional
3.3 V
12 mA
Bidirectional
3.3 V
8 mA
Bidirectional
3.3 V
4 mA
Bidirectional
3.3 V
2 mA
Bidirectional
2.5 V
12 mA
Bidirectional
2.5 V
8 mA
Bidirectional
2.5 V
4 mA
Bidirectional
2.5 V
2 mA
Bidirectional
1.8 V
12 mA
Bidirectional
1.8 V
8 mA
Bidirectional
1.8 V
4 mA
Bidirectional
1.8 V
2 mA
Bidirectional
Differential
2.5 V
50
SSTL-2
Bidirectional
2.5 V
Class I
Bidirectional
2.5 V
Class II
LVDS
Differential Output
2.5 V
4 mA
Differential Input
2.5 V
HSTL- Single
Ended
Bidirectional
1.5 V
Class I (8 mA)
Bidirectional
1.5 V
Class II (16 mA)
Bidirectional
1.5 V
Class III (24 mA)
LVPECL
Input
3.3 V
PCI-66
Bidirectional
3.3 V
PDF 
ZIP