V385
V385 Datasheet
1
8/30/2004
Revision 1.3
Integrated Circuit Systems 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com
8-B
IT
LVDS T
RANSMITTER
FOR
V
IDEO
General Description
The V385 transmitter converts 28 bits of 3.3 V
CMOS/TTL into 4 Low Voltage Differential Signaling
(LVDS) data streams while the transmit clock input is
transmitted in parallel with the data streams over a fifth
LVDS link. The V385 can be programmed for rising
edge or falling edge clocks through pin R_FB.
ICS manufactures a large variety of video application
devices. Consult ICS for all of your video application
requirements.
Pin Assignment
Features
Packaged in a 56-pin TSSOP (Pb free available)
Convert 28 bits of 3.3 V CMOS/TTL into 4 LVDS
streams
Up to 2.38 Gbps throughput or 297.5 Megabytes/sec
bandwidth
Wide clock frequency range from 20 MHz to 85 MHz
Supports VGA, SVGA, XGA, and SXGA
LVDS voltage swing of 350 mV for low EMI
On-chip PLL requires no external components
Single 3.3 V low-power CMOS design
Programmable rising or falling edge strobe
Power-down control function
Compatible with TIA/EIA-644 LVDS standards
Pin and function compatible with the National
DS90C385, TI SN65LVDS93 and THine
THC63LVDM83
Block Diagram
12
1
11
2
10
VCC
3
9
TxIN5
4
5
6
7
8
16
15
14
13
56-pin TSSOP
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
TxIN6
TxIN7
TxIN8
TxIN9
TxIN10
GND
VCC
TxIN11
TxIN12
TxIN13
GND
TxIN14
TxIN15
TxIN16
R_FB
TxIN17
TxIN18
TxIN19
GND
TxIN20
TxIN21
TxIN22
TxIN23
TxIN24
TxIN25
VCC
GND
TxIN26
PWRDWN
PLL_GND
PLL_GND
PLL_VCC
LVDS_GND
LVDS_GND
LVDS_GND
LVDS_VCC
TxOUT3+
TxOUT3-
TxCLKOUT+
TxCLKOUT-
TxOUT2+
TxOUT2-
TxCLKIN
TxOUT1+
TxOUT1-
TxOUT0+
TxOUT0-
TxIN27
TxIN0
TxIN1
GND
TxIN2
TxIN3
TxIN4
TTL to
LVDS
TxOUT0+
PLL
TxOUT0-
TxOUT1+
TxOUT1-
TxOUT2+
TxOUT2-
TxOUT3+
TxOUT3-
TxCLKOUT+
TxCLKOUT-
24
Red, Green, Blue
CLOCK
PWRDWN
R_FB
CONTROL
DATA ENABLE
VSYNC
HSYNC
8-B
IT
LVDS T
RANSMITTER
FOR
V
IDEO
V385
V385 Datasheet
2
8/30/2004
Revision 1.3
Integrated Circuit Systems 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com
Pin Descriptions
External Components
The V385 requires no external components.
Pin
Type
Pin
Count
Pins
Pin Description/Name
VCC
5
1, 9, 26,34, 44
3 pins for Logic and Data TTL inputs (VCC, 3.3 V power supply).
1 pins for PLL (PLL_VCC).
1 pin for LVDS (LVDS_VCC).
GND
10
5, 13, 21, 29, 33, 35,
36, 43, 49, 53
5 pins for Logic and Data TTL inputs(GND).
2 pins for PLL (PLL_GND).
3 pins for LVDS input pairs (LVDS_GND).
CMOS/TTL
28
2, 3, 4, 6, 7, 8, 10, 11,
12, 14, 15, 16, 18, 19,
20, 22, 23, 24, 25, 27,
28, 30, 50, 51, 52, 54,
55, 56
Parallel digital video input pins (TxIN0..27).
LVDS Differential
Ouput
10
37, 38, 39, 40, 41, 42,
45, 46, 47, 48
8 pins (4 pairs) for Serialized video data (TxOUT0..3+/-).
2 pins (1 pair) for clock outputs (TxCLKOUT+/-)
CMOS/TTL
1
31
Clock input (TxCLKIN)
Prgrammable
Strobe Select
1
17
Programmable strobe select input pin (R_FB). High = rising
edge; Low = falling edge.
Power Down
1
32
Active low (PWRDWN). Power-down tri-states outputs.
8-B
IT
LVDS T
RANSMITTER
FOR
V
IDEO
V385
V385 Datasheet
3
8/30/2004
Revision 1.3
Integrated Circuit Systems 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the V385. These ratings, which
are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Recommended Operation Conditions
SMT IR-Profile
Item
Rating
Supply Voltage, VDD
-0.3 V to +4 V
All Inputs and Outputs
-0.3 V to VCC+0.3 V
Electrostatic Discharge (EIAJ, 0
, 200 pF)
> 500 V
Ambient Operating Temperature
0 to +70
C
Storage Temperature
-65 to +150
C
Junction Temperature
150
C
Soldering Temperature
230
C
Parameter
Min.
Typ.
Max.
Units
Ambient Operating Temperature
0
+70
C
Power Supply Voltage (measured in respect to GND)
3.0
3.3
3.6
V
0
30
60
90
120
150
180
210
240
270
300
0
30
60
90
120
150
180
210
240
270
300
330
360
390
TIME(SECS)
TE
M
P
o
C
Tg
Peak Temp.
23010
o
C
Melting
Cooling
Preheat
Inital
Sn/Pb :63/37 183
o
C
8-B
IT
LVDS T
RANSMITTER
FOR
V
IDEO
V385
V385 Datasheet
4
8/30/2004
Revision 1.3
Integrated Circuit Systems 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com
Electrical Characteristics
VDD=3.3 V 10%,
Ambient temperature 0 to +70
C
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Freq.
CMOS/TTL DC Specifications
Input High Voltage
V
IH
2.00
VCC
V
Input Low Voltage
V
IL
GND
0.80
V
Input Current
I
IN
GND<VIN<VCC
10
A
Power-down Current
I
PD
No switching for input pins
10
A
LVDS DC Specifications
Differential Output Voltage
V
OD
R
L
= 100 ohms
250
345
450
mV
Change in V
OD
Between
Complimentary Output States
DV
OD
35
mV
Common Mode Voltage
V
OC
1.125
1.250
1.375
V
Change in V
OC
Between
Complimentary Output States
DV
OC
35
mV
Output Short Circuit Current
I
OS
V
OD
=0V
3.5
5
mA
Output Tri-State Current
I
OZ
Power Down#=0V
12
A
Transmitter Supply Current
Transmitter Supply Current
(worst case)
I
TCCW
R
L
= 100 ohms, C
L
=5 pF,
worst case pattern
mA
65 MHz
mA
85 MHz
Transmitter Supply Current
(16 Grayscale)
I
TCCG
R
L
= 100 ohms, C
L
=5 pF,
16 Grayscale pattern
mA
65 MHz
mA
85 MHz
Recommended Transmitter Input Characteristics
TxCLK IN Transition Time
TCIT
5
ns
TxCLK IN Period
TCIP
11.76
T
50
ns
TxCLK IN High Time
TCIH
0.35T
0.5T
0.65T
ns
TxCLK IN Low Time
TCIL
0.35T
0.5T
0.65T
ns
TxIN Transition Time
TXIT
1.5
6
ns
Transmitter Switching Characteristics
LVDS Low-to-High Time
LLHT
0.75
1.5
ns
LVDS High-to-Low Time
LHLT
0.75
1.5
ns
Transmitter Output Pulse
Position
TPPos0
Bit0
-0.2
0
0.2
0.2
85 MHz
TPPos1
Bit1
T/7-0.2
T/7
T/7+0.2
ns
85 MHz
TPPos2
Bit2
2T/7-0.2
2T/7
2T/7+0.2
ns
85 MHz
TPPos3
Bit3
3T/7-0.2
3T/7
3T/7+0.2
ns
85 MHz
TPPos4
Bit4
4T/7-0.2
4T/7
4T/7+0.2
ns
85 MHz
TPPos5
Bit5
5T/7-0.2
5T/7
5T/7+0.2
ns
85 MHz
TPPos6
Bit6
6T/7-0.2
6T/7
6T/7+0.2
ns
85 MHz
Transmitter Phase Loop Set
TPLLS
10
ms
TxIN Setup to TxCLK IN
TSTC
2.5
ns
8-B
IT
LVDS T
RANSMITTER
FOR
V
IDEO
V385
V385 Datasheet
5
8/30/2004
Revision 1.3
Integrated Circuit Systems 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com
Thermal Characteristics
AC Timing Diagrams
Figure AC1. Transmitter Setup/Hold and High/Low Times (Falling Edge Strobe or R_FB=0)
Figure AC2. Clock IN to Clock OUT Delay (Rising Edge Strobe or R_FB=1)
TxIN Hold to TxCLK IN
THTC
0
ns
TxCLK IN to TxCLK OUT
Delay
TCCD
1T/7+0.8
1T/7+3.4
ns
Transmitter Jitter
Cycle-to-Cycle
TJCC
350
370
ps
40 MHz
210
230
ps
65 MHZ
110
150
ps
85 MHz
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Thermal Resistance Junction to Ambient
JA
Still air
84
C/W
JA
1 m/s air flow
76
C/W
JA
3 m/s air flow
67
C/W
Thermal Resistance Junction to Case
JC
50
C/W
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Freq.
TxCLK IN
TxIN
TCIL
THTC
TCIH
TCIH
TCIP
TxCLK OUT+
TxCLK IN
TCCD
TxCLK OUT-
8-B
IT
LVDS T
RANSMITTER
FOR
V
IDEO
V385
V385 Datasheet
6
8/30/2004
Revision 1.3
Integrated Circuit Systems 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com
Figure AC3. Phase Lock Loop Set Time
Figure AC4. Transmitter Device Transition Times and Load
TxCLK IN
VCC
PWRDWN#
Unknown
TPLLS
TTL Input
TCIT
5 pF
100 ohms
LVDS Output
TCIT
LLHT
LLHT
20%
20%
10%
10%
80%
80%
90%
90%
8-B
IT
LVDS T
RANSMITTER
FOR
V
IDEO
V385
V385 Datasheet
7
8/30/2004
Revision 1.3
Integrated Circuit Systems 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com
Figure AC5. Transmitter LVDS Output Pulse Position Measurement
TxIN27-1
TxIN27-1
TxOUT3
TxIN23
TxIN17
TxIN16
TxIN11
TxIN10
TxIN5
TxIN19-1
TxIN20-1
TxIN26
TxIN25
TxIN24
TxIN22
TxIN21
TxIN20
TxIN8-1
TxIN9-1
TxIN18
TxIN15
TxIN14
TxIN13
TxIN12
TxIN9
TxIN0-1
TxIN1-1
TxIN7
TxIN6
TxIN4
TxIN3
TxIN2
TxIN1
TxOUT2
TxOUT1
TxOUT0
TPPos0
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
TxCLK OUT+
8-B
IT
LVDS T
RANSMITTER
FOR
V
IDEO
V385
V385 Datasheet
8
8/30/2004
Revision 1.3
Integrated Circuit Systems 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com
Package Outline and Package Dimensions
(56-pin TSSOP)
Package dimensions are kept current with JEDEC Publication No. 95
Ordering Information
"LF" denotes Pb (lead) free annealed packaging.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no
responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other
circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as
those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without
additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant
any ICS product for use in life support devices or critical medical instruments.
Part / Order Number
Marking
Shipping Packaging
Package
Temperature
V385G
V385G
Tubes
56-pin TSSOP
0 to +70
C
V385GTR
V385G
Tape and Reel
56-pin TSSOP
0 to +70
C
V385GLF
V385GLF
Tubes
56-pin TSSOP
0 to +70
C
V385GLFTR
V385GLF
Tape and Reel
56-pin TSSOP
0 to +70
C
INDEX
AREA
1 2
56
D
E1
E
SEATING
PLANE
A
1
A
A
2
e
- C -
b
aaa
C
c
L
Millimeters
Inches
Symbol
Min
Max
Min
Max
A
--
1.20
--
0.047
A1
0.05
0.15
0.002
0.006
A2
0.80
1.05
0.032
0.041
b
0.17
0.27
0.007
0.011
C
0.09
0.20
0.0035
0.008
D
13.90
14.10
0.547
0.555
E
8.10 BASIC
0.319 BASIC
E1
6.00
6.20
0.236
0.244
e
0.50 BASIC
0.020 BASIC
L
0.45
0.75
0.018
0.030
a
0
8
0
8
aaa
--
0.10
--
0.004
PDF 
ZIP