Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

Features

· 16,384-channel x 16,384-channel non-blocking

unidirectional switching.The Backplane and Local

inputs and outputs can be combined to form a

non-blocking switching matrix with 64 input

streams and 64 output streams

· 8,192-channel x 8,192-channel non-blocking

Backplane input to Local output stream switch

· 8,192-channel x 8,192-channel non-blocking

Local input to Backplane output stream switch

· 8,192-channel x 8,192-channel non-blocking

Backplane input to Backplane output switch

· 8,192-channel x 8,192-channel non-blocking

Local input to Local output stream switch

· Backplane port accepts 32 input and 32 output

ST-BUS streams with fixed data rates of

2.048Mbps, 4.096Mbps, 8.192Mbps or

16.384Mbps

· Local port accepts 32 input and 32 output ST-

BUS streams with fixed data rates of 2.048Mbps,

4.096Mbps, 8.192Mbps or 16.384Mbps

· Exceptional input clock jitter tolerance (17ns)

· Per-stream bit delay for Local and Backplane

input streams

· Per-stream advancement for Local and Backplane

output streams

· Constant 2-frame throughput delay for frame

integrity

· Per-channel high impedance output control for

Local and Backplane streams

· Per-channel driven-high output control for Local

and Backplane streams

· Per-channel message mode for Local and

Backplane output streams

· Connection memory block programming for fast

device initialization

November 2003

Ordering Information

ZL50062GAC

256-Ball PBGA

ZL50064QCC

256-Pin LQFP

-40

C to +85

ZL50062/4

16K-Channel Digital Switch with High Jitter

Tolerance, Single Rate (2, 4, 8,

or 16Mbps), and 64 Inputs and 64 Outputs

Data Sheet

Figure 1 - ZL50062/4 Functional Block Diagram

Backplane Data Memories

(8,192 channels)

DS CS R/W

A14-0

DTA

D15-0

Test Port

Microprocessor Interface

and Internal Registers

SS (GND)

DD_CORE

TDi TDo TCK TRST

TMS

LSTo0-31

(8,192 locations)

RESET

Local

Interface

Connection Memory

BSTi0-31

Input

Timing Unit

FP8i

PLL

LSTi0-31

Interface

Backplane

BSTo0-31

Local

C8i

DD_IO

ODE

C8o

C16o

FP8o

FP16o

DD_PLL

Output

Timing

Unit

(8,192 locations)

Connection Memory

Backplane

Interface

Local

Local Data Memories

(8,192 channels)

BORS

LORS

ZL50062/4

Data Sheet

Zarlink Semiconductor Inc.

Device Overview

The ZL50062 and ZL50064 are two different packages of the same device. They have the same functionality
except that ZL50064 does not have 16.384MHz output clock and frame pulse (C16o and FP16o) due to package
differences. The ZL50062/4 has two data ports, the Backplane and the Local port. The device can operate at four
different data rates, 2.048Mbps, 4.096Mbps, 8.192Mbps or 16.384Mbps. All 64 input and 64 output streams must
operate at the same data rate.

The ZL50062/4 contains two data memory blocks (Backplane and Local) to provide the following switching path
configurations:

· Input-to-Output Unidirectional, supporting 16K x 16K switching

· Backplane-to-Local Bi-directional, supporting 8K x 8K data switching,

· Local-to-Backplane Bi-directional, supporting 8K x 8K data switching,

· Backplane-to-Backplane Bi-directional, supporting 8K x 8K data switching.

· Local-to-Local Bi-directional, supporting 8K x 8K data switching.

The device contains two connection memory blocks, one for the Backplane output and one for the Local output.
Data to be output on the serial streams may come from either of the data memories (Connection Mode) or directly
from the connection memory contents (Message Mode).

In Connection Mode, the contents of the connection memory define, for each output stream and channel, the
source stream and channel (stored in data memory) to be switched.

In Message Mode, microprocessor data can be written to the connection memory for broadcast on the output
streams on a per channel basis. This feature is useful for transferring control and status information to external
circuits or other ST-BUS devices.

The device uses a master frame pulse (FP8i) and master clock (C8i) to define the input frame boundary and timing
for both the Backplane port and the Local port. The device will automatically detect whether an ST-BUS or a GCI-
Bus style frame pulse is being used. There is a two-frame delay from the time RESET is de-asserted to the
establishment of full switch functionality. During this period, the input frame pulse format is determined before
switching begins.

The device provides FP8o, FP16o, C8o and C16o outputs to support external devices connected to the outputs of
the Backplane and Local ports.

A non-multiplexed Motorola microprocessor port allows programming of the various device operation modes and
switching configurations. The microprocessor port provides access for Register read/write, Connection Memory
read/write and Data Memory read-only operations. The port has a 15-bit address bus, 16-bit data bus and 4 control
signals. The microprocessor may monitor channel data in the Backplane and Local data memories.

The mandatory requirements of the IEEE-1149.1 (JTAG) standard are fully supported via a dedicated test port.

The ZL50062 and ZL50064 are each available in one package:

· ZL50062: a 17mm x 17mm body, 1mm ball-pitch, 256-PBGA.

· ZL50064: a 28mm x 28mm body, 0.40mm pin-pitch, 256-LQFP.

ZL50062/4

Data Sheet

Table of Contents

Zarlink Semiconductor Inc.

1.0 Unidirectional and Bi-directional Switching Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

1.1 Flexible Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

1.1.1 Non-Blocking Unidirectional Configuration (Typical System Configuration) . . . . . . . . . . . . . . . . . . 18
1.1.2 Non-Blocking Bi-directional Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.1.3 Blocking Bi-directional Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.1 Switching Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.1.1 Unidirectional Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.1.2 Backplane-to-Local Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.1.3 Local-to-Backplane Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.1.4 Backplane-to-Backplane Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.1.5 Local-to-Local Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.1.6 Port Data Rate Modes and Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.1.6.1 Local Output Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.1.6.2 Backplane Output Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.2 Frame Pulse Input and Master Input Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3 Input Frame Pulse and Generated Frame Pulse Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.4 Jitter Tolerance Improvement Circuit - Frame Boundary Discriminator. . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.5 Input Clock Jitter Tolerance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.0 Input and Output Offset Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.1 Input Offsets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.1.1 Input Bit Delay Programming (Backplane and Local Input Streams) . . . . . . . . . . . . . . . . . . . . . . . . 23

3.2 Output Advancement Programming (Backplane and Local Output Streams) . . . . . . . . . . . . . . . . . . . . . . 25

4.0 Port high impedance Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.0 Data Delay Through the Switching Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.0 Microprocessor Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.0 Device Power-up, Initialization and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.1 Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.2 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

8.0 Connection Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

8.1 Local Connection Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8.2 Backplane Connection Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8.3 Connection Memory Block Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

8.3.1 Memory Block Programming Procedure: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

9.0 Memory Built-In-Self-Test (BIST) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10.0 JTAG Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

10.1 Test Access Port (TAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10.2 TAP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

10.2.1 Test Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10.2.2 Test Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

10.2.2.3 The Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

10.3 Boundary Scan Description Language (BSDL) File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

11.0 Memory Address Mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

11.1 Local Data Memory Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
11.2 Backplane Data Memory Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
11.3 Local Connection Memory Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
11.4 Backplane Connection Memory Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

12.0 Internal Register Mappings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
13.0 Detailed Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

ZL50062/4

Data Sheet

Table of Contents

Zarlink Semiconductor Inc.

13.1 Control Register (CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
13.2 Block Programming Register (BPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
13.3 Local Input Bit Delay Registers (LIDR0 to LIDR31). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

13.3.1 Local Input Delay Bits 4-0 (LID[4:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

13.4 Backplane Input Bit Delay Registers (BIDR0 to BIDR31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

13.4.1 Backplane Input Delay Bits 4-0 (BID[4:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

13.5 Local Output Advancement Registers (LOAR0 to LOAR31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

13.5.1 Local Output Advancement Bits 1-0 (LOA1-LOA0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

13.6 Backplane Output Advancement Registers (BOAR0 - BOAR31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

13.6.1 Backplane Output Advancement Bits 1-0 (BOA1-BOA0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

13.7 Memory BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
13.8 Bit Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
13.9 Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

14.0 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
15.0 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

ZL50062/4

Data Sheet

List of Figures

Zarlink Semiconductor Inc.

Figure 1 - ZL50062/4 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - ZL50064 LQFP Connections (256 LQFP, 28mm x 28mm) Pin Diagram

(as viewed through top of package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 3 - ZL50062 PBGA Connections (256 PBGA, 17mm x 17mm) Pin Diagram

(as viewed through top of package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 4 - 16,384 x 16,384 Channels (16Mbps), Unidirectional Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 5 - 8,192 x 8,192 Channels (16Mbps), Bi-directional Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 6 - 12,288 by 4,096 Channels Blocking Bi-directional Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 7 - ST-BUS and GCI-Bus Input Timing Diagram for Different Data Rates . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 8 - Input and Output Frame Pulse Alignment for Different Data Rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 9 - Backplane and Local Input Bit Delay Timing Diagram for Data Rate of 16Mbps. . . . . . . . . . . . . . . . . . 24
Figure 10 - Backplane and Local Input Bit Delay or Sampling Point Selection Timing Diagram for Data Rate of

8Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 11 - Local and Backplane Output Advancement Timing Diagram for Data Rate of 16Mbps . . . . . . . . . . . 26
Figure 12 - Data Throughput Delay with Input Ch0 Switched to Output Ch0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 13 - Data Throughput Delay with Input Ch0 Switched to Output Ch13. . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 14 - Data Throughput Delay with Input Ch13 Switched to Output Ch0. . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 15 - Hardware RESET De-assertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 16 - Frame Boundary Conditions, ST-BUS Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 17 - Frame Boundary Conditions, GCI-Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 18 - Input and Output Clock Timing Diagram for ST-BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 19 - Input and Output Clock Timing Diagram for GCI-Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 20 - ST-BUS Local/Backplane Data Timing Diagram (8Mbps, 4Mbps, 2Mbps) . . . . . . . . . . . . . . . . . . . . . 57
Figure 21 - ST-BUS Local/Backplane Data Timing Diagram (16Mbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 22 - GCI-Bus Local/Backplane Data Timing Diagram (8Mbps, 4Mbps, 2Mbps) . . . . . . . . . . . . . . . . . . . . . 59
Figure 23 - GCI-Bus Local/Backplane Data Timing Diagram (16Mbps). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 24 - Serial Output and External Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 25 - Output Driver Enable (ODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 26 - Motorola Non-Multiplexed Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 27 - JTAG Test Port Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

ZL50062/4

Data Sheet

List of Tables

Zarlink Semiconductor Inc.

Table 1 - Local and Backplane Output Enable Control Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 2 - Variable Range for Input Streams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 3 - Variable Range for Output Streams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 5 - Local Connection Memory in Block Programming Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 6 - Backplane Connection Memory in Block Programming Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 4 - Local and Backplane Connection Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 7 - Address Map for Data and Connection Memory Locations (A14 = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 8 - Local Data Memory (LDM) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 9 - Backplane Data Memory (BDM) Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 10 - LCM Bits for Source-to-Local Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 11 - BCM Bits for Source-to-Backplane Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 12 - Address Map for Registers (A14 = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 13 - Control Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 14 - Block Programming Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 15 - Local Input Bit Delay Register (LIDRn) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 16 - Local Input Bit Delay and Sampling Point Programming Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 17 - Backplane Input Bit Delay Register (BIDRn) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 18 - Backplane Input Bit Delay and Sampling Point Programming Table. . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 19 - Local Output Advancement Register (LOAR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 20 - Local Output Advancement (LOAR) Programming Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 21 - Backplane Output Advancement Register (BOAR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 22 - Backplane Output Advancement (BOAR) Programming Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 23 - Memory BIST Register (MBISTR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 24 - Bit Rate Register (BRR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 25 - Device Identification Register (DIR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

ZL50062/4

Data Sheet

Zarlink Semiconductor Inc.

Figure 2 - ZL50064 LQFP Connections (256 LQFP, 28mm x 28mm) Pin Diagram

(as viewed through top of package)

256 PIN LQFP

152

154

156

158

160

162

164

166

168

170

172

174

176

178

180

22 24 26 28 30

i
2

I
2

I
3

i
2

DD_I

BST

i
3

DD_CO

D15

D13

D14 D11

D12 D10

DD_I

DD_CO

D7 D6 D5

D4 D3 D2 D1

120

102

104

106

108

110

114

116

118

112

52 54 56

58 60

100

132

134

136

138

140

142

144

146

148

150

LSTi14

GND

VDD_IO

LSTi13

VDD_CORE

GND

LSTi11

LSTi12

LSTi9

LSTi5

LSTi6

LSTi3

LSTi4

LSTi1

LSTi0

LSTi2

LORS

LSTo31

LSTo30

VDD_IO

GND

VDD_CORE

LSTo29

LSTo28

LSTo27

LSTo26

LSTo25

LSTo24

LSTo23

LSTo22

VDD_IO

GND

LSTo21

LSTo20

LSTo19

LSTo18

LSTo17

LSTo16

LSTo15

LSTo14

VDD_IO

GND

VDD_CORE

LSTo13

LSTo11

LSTo12

LSTo9

LSTo10

LSTo7

LSTo8

VDD_IO

LSTo6

GND

VDD_CORE

LSTo5

DD_I

CS DT

SET

DD_CO

DD_I

D_CO

RE C8i

C8o FP

i
31

i
29

DD_I

i
27

i
28

i
25

i
26

i
23

i
24

i
21

i
22

i
19

DD_

62 64

122

124

126

128

182

184

186

188

190

DD_I

LSTi10

LSTi7

LSTi8

LSTo4

LSTo3

LSTo2

A0 A3

DD_CO

DD_I

A6 A7

A9 A1

BSTi24

BSTi22

BSTi21

BSTi23

BSTi19

BSTi20

BSTi17

BSTi18

BSTi16

BSTi15

VDD_IO

BSTi13

BSTi14

BSTi11

BSTi9

BSTi12

BSTi10

BSTi8

BSTi7

BSTi6

BSTi5

BSTi4

BSTi3

BSTi2

BSTi1

BSTi0

VDD_CORE

GND

VDD_IO

BORS

BSTo31

BSTo30

BSTo29

BSTo28

BSTo27

BSTo26

BSTo25

BSTo24

VDD_CORE

GND

VDD_IO

BSTo23

BSTo21

BSTo22

BSTo19

BSTo20

BSTo17

VDD_CORE

GND

BSTo15

BSTo13

BSTo14

VDD_CORE

GND

BSTo12

BSTo11

BST010

202

220

218

216

214

212

208

206

204

210

222

240

238

236

234

232

228

226

224

230

242

256

254

252

248

246

244

250

200

198

196

194

VDD_IO

BSTo18

BSTo16

(TOP VIEW)

i
2

DD_P

i
3

i
20

i
18

i
1

i
16

i
15

ZL50062/4

Data Sheet

Zarlink Semiconductor Inc.

Figure 3 - ZL50062 PBGA Connections (256 PBGA, 17mm x 17mm) Pin Diagram

(as viewed through top of package)

Pinout Diagram: (as viewed through top of package)

A1 corner identified by metallized marking

R/W

IC_

OPEN

IC_

OPEN

IC_

OPEN

IC_

OPEN

IC_

OPEN

IC_

OPEN

IC_

OPEN

IC_

OPEN

BSTo0

BSTo1

BSTo2

BSTo3

ODE

RESET

TMS

LSTo0

LSTo1

LSTo2

LSTo3

BSTo4

BSTo5

BSTo6

BSTo7

A10

A11

A12

A13

A14

DTA

TDi

TDo

LSTo4

LSTo5

LSTo6

LSTo7

BSTo8

BSTo9

BSTo10 BSTo11

BORS IC_GND IC_GND IC_GND IC_GND

TCK

TRST

LORS

LSTo8

LSTo9

LSTo10 LSTo11

BSTo12 BSTo13 BSTo14 BSTo15 VDD_IO VDD_IO

VDD_

CORE

VDD_

CORE

VDD_

CORE

VDD_

CORE

VDD_IO VDD_IO LSTo12 LSTo13 LSTo14 LSTo15

BSTo16 BSTo17 BSTo18 BSTo19 VDD_IO

VDD_

CORE

GND

VDD_

CORE

VDD_IO LSTo16 LSTo17 LSTo18 LSTo19

BSTo20 BSTo21 BSTo22 BSTo23 VDD_IO

GND

VDD_IO LSTo20 LSTo21 LSTo22 LSTo23

BSTo24 BSTo25 BSTo26 BSTo27 VDD_IO

GND

VDD_IO LSTo24

LST25

LSTo26 LSTo27

BSTo28 BSTo29 BSTo30 BSTo31

VDD_

CORE

GND

VDD_

CORE

LSTo28 LSTo29 LSTo30 LSTo31

BSTi0

BSTi1

BSTi2

BSTi3

VDD_

CORE

GND

VDD_

CORE

LSTi0

LSTi1

LSTi2

LSTi3

BSTi4

BSTi5

BSTi6

BSTi7

VDD_IO

VDD_

CORE

VDD_

CORE

GND

VDD_

CORE

VDD_

CORE

VDD_IO

LSTi4

LSTi5

LSTi6

LSTi7

BSTi8

BSTi9

BSTi10

BSTi11 VDD_IO

VDD_

PLL

VDD_IO

LSTi8

LSTi9

LSTi10

LSTi11

BSTi12 BSTi13 BSTi14 BSTi15 BSTi16

IC_

OPEN

IC_

OPEN

LSTi12

LSTi13

LSTi14

LSTi15

LSTi16

BSTi17 BSTi18 BSTi19 BSTi20 BSTi21

D11

D10

C16o

FP16o

LSTi17

LSTi18

LSTi19

LSTi20

LSTi21

BSTi22 BSTi23 BSTi24 BSTi25 BSTi26

D15

D14

D13

D12

FP8o

FP8i

LSTi22

LSTi23

LSTi24

LSTi25

LSTi26

BSTi27 BSTi28 BSTi29 BSTi30 BSTi31 IC_GND IC_GND IC_GND IC_GND

C8i

C8o

LSTi27

LSTi28

LSTi29

LSTi30

LSTi31

ZL50062/4

Data Sheet

Zarlink Semiconductor Inc.

Pin Description

Pin Name

ZL50064

Package

Coordinates

(256-pin

LQFP)

ZL50062

Package

Coordinates

(256-ball

PBGA)

Description

Device Timing

C8i

T10

Master Clock (5V Tolerant Schmitt-Triggered Input). This
pin accepts an 8.192MHz clock. The internal frame boundary
is aligned with the clock falling or rising edge, as controlled by
the C8IPOL bit in the Control Register. Input data on both the
Backplane and Local sides (BSTi0-31 and LSTi0-31) must be
aligned to this clock and the accompanying input frame pulse,
FP8i.

FP8i

R11

Frame Pulse Input (5V Tolerant Schmitt-Triggered Input).
When the Frame Pulse Width bit (FPW) of the Control
Register is LOW (default), this pin accepts a 122ns-wide
frame pulse. When the FPW bit is HIGH, this pin accepts a
244ns-wide frame pulse. The device will automatically detect
whether an ST-BUS or GCI-Bus style frame pulse is applied.
Input data on both the Backplane and Local sides (BSTi0-31
and LSTi0-31) must be aligned to this frame pulse and the
accompanying input clock, C8i.

C8o

T11

C8o Output Clock (5V Tolerant Three-state Output). This
pin outputs an 8.192MHz clock generated within the device.
The clock falling edge or rising edge is aligned with the output
frame boundary presented on FP8o; this edge polarity
alignment is controlled by the COPOL bit of the Control
Register. Output data on both the Backplane and Local sides
(BSTo0-31 and LSTo0-31) will be aligned to this clock and the
accompanying output frame pulse, FP8o.

FP8o

R10

Frame Pulse Output (5V Tolerant Three-state Output).
When the Frame Pulse Width bit (FPW) of the Control
Register is LOW (default), this pin outputs a 122ns-wide frame
pulse. When the FPW bit is HIGH, this pin outputs a
244ns-wide frame pulse. The frame pulse, running at 8kHz
rate, will have the same format (ST-BUS or GCI-Bus) as the
input frame pulse (FP8i). Output data on both the Backplane
and Local sides (BSTo0-31 and LSTo0-31) will be aligned to
this frame pulse and the accompanying output clock, C8o.

C16o

P10

C16o Output Clock (5V Tolerant Three-state Output). This
pin outputs a 16.384MHz clock generated within the device.
The clock falling edge or rising edge is aligned with the output
frame boundary presented on FP16o; this edge polarity
alignment is controlled by the COPOL bit of the Control
Register. Output data on both the Backplane and Local sides
(BSTo0-31 and LSTo0-31) will be aligned to this clock and the
accompanying output frame pulse, FP16o.

ZL50062/4

Data Sheet

Zarlink Semiconductor Inc.

FP16o

P11

Frame Pulse Output (5V Tolerant Three-state Output).
When the Frame Pulse Width bit (FPW) of the Control
Register is LOW (default), this pin outputs a 61ns-wide frame
pulse. When the FPW bit is HIGH, this pin outputs a
122ns-wide frame pulse. The frame pulse, running at 8kHz
rate, will have the same format (ST-BUS or GCI-Bus) as the
input frame pulse (FP8i). Output data on both the Backplane
and Local sides (BSTo0-31 and LSTo0-31) will be aligned to
this frame pulse and the accompanying output clock, C16o.

Backplane and Local Inputs

BSTi0-15

228, 229,
230, 231,
232, 233,
234, 235,
236, 238,
237, 240,
239, 242,

241, 244

K1, K2, K3,

K4, L1, L2,

L3, L4, M1,

M2, M3, M4,

N1, N2, N3,

Backplane Serial Input Streams 0 to 15 (5V Tolerant Inputs with

Internal Pull-downs).

These pins accept serial TDM data streams at a data rate of:
16.384Mbps (with 256 channels per stream),
8.192Mbps (with 128 channels per stream),
4.096Mbps (with 64 channels per stream) or
2.048Mbps (with 32 channels per stream).

BSTi16-31

248, 250,
249, 252,
251, 254,
253, 255,

256, 1, 2, 3,

4, 6, 5, 8

N5, P1, P2,

P3, P4, P5,

R1, R2, R3,

R4, R5, T1,

T2, T3, T4, T5

Backplane Serial Input Streams 16 to 31 (5V Tolerant Inputs with
Internal Pull-downs).

LSTi0-15

83, 81, 82,
79, 80, 77,
78, 75, 76,
73, 74, 71,

72, 66, 65, 64

K13, K14,

K15, K16,

L13, L14,

L15, L16,

M13, M14,

M15, M16,

N12, N13,

N14, N15

Local Serial Input Streams 0 to 15 (5V Tolerant Inputs with

Internal Pull-downs).

LSTi16-31

63, 62, 61,
59, 60, 57,
58, 55, 56,
53, 54, 51,

52, 46, 45, 44

N16, P12,

P13, P14,

P15, P16,

R12, R13,

R14, R15,

R16, T12,

T13, T14,

T15, T16

Local Serial Input Streams 16 to 31 (5V Tolerant Inputs with
Internal Pull-downs).

Pin Description (continued)

Pin Name

ZL50064

Package

Coordinates

(256-pin

LQFP)

ZL50062

Package

Coordinates

(256-ball

PBGA)

Description

ZL50062/4

Data Sheet

Zarlink Semiconductor Inc.

Backplane and Local Outputs and Control

ODE

149

B10

Output Drive Enable (5V Tolerant Input with Internal Pull-up).

An asynchronous input providing Output Enable control to the
BSTo0-31 and LSTo0-31 outputs.

When LOW, the BSTo0-31 and LSTo0-31 outputs are driven
HIGH or high impedance (dependent on the BORS and LORS
pin settings respectively).

When HIGH, the outputs BSTo0-31 and LSTo0-31 are
enabled.

BORS

223

Backplane Output Reset State (5V Tolerant Input with Internal

Pull-down).

When this input is LOW, the device will initialize with the
BSTo0-31 outputs driven high. Following initialization, the
Backplane stream outputs are always active.

When this input is HIGH, the device will initialize with the
BSTo0-31 outputs at high impedance. Following initialization,
the Backplane stream outputs may be set active or high
impedance using the ODE pin or on a per-channel basis with
the BE bit in the Backplane Connection Memory.

BSTo0-15

182, 181,
184, 183,
186, 185,
188, 187,
191, 192,
193, 194,
195, 197,

196, 199

B1, B2, B3,

B4, C1, C2,

C3, C4, D1,

D2, D3, D4,

E1, E2, E3,

Backplane Serial Output Streams 0 to 15 (5V Tolerant,

Three-state Outputs with Slew-Rate Control).

These pins output serial TDM data streams at a data rate of:
16.384Mbps (with 256 channels per stream),
8.192Mbps (with 128 channels per stream),
4.096Mbps (with 64 channels per stream) or
2.048Mbps (with 32 channels per stream).

Refer to the descriptions of the BORS and ODE pins for
control of the output HIGH or high impedance state.

BSTo16-31

203, 205,
204, 207,
206, 209,
208, 210,
215, 216,
217, 218,
219, 220,

221, 222

F1, F2, F3,

F4, G1, G2,

G3, G4, H1,

H2, H3, H4,

J1, J2, J3, J4

Backplane Serial Output Streams 16 to 31 (5V Tolerant,

Three-state Outputs with Slew-Rate Control).

Refer to the descriptions of the BORS and ODE pins for
control of the output HIGH or high impedance state.

Pin Description (continued)

Pin Name

ZL50064

Package

Coordinates

(256-pin

LQFP)

ZL50062

Package

Coordinates

(256-ball

PBGA)

Description

ZL50062/4

Data Sheet

Zarlink Semiconductor Inc.

LORS

D12

Local Output Reset State (5V Tolerant Input with Internal

Pull-down).

When this input is LOW, the device will initialize with the
LSTo0-31 outputs driven high. Following initialization, the
Local stream outputs are always active.

When this input is HIGH, the device will initialize with the
LSTo0-31 outputs at high impedance. Following initialization,
the Local stream outputs may be set active or high impedance
using the ODE pin or on a per-channel basis with the LE bit in
the Local Connection Memory.

LSTo0-15

130, 129,
128, 127,
126, 125,

121, 118, 119,

116, 117, 114,

115, 113, 108,

107

B13, B14,

B15, B16,

C13, C14,

C15, C16,

D13, D14,

D15, D16,

E13, E14,

E15, E16

Local Serial Output Streams 0 to 15 (5V Tolerant Three-state

Outputs with Slew-Rate Control).

Refer to the descriptions of the LORS and ODE pins for
control of the output HIGH or high impedance state.

LSTo16-31

106, 105,
104, 103,

102, 101, 98,

97, 96, 95,
94, 93, 92,

91, 86, 85

F13, F14,

F15, F16,

G13, G14,

G15, G16,

H13, H14,

H15, H16,

J13, J14, J15,

J16

Local Serial Output Streams 16 to 31 (5V Tolerant Three-state

Outputs with Slew-Rate Control).

Refer to the descriptions of the LORS and ODE pins for
control of the output HIGH or high impedance state.

Microprocessor Port Signals

A0 - A14

179, 180,
177, 178,
172, 171,
170, 169,
168, 167,
166, 165,

164, 163, 162

A1, A2, A3,

A4, A5, B5,

B6, B7, B8,

B9, C5, C6,

C7, C8, C9

Address 0 - 14 (5V Tolerant Inputs). These pins form the
15-bit address bus to the internal memories and registers.

A0 = LSB

D0 - D15

31, 30, 29,
28, 27, 26,
25, 24, 19,
18, 17, 15,

16, 13, 14, 11

M9, M8, M7,

M6, N9, N8,

N7, N6, P9,

P8, P7, P6,

R9, R8, R7,

Data Bus 0 - 15 (5V Tolerant Inputs/Outputs with
Slew-Rate Control). These pins form the 16-bit data bus of
the microprocessor port.

D0 = LSB

Pin Description (continued)

Pin Name

ZL50064

Package

Coordinates

(256-pin

LQFP)

ZL50062

Package

Coordinates

(256-ball

PBGA)

Description

ZL50062/4

Data Sheet

Zarlink Semiconductor Inc.

151

Chip Select (5V Tolerant Input). Active LOW input used by
the microprocessor to enable the microprocessor port access.
Note that a minimum of 30ns must separate the
de-assertion of DTA (to high) and the assertion of CS
and/or DS to initiate the next access.

157

Data Strobe (5V Tolerant Input). This active LOW input
works in conjunction with CS to enable the microprocessor
port read and write operations. Note that a minimum of 30ns
must separate the de-assertion of DTA (to high) and the
assertion of CS and/or DS to initiate the next access.

R/W

152

Read/Write (5V Tolerant Input). This input controls the
direction of the data bus lines (D0-D15) during a
microprocessor access.

DTA

150

C10

Data Transfer Acknowledgment (5V Tolerant Three-state
Output). This active LOW output indicates that a data bus
transfer is complete. A pull-up resistor is required to hold a
HIGH level. Note that a minimum of 30ns must separate
the de-assertion of DTA (to high) and the assertion of CS
and/or DS to initiate the next access.

RESET

148

B11

Device Reset (5V Tolerant Input with Internal Pull-up). This
input (active LOW) asynchronously applies reset and
synchronously releases reset to the device. In the reset state,
the outputs LSTo0-31 and BSTo0-31 are set to a HIGH or high
impedance state, depending on the state of the LORS and
BORS external control pins, respectively. The assertion of this
pin also clears the device registers and internal counters.
Refer to Section 7.3 on page 29 for the timing
requirements regarding this reset signal.

JTAG Control Signals

TCK

143

D10

Test Clock (5V Tolerant Input).

Provides the clock to the JTAG test logic.

TMS

147

B12

Test Mode Select (5V Tolerant Input with Internal Pull-up).

JTAG signal that controls the state transitions of the TAP
controller.

TDi

145

C11

Test Serial Data In (5V Tolerant Input with Internal Pull-up).

JTAG serial test instructions and data are shifted in on this pin.

TDo

146

C12

Test Serial Data Out (5V Tolerant Three-state Output).
JTAG serial data is output on this pin on the falling edge of
TCK. This pin is held in a high impedance state when JTAG is
not enabled.

Pin Description (continued)

Pin Name

ZL50064

Package

Coordinates

(256-pin

LQFP)

ZL50062

Package

Coordinates

(256-ball

PBGA)

Description

ZL50062/4

Data Sheet

Zarlink Semiconductor Inc.

1.0 Unidirectional and Bi-directional Switching Applications

The ZL50062/64 has a maximum capacity of 16,384 input channels and 16,384 output channels. This is calculated
from the maximum number of streams and channels: 64 input streams (32 Backplane, 32 Local) at 16.384Mbps
and 64 output streams (32 Backplane, 32 Local) at 16.384Mbps.

A typical mode of operation is to separate the input and output streams to form a unidirectional switch, as shown in
Figure 4 below.

Figure 4 - 16,384 x 16,384 Channels (16Mbps), Unidirectional Switching

In this system, the Backplane and Local input streams are combined, and the Backplane and Local output streams
are combined, so that the switch appears as a 64 input stream by 64 output stream switch. This gives the maximum
16,384 x 16,384 channel capacity.

Often a system design needs to differentiate between a Backplane and a Local side, or it needs to put the switch in
a bi-directional configuration. In this case, the ZL50062/64 can be used as shown in Figure 5 to give 8,192 x 8,192
channel bi-directional capacity.

Figure 5 - 8,192 x 8,192 Channels (16Mbps), Bi-directional Switching

In this system setup, the chip has a capacity of 8,192 input channels and 8,192 output channels on the Backplane
side, as well as 8,192 input channels and 8,192 output channels on the Local side. Note that some or all of the
output channels on one side can come from the other side, e.g., Backplane input to Local output switching.

ZL50062/64

32 streams

BSTi0-31

LSTi0-31

BSTo0-31

LSTo0-31

INPUT

OUTPUT

ZL50062/64

32 streams

BSTi0-31

BSTo0-31

LSTo0-31

LSTi0-31

BACKPLANE

LOCAL

ZL50062/4

Data Sheet

Zarlink Semiconductor Inc.

1.1 Flexible Configuration

The ZL50062/64 can be configured as a 16K by 16K non-blocking unidirectional digital switch, an 8K by 8K
non-blocking bi-directional digital switch, or as a blocking switch with various switching capacities.

1.1.1 Non-Blocking Unidirectional Configuration (Typical System Configuration)

Because the input and output drivers are synchronous, the user can combine input Backplane streams and input
Local streams as well as output Backplane streams and output Local streams to increase the total number of input
and output streams of the switch in a unidirectional configuration, as shown in Figure 4.

· 16,384-channel x 16,384-channel non-blocking switching from input to output streams

1.1.2 Non-Blocking Bi-directional Configuration

Another typical application is to configure the ZL50062/64 as a non-blocking 8K by 8K bi-directional switch, as
shown in Figure 5:

· 8,192-channel x 8,192-channel non-blocking switching from Backplane input to Local output streams

· 8,192-channel x 8,192-channel non-blocking switching from Local input to Backplane output streams

· 8,192-channel x 8,192-channel non-blocking switching from Backplane input to Backplane output streams

· 8,192-channel x 8,192-channel non-blocking switching from Local input to Local output streams

1.1.3 Blocking Bi-directional Configuration

The ZL50062/64 can be configured as a blocking bi-directional switch if it is an application requirement. For
example, it can be configured as a 12K by 4K bi-directional blocking switch, as shown in Figure 6:

· 12,288-channel x 4,096-channel blocking switching from Backplane input to Local output streams

· 4,096-channel x 12,288-channel blocking switching from Local input to Backplane output streams

· 12,288-channel x 12,288-channel non-blocking switching from Backplane input to Backplane output streams

· 4,096-channel x 4,096-channel non-blocking switching from Local input to Local output streams

Figure 6 - 12,288 by 4,096 Channels Blocking Bi-directional Configuration

ZL50062/64

12K by 12K

LSTo16-31

LSTi16-31

4K by 4K

LSTi0-15

BSTi0-31

BSTo0-31

LSTo0-15

12K by 4K

4K by 12K

Total 16 streams input and 16 streams output

Total 48 streams input and 48 streams output

ZL50062/4

Data Sheet

Zarlink Semiconductor Inc.

2.0 Functional Description

2.1 Switching Configuration

The device supports five switching configurations: (1) Unidirectional switch, (2) Backplane-to-Local, (3)
Local-to-Backplane, (4) Backplane-to-Backplane, and (5) Local-to-Local. The following sections describe the
switching paths in detail. Configurations (2) - (5) enable a non-blocking bi-directional switch with 8,192 Backplane
input/output channels at Backplane stream data rates of 16.384Mbps, and 8,192 Local input/output channels at
Local stream data rates of 16.384Mbps. The switching paths of configurations (2) to (5) may be operated
simultaneously. When the lower data-rates of 8.192, 4.096 and 2.048Mbps are used, there will be a corresponding
reduction in switch capacity.

2.1.1 Unidirectional Switch

The device can be configured as a 16,384 x 16,384 unidirectional switch by grouping together all input streams and
all output streams. All streams can be operated at a data rate of 16.384Mbps. Lower data rates may be used with a
corresponding reduction in switch capacity.

2.1.2 Backplane-to-Local Path

The device can provide data switching between the Backplane input port and the Local output port. The Local
Connection Memory determines the switching configurations.

2.1.3 Local-to-Backplane Path

The device can provide data switching between the Local input port and the Backplane output port. The Backplane
Connection Memory determines the switching configurations.

2.1.4 Backplane-to-Backplane Path

The device can provide data switching between the Backplane input and output ports. The Backplane Connection
Memory determines the switching configurations.

2.1.5 Local-to-Local Path

The device can provide data switching between the Local input and output ports. The Local Connection Memory
determines the switching configurations.

2.1.6 Port Data Rate Modes and Selection

The Local port has 32 input (LSTi0-31) and 32 output (LSTo0-31) data streams. Similarly, the Backplane port has
32 input (BSTi0-31) and 32 output (BSTo0-31) data streams. The bit rate of all these streams is selected by writing
to the Bit Rate Registers, BRR (see Table 24). All the streams operate at the same bit rate at a time. The device can
operate at 2.048, 4.096, 8.192 or 16.384 Mbps. The default operation mode is 2.048Mbps. The timing of the input
and output clocks and frame pulses is shown in Figure 8, "Input and Output Frame Pulse Alignment for Different
Data Rates" on page 22. The input traffic are aligned based on the FP8i and C8i input timing signals, while the
output traffic are aligned based on the FP8o and C8o output timing signals.

2.1.6.1 Local Output Port

Operation of stream data in Connection Mode or Message Mode is determined by the state of the LMM bit of the
Local Connection Memory. The channel high impedance state is controlled by the LE bit of the Local Connection
Memory. The data source (i.e. from the Local or Backplane Data Memory) is determined by the LSRC bit of the
Local Connection Memory. Refer to Section 8.1, Local Connection Memory, and Section 11.3, Local Connection
Memory Bit Definition for more details.

ZL50062/4

Data Sheet

Zarlink Semiconductor Inc.

2.1.6.2 Backplane Output Port

Operation of stream data in Connection Mode or Message Mode is determined by the state of the BMM bit of the
Backplane Connection Memory and the channel high impedance state is controlled by the BE bit of the Backplane
Connection Memory. The data source (i.e. from the Local or Backplane Data Memory) is determined by the BSRC
bit of the Backplane Connection Memory. Refer to Section 8.2, Backplane Connection Memory and Section 11.4,
Backplane Connection Memory Bit Definition for more details.

2.2 Frame Pulse Input and Master Input Clock Timing

The input frame pulse (FP8i) is an 8kHz input signal active for 122ns or 244ns at the frame boundary. The FPW bit
in the Control Register must be set according to the applied pulse width. See Pin Description and Table 13, "Control
Register Bits" on page 37, for details.

The active state and timing of FP8i can conform either to the ST-BUS or to the GCI-Bus as shown in Figure 7,
ST-BUS and GCI-Bus Input Timing Diagram for Different Data Rates. The ZL50062/64 device will automatically
detect whether an ST-BUS or a GCI-Bus style frame pulse is being used for the master frame pulse (FP8i). The
output frame pulses (FP8o and FP16o) are always of the same style (ST-BUS or GCI-Bus) as the input frame
pulse. The active edge of the input clock (C8i) shall be selected by the state of the Control Register bit C8IPOL.

Note that the active edge of ST-BUS is falling edge, which is the default mode of the device, while GCI-Bus uses
rising edge as the active edge. Although GCI frame pulse will be automatically detected, to fully conform to
GCI-Bus operation, the device should be set to use C8i rising edge as the active edge (by setting bit C8IPOL HIGH)
when GCI-Bus is used.

For the purposes of describing the device operation, the remaining part of this document assumes the ST-BUS
frame pulse format with a single width frame pulse of 122ns and a falling active clock-edge, unless explicitly stated
otherwise.

In addition, the ZL50062 device provides FP8o, FP16o, C8o and C16o outputs to support external devices which
connect to the output ports. The ZL50064 only provides FP8o and C8o outputs. The generated frame pulses (FP8o,
FP16o) will be provided in the same format as the master frame pulse (FP8i). The polarity of C8o and C16o, at the
frame boundary, can be controlled by the Control Register bit, COPOL. An analog phase lock loop (APLL) is used
to multiply the input clock frequency on C8i to generate an internal clock signal operating at 131.072MHz.

ZL50062/4

Data Sheet

Zarlink Semiconductor Inc.

2.3 Input Frame Pulse and Generated Frame Pulse Alignment

The ZL50062 accepts a frame pulse (FP8i) and generates two frame pulse outputs, FP8o and FP16o, which are
aligned to the master frame pulse. The ZL50064 only generates one frame pulse output, FP8o. There is a constant
throughput delay for data being switched from the input to the output of the device such that data which is input
during Frame N is output during Frame N+2.

For further details of frame pulse conditions and options, see Section 13.1, Control Register (CR), Figure 16, Frame
Boundary Conditions, ST-BUS Operation, and Figure 17, Frame Boundary Conditions, GCI-Bus Operation.

Figure 8 - Input and Output Frame Pulse Alignment for Different Data Rates

The t

FBOS

is the offset between the input frame pulse, FP8i, and the generated output frame pulse, FP8o. Refer to

the "AC Electrical Characteristics," on page 52. Note that although the figure above shows the traditional setups of
the frame pulses and clocks for both ST-BUS and GCI-Bus configurations, the devices can be configured to
accept/generate double-width frame pulses (if the FPW bit in the Control Register is set) as well as to use the
opposite clock edge for frame-boundary determination (using the C8IPOL and COPOL bits in the Control Register).
See the timing diagrams in "AC Electrical Characteristics," on page 52 for all of the available configurations.

2.4 Jitter Tolerance Improvement Circuit - Frame Boundary Discriminator

To improve the jitter tolerance of the ZL50062/64, a Frame Boundary Discriminator (FBD) circuit was added to the
device. This circuit is enabled by setting the Control Register bit FBDEN to HIGH. By default the FBD is disabled.

The FBD can operate in two modes, as controlled by the FBD_MODE[2:0] bits of the Control Register. When bits
FBD_MODE[2:0] are set to 000

, the FBD is set to handle lower frequency jitter only (<8kHz). When bits

FBD_MODE[2:0] are set to 111

, the FBD can handle both low frequency and high frequency jitter. All other values

are reserved. These bits are ignored when bit FBDEN is LOW. It is strongly recommended that if bit FBDEN is set
HIGH, bits FBD_MODE[2:0] should be set to 111

to improve the high frequency jitter handling capability.

To achieve the best jitter tolerance performance, it is also recommended that the input data sampling point be
optimized. In most applications, the optimum sampling point is 1/2 instead of the default 3/4 (it can be changed by
programming all the LIDR and BIDR registers). This will give more allowance for sampling point variations caused

CH3

CH7

CH0

CH1

CH2

BSTi/LSTi0-31

(16Mbps)

C8o

FP8o

BSTo/LSTo0-31

(2Mbps)

BSTo/LSTo0-31

(4Mbps)

BSTo/LSTo0-31

(8Mbps)

BSTo/LSTo0-31

(16Mbps)

CH2

CH1

CH0

CH6

CH5

CH4

CH3

CH2

CH0

CH4

CH5

CH10

CH9

CH8

CH11

CH1

FP8i

C8i

CH3

CH7

CH0

CH1

CH2

(2Mbps)

BSTi/LSTi0-31

(4Mbps)

BSTi/LSTi0-31

CH2

CH1

CH0

CH6

CH5

CH4

CH3

CH2

CH0

CH4

CH5

CH10

CH9

CH8

CH11

CH1

BSTi/LSTi0-31

(8Mbps)

FBOS

ZL50062/4

Data Sheet

Zarlink Semiconductor Inc.

by jitter. There are, however, some cases where data experience more delay than the timing signals. A common
example is when multiple data lines are tied together to form bidirectional buses. The large bus loading may cause
data to be delayed. If this is the case, the optimum sampling point may be 3/4 or 4/4 instead of 1/2. The optimum
sampling point is dependent on the application. The user should optimize the sampling point to achieve the best
jitter tolerance performance.

2.5 Input Clock Jitter Tolerance

Input clock jitter tolerance depends on the data rate. In general, the higher the data rate, the smaller the jitter
tolerance is, because the period of a bit cell is shorter, and the sampling point variation allowance is smaller.

Jitter tolerance can not be accurately represented by just one number. Jitter of the same amplitude but different
frequency spectrum can have different effect on the operation of a device. For example, a device that can tolerate
20ns of jitter of 10kHz frequency may only be able to tolerate 10ns of jitter of 1MHz frequency. Therefore, jitter
tolerance should be represented as a spectrum over frequency. The highest possible jitter frequency is half of the
carrier frequency. In the case of the ZL50062/64, the input clock is 8.192MHz, and the jitter associated with this
clock can have the highest frequency component at 4.096MHz.

For the above reasons, jitter tolerance of the ZL50062/64 has been characterized at 16.384Mbps. The lower data
rates (2.048Mbps, 4.096Mbps, 8.192Mbps) will have the same or better tolerance than that of the 16.384Mbps
operation. Tolerance of jitter of different frequencies are shown in the "AC Electrical Characteristics" section, table
"Input Clock Jitter Tolerance" on page 62. The Jitter Tolerance Improvement Circuit was enabled (Control Register,
bit FBDEN set HIGH, and bits FBD_MODE[2:0] set to 111

), and the sampling point was optimized.

3.0 Input and Output Offset Programming

Various registers are used to control the input sampling point (delay) and the output advancement for the Local and
Backplane streams. The following sections explain the details of these offset programming features.

3.1 Input Offsets

Control of the Input Bit Delay allows each input stream to have a different frame boundary with respect to the
master frame pulse, FP8i. Each input stream can be individually delayed by up to 7 3/4 bits with a resolution of 1/4
bit of the bit period.

3.1.1 Input Bit Delay Programming (Backplane and Local Input Streams)

Input Bit Delay Registers LIDR0-31 and BIDR0-31 work in conjunction with the SMPL_MODE bit in the Control
Register to allow users to control input bit fractional delay as well as input bit sample point selection for greater
flexibility when designing switch matrices for high speed operation.

When SMPL_MODE = LOW (input bit fractional delay mode), bits LID[4:0] and BID[4:0] in the LIDR0-31 and
BIDR0-31 registers respectively define the input bit fractional delay of the corresponding local and backplane
stream. The total delay can be up to 7 3/4 bits with a resolution of 1/4 bit at the selected data rate. When
SMPL_MODE = HIGH (sampling point select mode), bits LID[1:0] and BID[1:0] define the input bit sampling point of
the stream. The sampling point can be programmed at the 3/4, 4/4, 1/4 or 2/4 bit location to allow better tolerance
for input jitter. Bits LID[4:2] and BID[4:2] define the integer input bit delay, with a maximum value of 7 bits at a
resolution of 1 bit.

Refer to Figure 9 and Figure 10 for Input Bit Delay Timing at 16Mbps and 8Mbps data rates, respectively.

Refer to Figure 10 for Input Sampling Point Selection Timing at 8Mbps data rates.

ZL50062/4

Data Sheet

Zarlink Semiconductor Inc.

Figure 10 - Backplane and Local Input Bit Delay or Sampling Point Selection Timing Diagram for

Data Rate of 8Mbps

3.2 Output Advancement Programming (Backplane and Local Output Streams)

This feature is used to advance the output channel alignment of individual Local or Backplane output streams with
respect to the frame boundary FP8o. Each output stream has its own advancement value that can be programmed
by the Output Advancement Registers. The output advancement selection is useful in compensating for various
parasitic loading on the serial data output pins.

The Local and Backplane Output Advancement Registers, LOAR0 - LOAR31 and BOAR0 - BOAR31, are used to
control the Local and Backplane output advancement respectively. The advancement is determined with reference
to the internal system clock rate (131.072MHz). The advancement can be 0, -2 cycles, -4 cycles or -6 cycles, which
converts to approximately 0ns, -15ns, -31ns or -46ns as shown in Figure 11.

C8i

BSTi/LSTi0-31

BID[4:0]/LID[4:0] = 00011

Ch0

Ch127

sample at 3/4 point

FP8i

BSTi/LSTi0-31

BID[4:0]/LID[4:0] = 00000

Ch0

Bit delay = 0 bit (Default)

Ch127

sample at 3/4 point

SMPL_MODE = LOW

C8i

BSTi/LSTi0-31

BID[4:0]/LID[4:0] = 00011

Ch0

Ch127

sample at 2/4 point

FP8i

BSTi/LSTi0-31

BID[4:0]/LID[4:0] = 00000

Ch0

3/4 sampling (Default)

Ch127

sample at 3/4 point

SMPL_MODE = HIGH

Please refer to Control Register (Section 13.1) for SMPL_MODE definition.

Bit Delay = 3/4 bit

2/4 sampling

ZL50062/4

Data Sheet

Zarlink Semiconductor Inc.

Figure 11 - Local and Backplane Output Advancement Timing Diagram for Data Rate of 16Mbps

4.0 Port high impedance Control

The input pins, LORS and BORS, select whether the Local (LSTo0-31) and Backplane (BSTo0-31) output streams,
respectively, are set to high impedance at the output of the device itself, or are always driven (active HIGH or active
LOW).

Setting LORS/BORS to a LOW state will configure the output streams, LSTo0-31/BSTo0-31, to transmit bi-state
channel data.

Setting LORS/BORS to a HIGH state will configure the output streams, LSTo0-31/BSTo0-31, of the device to
invoke a high impedance output on a per-channel basis. The Local/Backplane Output Enable Bit (LE/BE) of the
Local/Backplane Connection Memory has direct per-channel control on the high impedance state of the
Local/Backplane output streams, L/BSTo0-31. Programming a LOW state in the connection memory LE/BE bit will
set the stream output of the device to high impedance for the duration of the channel period. See "Local Connection
Memory Bit Definition," on page 34 and "Backplane Connection Memory Bit Definition," on page 35 for
programming details.

The state of the LORS/BORS pin is detected and the device configured accordingly during a RESET operation,
e.g. following power-up. The LORS/BORS pin is an asynchronous input and is expected to be hard-wired for a
particular system application, although it may be driven under logic control if preferred.

The Local/Backplane output enable control in order of highest priority is: RESET, ODE, OSB, LE/BE.

RESET

(input pin)

ODE

(input pin)

OSB

(Control

Register bit)

LE/BE

(Local /

Backplane

Connection

Memory bit)

LORS/BORS

(input pin)

LSTo0-31/

BSTo0-31

HIGH

HI-Z

HIGH

HI-Z

HIGH

Table 1 - Local and Backplane Output Enable Control Priority

Bit Advancement, -2

Bit Advancement, -4

Bit Advancement, -6

FP8o

System Clock

BSTo/LSTo0-31

Bit Advancement = 0

BSTo/LSTo0-31

Bit Advancement = -2

(Default)

Bit Advancement = -6

BSTo/LSTo0-31

Bit Advancement = -4

BSTo/LSTo0-31

131.072 MHz

Ch255

Ch0

Bit 1

Bit 0

Bit 7

Bit 6

Bit 5

Bit 1

Bit 0

Bit 7

Bit 6

Bit 5

Bit 1

Bit 0

Bit 7

Bit 6

Bit 5

Bit 1

Bit 0

Bit 7

Bit 6

Bit 5

Bit 4

Bit Advancement, 0

ZL50062/4

Data Sheet

Zarlink Semiconductor Inc.

5.0 Data Delay Through the Switching Paths

Serial data which goes into the device is converted into parallel format and written to consecutive locations in the
data memory. Each data memory location corresponds to the input stream and channel number. Channels written
to any of the buffers during Frame N will be read out during Frame N+2. The input bit delay and output bit
advancement have no impact on the overall data throughput delay.

In the following paragraphs, the data throughput delay (T) is represented as a function of ST-BUS frames, input
channel number, (m), and output channel number (n). Table 2 describes the variable range for input streams and
Table 3 describes the variable range for output streams. The data throughput delay under various input channel
and output channel conditions can be summarized as:

T = 2 frames + (n - m)

HI-Z

HIGH

HI-Z

ACTIVE

(HIGH or LOW)

Input Stream

Data Rate

Input Channel

Number (m)

2Mbps

0 to 31

4Mbps

0 to 63

8Mbps

0 to 127

16Mbps

0 to 255

Table 2 - Variable Range for Input Streams

Output Stream

Data Rate

Output Channel

Number (n)

2Mbps

0 to 31

4Mbps

0 to 63

8Mbps

0 to 127

16Mbps

0 to 255

Table 3 - Variable Range for Output Streams

RESET

(input pin)

ODE

(input pin)

OSB

(Control

Register bit)

LE/BE

(Local /

Backplane

Connection

Memory bit)

LORS/BORS

(input pin)

LSTo0-31/

BSTo0-31

Table 1 - Local and Backplane Output Enable Control Priority (continued)

ZL50062/4

Data Sheet

Zarlink Semiconductor Inc.

The data throughput delay (T) is: T = 2 frames + (n - m). Assuming that m (input channel) and n (output channel)
are equal, we have the figure below, in which the delay between the input data being written and the output data
being read is exactly 2 frames.

Figure 12 - Data Throughput Delay with Input Ch0 Switched to Output Ch0

Assuming that n (output channel) is greater than m (input channel), we have the figure below, in which the delay
time between the input channel being written and the output channel being read exceeds 2 frames.

Figure 13 - Data Throughput Delay with Input Ch0 Switched to Output Ch13

Assuming that n (output channel) is less than m (input channel), we have the figure below, in which the delay time
between the input channel being written and the output channel being read is less than 2 frames.

Figure 14 - Data Throughput Delay with Input Ch13 Switched to Output Ch0

Frame

Frame N

Frame N+1

Frame N+2

Frame N+3

Frame N+4

Frame N+5

Frame N Data

Frame N+1Data

Frame N+2 Data

Frame N+3 Data

Frame N+4 Data

Frame N+5 Data

Serial Input Data

Serial Output Data

Frame N-2 Data

Frame N-1 Data

Frame N Data

Frame N+1 Data

Frame N+2 Data

Frame N+3 Data

2 Frames + 0

Frame

Frame N

Frame N+1

Frame N+2

Frame N+3

Frame N+4

Frame N+5

Frame N Data

Frame N+1Data

Frame N+2 Data

Frame N+3 Data

Frame N+4 Data

Frame N+5 Data

Serial Input Data

Serial Output Data

Frame N-2 Data

Frame N-1 Data

Frame N Data

Frame N+1 Data

Frame N+2 Data

Frame N+3 Data

2 Frames + (n - m)

Frame

Frame N

Frame N+1

Frame N+2

Frame N+3

Frame N+4

Frame N+5

Frame N Data

Frame N+1Data

Frame N+2 Data

Frame N+3 Data

Frame N+4 Data

Frame N+5 Data

Serial Input Data

Serial Output Data

Frame N-2 Data

Frame N-1 Data

Frame N Data

Frame N+1 Data

Frame N+2 Data

Frame N+3 Data

2 Frames + (n - m)

ZL50062/4

Data Sheet

Zarlink Semiconductor Inc.

6.0 Microprocessor Port

The 16K switch family supports non-multiplexed Motorola type microprocessor buses. The microprocessor port
consists of a 16-bit parallel data bus (D0-15), a 15-bit address bus (A0-14) and four control signals (CS, DS, R/W
and DTA). The data bus provides access to the internal registers, the Backplane Connection and Data Memories,
and the Local Connection and Data Memories. Each memory has 8,192 locations. See Table 7, Address Map for
Data and Connection Memory Locations (A14 = 1), for the address mapping.

Each Connection Memory can be read or written via the 16-bit microprocessor port. The Data Memories can only
be read (but not written) from the microprocessor port.

To prevent the bus 'hanging', in the event of the switch not receiving a master clock, the microprocessor port shall
complete the DTA handshake when accessed, but any data read from the bus will be invalid.

7.0 Device Power-up, Initialization and Reset

7.1 Power-Up Sequence

The recommended power-up sequence is for the V

DD_IO

supply (nominally +3.3V) to be established before the

power-up of the V

DD_PLL

and V

DD_CORE

supplies (nominally +1.8V). The V

DD_PLL

and V

DD_CORE

supplies may be

powered up simultaneously, but neither should 'lead' the V

DD_IO

supply by more than 0.3V.

All supplies may be powered-down simultaneously.

7.2 Initialization

Upon power up, the device should be initialized by applying the following sequence:

7.3 Reset

The RESET pin is used to reset the device. When set LOW, an asynchronous reset is applied to the device. It is
then synchronized to the internal clock. During the reset period, depending on the state of input pins LORS and
BORS, the output streams LSTo0-31 and BSTo0-31 are set to HIGH or high impedance, and all internal registers
and counters are reset to the default state.

The RESET pin must remain LOW for two input clock cycles (C8i) to guarantee a synchronized reset release. A
delay of an additional 250

s must also be waited before the first microprocessor access is performed following

the de-assertion of the RESET pin; this delay is required for determination of the frame pulse format.

Ensure the TRST pin is permanently LOW to disable the JTAG TAP controller.

Set ODE pin to LOW. This sets the LSTo0-31 outputs to HIGH or high impedance, dependent on the
LORS input value, and sets the BSTo0-31 outputs to HIGH or high impedance, dependent on BORS
input value. Refer to Pin Description for details of the LORS and BORS pins.

Reset the device by asserting the RESET pin to zero for at least two cycles of the input clock, C8i. A
delay of an additional 250

s must also be applied before the first microprocessor access is

performed following the de-assertion of the RESET pin; this delay is required for determination of the
input frame pulse format.

Use the Block Programming Mode to initialize the Local and the Backplane Connection Memories. Refer
to Section 8.3, Connection Memory Block Programming.

Set ODE pin to HIGH after the connection memories are programmed to ensure that bus contention will
not occur at the serial stream outputs.

ZL50062/4

Data Sheet

Zarlink Semiconductor Inc.

In addition, the reset signal must be de-asserted less than 12

s after the frame boundary or more than 13

s after

the frame boundary, as illustrated in Figure 15. This can be achieved, for example, by synchronizing the
de-assertion of the reset signal with the input frame pulse FP8i.

Figure 15 - Hardware RESET De-assertion

8.0 Connection Memory

The device includes two connection memories, the Local Connection Memory and the Backplane Connection
Memory.

8.1 Local Connection Memory

The Local Connection Memory (LCM) is a 16-bit wide memory with 8,192 memory locations to support the Local
output port. The most significant bit of each word, bit[15], selects the source stream from either the Backplane
(LSRC = LOW) or the Local (LSRC = HIGH) port and determines the Backplane-to-Local or Local-to-Local data
routing. Bits[14:13] select the control modes of the Local output streams, the per-channel Message Mode and the
per-channel high impedance output control modes. In Connection Mode (bit[14] = LOW), bits[12:0] select the
source stream and channel number as detailed in Table 4. In Message Mode (bit[14] = HIGH), bits[12:8] are unused
and bits[7:0] contain the message byte to be transmitted. Bit[13] must be HIGH for Message Mode to ensure that
the output channel is not tri-stated.

8.2 Backplane Connection Memory

The Backplane Connection Memory (BCM) is a 16-bit wide memory with 8,192 memory locations to support the
Backplane output port. The most significant bit of each word, bit[15], selects the source stream from either the
Backplane (BSRC = HIGH) or the Local (BSRC = LOW) port and determines the Local-to-Backplane or
Backplane-to-Backplane data routing. Bit[14:13] select the control modes of the Backplane output streams, namely
the per-channel Message Mode and the per-channel high impedance output control mode. In Connection Mode
(bit[14] = LOW), bits[12:0] select the source stream and channel number as detailed in Table 4. In Message Mode
(bit[14] = HIGH), bits[12:8] are unused and bits[7:0] contain the message byte to be transmitted. Bit[13] must be
HIGH for Message Mode to ensure that the output channel is not tri-stated.

The Control Register bits MS[2:0] must be set to 000 to select the Local Connection Memory for the write and read
operations via the microprocessor port. The Control Register bits MS[2:0] must be set to 001 to select the
Backplane Connection Memory for the write and read operations via the microprocessor port. See Section 6.0,
Microprocessor Port, and Section 13.1, Control Register (CR) for details on microprocessor port access.

FP8i

RESET

De-assertion of RESET must not fall within this window

RESET assertion

RESET de-assertion

RESET

(case 1)

(case 2)

ZL50062/4

Data Sheet

Zarlink Semiconductor Inc.

8.3 Connection Memory Block Programming

This feature allows fast, simultaneous, initialization of the Local and Backplane Connection Memories after
power-up. When the Memory Block Programming mode is enabled, the contents of the Block Programming
Register (BPR) will be loaded into the connection memories. See Table 13 and Table 14 for details of the Control
Register and Block Programming Register values, respectively.

8.3.1 Memory Block Programming Procedure:

· Set the MBP bit in the Control Register from LOW to HIGH.

· Set the BPE bit to HIGH in the Block Programming Register (BPR). The Local Block Programming data bits,

LBPD[2:0], of the Block Programming Register, will be loaded into bits[15:13] of the Local Connection

Memory. The remaining bit positions are loaded with zeros as shown in Table 5.

Table 5 - Local Connection Memory in Block Programming Mode

The Backplane Block Programming data bits, BBPD[2:0], of the Block Programming Register, will be loaded into
bits[15:13] respectively, of the Backplane Connection Memory. The remaining bit positions are loaded with zeros as
shown in Table 6.

Table 6 - Backplane Connection Memory in Block Programming Mode

The Block Programming Register bit, BPE will be automatically reset LOW within 125

s, to indicate completion of

memory programming.

The Block Programming Mode can be terminated at any time prior to completion by clearing the BPE bit of the
Block Programming Register or the MBP bit of the Control Register.

Note that the default values (LOW) of LBPD[2:0] and BBPD[2:0] of the Block Programming Register, following a
device reset, can be used.

Source Stream Bit Rate

Source Stream No.

Source Channel No.

2Mbps

Bits[12:8]

legal values 0:31

Bits[7:0]

legal values 0:31

4Mbps

Bits[12:8]

legal values 0:31

Bits[7:0]

legal values 0:63

8Mbps

Bits[12:8]

legal values 0:31

Bits[7:0]

legal values 0:127

16Mbps

Bits[12:8]

legal values 0:31

Bits[7:0]

legal values 0:255

Table 4 - Local and Backplane Connection Memory Configuration

LBPD2

LBPD1

LBPD0

BBPD2

BBPD1

BBPD0

ZL50062/4

Data Sheet

Zarlink Semiconductor Inc.

During reset, all output channels go HIGH or high impedance, depending on the value of the LORS and BORS
pins, irrespective of the values in bits[14:13] of the connection memory.

9.0 Memory Built-In-Self-Test (BIST) Mode

As operation of the memory BIST will corrupt existing data, this test must only be initiated when the device is placed
"out-of-service" or isolated from live traffic.

The memory BIST mode is enabled through the microprocessor port (Section 13.7, Memory BIST Register).
Internal BIST memory controllers generate the memory test pattern (S-march) and control the memory test. The
memory test result is monitored through the Memory BIST Register.

10.0 JTAG Port

The ZL50062/64 JTAG interface conforms to the IEEE 1149.1 standard. The operation of the boundary-scan circuit
shall be controlled by an external Test Access Port (TAP) Controller.

10.1 Test Access Port (TAP)

The Test Access Port (TAP) consists of four input pins and one output pin described as follows:

· Test Clock Input (TCK)

TCK provides the clock for the TAP Controller and is independent of any on-chip clock. TCK permits the

shifting of test data into or out of the Boundary-Scan register cells under the control of the TAP Controller in

Boundary-Scan Mode.

· Test Mode Select Input (TMS)

The TAP controller uses the logic signals applied to the TMS input to control test operations. The TMS

signals are sampled at the rising edge of the TCK pulse. This pin in internally pulled to V

DD_IO

when not

driven from an external source.

· Test Data Input (TDi)

Depending on the previously applied data to the TMS input, the serial input data applied to the TDi port is

connected either to the Instruction Register or to a Test Data Register. Both registers are described in

Section 10.2, TAP Registers. The applied input data is sampled at the rising edge of TCK pulses. This pin is

internally pulled to V

DD_IO

when not driven from an external source.

· Test Data Output (TDo)

Depending on the previously applied sequence to the TMS input, the contents of either the instruction

falling edge of the TCK pulses. When no data is shifted through the boundary scan cells, the TDo output is

set to a high impedance state.

· Test Reset (TRST)

TRST provides an asynchronous Reset to the JTAG scan structure. This pin is internally pulled high when

not driven from an external source. This pin MUST be pulled low

for normal operation.

10.2 TAP Registers

The ZL50062/64 implements the public instructions defined in the IEEE-1149.1 standard with the provision of an
Instruction Register and three Test Data Registers.

10.2.1 Test Instruction Register

The JTAG interface contains a four-bit instruction register. Instructions are serially loaded into the Instruction
Register from the TDi pin when the TAP Controller is in the shift-IR state. Instructions are subsequently decoded to
achieve two basic functions: to select the Test Data Register to operate while the instruction is current, and to
define the serial Test Data Register path to shift data between TDi and TDo during data register scanning. Please
refer to Figure 27 for JTAG test port timing.

ZL50062/4

Data Sheet

Zarlink Semiconductor Inc.

10.2.2 Test Data Registers

10.2.2.1

The Boundary-Scan Register

The Boundary-Scan register consists of a series of Boundary-Scan cells arranged to form a scan path around the
boundary of the ZL50062/64 core logic.

10.2.2.2

The Bypass Register

The Bypass register is a single stage shift register to provide a one-bit path from TDi to TDo.

10.2.2.3 The Device Identification Register

The JTAG device ID for the ZL50062/64 is 0C38E14B

Version, Bits <31:28>:0000

Part No., Bits <27:12>:1100 0011 1000 1110

Manufacturer ID, Bits <11:1>:0001 0100 101

Header, Bit <0> (LSB):1

10.3 Boundary Scan Description Language (BSDL) File

A Boundary Scan Description Language (BSDL) file is available from Zarlink Semiconductor to aid in the use of the
IEEE 1149.1 test interface.

11.0 Memory Address Mappings

When the most significant bit, A14, of the address bus is set to '1', the microprocessor performs an access to one of
the device's internal memories. The Control Register bits MS[2:0] indicate which memory (Local Connection, Local
Data, Backplane Connection, or Backplane Data) is being accessed. Address bits A0-A13 indicate which location
within the particular memory is being accessed.

Table 7 - Address Map for Data and Connection Memory Locations (A14 = 1)

The device contains two data memory blocks, one for received Backplane data and one for received Local data. For
all data rates, the received data is converted to parallel format by internal serial-to-parallel converters and stored
sequentially in the relevant data memory.

Address Bit

Description

A14

Selects memory or register access (0 = register, 1 = memory).

Note that which memory (Local Connection, Local Data, Backplane Connection, Backplane
Data) is accessed depends on the MS[2:0] bits in the Control Register.

A13-A9

Stream address (0 - 31)

Streams 0 to 31 are used

A8-A0

Channel address (0 - 511)

Channels 0 to 31 are used when serial stream is at 2.048Mbps
Channels 0 to 63 are used when serial stream is at 4.096Mbps
Channels 0 to 127 are used when serial stream is at 8.192Mbps
Channels 0 to 255 are used when serial stream is at 16.384Mbps

ZL50062/4

Data Sheet

Zarlink Semiconductor Inc.

11.1 Local Data Memory Bit Definition

The 8-bit Local Data Memory (LDM) has 8,192 positions. The locations are associated with the Local input streams
and channels. As explained in the section above, address bits A13-A0 of the microprocessor define the addresses
of the streams and the channels. The LDM is read-only and configured as follows:

Table 8 - Local Data Memory (LDM) Bits

Note that the Local Data Memory is actually an 8-bit wide memory. The most significant 8 bits expressed in the
table above are presented to provide 16-bit microprocessor read accesses.

11.2 Backplane Data Memory Bit Definition

The 8-bit Backplane Data Memory (BDM) has 8,192 positions. The locations are associated with the Backplane
input streams and channels. As explained previously, address bits A13-A0 of the microprocessor define the
addresses of the streams and the channels. The BDM is read-only and configured as follows:

Table 9 - Backplane Data Memory (BDM) Bits

Note that the Backplane Data Memory is actually an 8-bit wide memory. The most significant 8 bits expressed in the
table above are presented to provide 16-bit microprocessor read accesses.

11.3 Local Connection Memory Bit Definition

The Local Connection Memory (LCM) has 8,192 addresses of 16-bit words. Each address, accessed through bits
A13-A0 of the microprocessor port, is allocated to an individual Local output stream and channel. The bit definition
for each 16-bit word is presented in Table 10 for Source-to-Local connections.

The most-significant bit in the memory location, LSRC, selects the switch configuration for Backplane-to-Local or
Local-to-Local. When the per-channel Message Mode is selected (LMM memory bit = HIGH), the lower byte of the
LCM word (LCAB[7:0]) will be transmitted as data on the output stream (LSTo0-31) in place of data defined by the
Source Control, Stream and Channel Address bits.

Bit

Name

Description

15:8

Reserved

Set to a default value of 8'h00.

7:0 LDM

Local Data Memory - Local Input Channel Data.

The LDM[7:0] bits contain the timeslot data from the Local side input TDM
stream. LDM[7] corresponds to the first bit received, i.e. bit 7 in ST-BUS mode,
bit 0 in GCI-Bus mode. See Figure 7, ST-BUS and GCI-Bus Input Timing
Diagram for Different Data Rates for the arrival order of the bits.

Bit

Name

Description

15:8

Reserved

Set to a default value of 8'h00.

7:0 BDM

Backplane Data Memory - Backplane Input Channel Data.
The BDM[7:0] bits contain the timeslot data from the Backplane side input TDM
stream. BDM[7] corresponds to the first bit received, i.e. bit 7 in ST-BUS mode,
bit 0 in GCI-Bus mode. See Figure 7, ST-BUS and GCI-Bus Input Timing
Diagram for Different Data Rates for the arrival order of the bits

ZL50062/4

Data Sheet

Zarlink Semiconductor Inc.

11.4 Backplane Connection Memory Bit Definition

The Backplane Connection Memory (BCM) has 8,192 addresses of 16-bit words. Each address, accessed through
bits A13-A0 of the microprocessor port, is allocated to an individual Backplane output stream and channel. The bit
definition for each 16-bit word is presented in Table 11 for Source-to-Backplane connections.

The most-significant bit in the memory location, BSRC, selects the switch configuration for Local-to-Backplane or
Backplane-to-Backplane. When the per-channel Message Mode is selected (BMM memory bit = HIGH), the lower
byte of the BCM word (BCAB[7:0]) will be transmitted as data on the output stream (BSTo0-31) in place of data
defined by the Source Control, Stream and Channel Address bits.

Bit

Name

Description

LSRC

Local Source Control Bit

When LOW, the source is from the Backplane input port (Backplane Data Memory).
When HIGH, the source is from the Local input port (Local Data Memory).
Ignored when LMM is set HIGH.

14 LMM

Local Message Mode Bit

When LOW, the channel is in Connection Mode (data to be output on channel originated in
Local or Backplane Data Memory).
When HIGH, the channel is in Message Mode (data to be output on channel originated in
Local Connection Memory).

Local Output Enable Bit

When LOW, the channel may be high impedance, either at the device output, or set by an
external buffer dependent upon the LORS pin.
When HIGH, the channel is active.

12:8

LSAB[4:0]

Source Stream Address Bits

The binary value of these 5 bits represents the input stream number.
Ignored when LMM is set HIGH.

7:0 LCAB[7:0]

Source Channel Address Bits / Message Mode Data

The binary value of these 8 bits represents the input channel number when LMM is set
LOW.
Transmitted as data when LMM is set HIGH.
Note: When LMM is set HIGH, in both ST-BUS and GCI-Bus modes, the LCAB[7:0] bits are
output sequentially to the timeslot with LCAB[7] being output first.

Table 10 - LCM Bits for Source-to-Local Switching

Bit

Name

Description

BSRC

Backplane Source Control Bit

When LOW, the source is from the Local input port (Local Data Memory).
When HIGH, the source is from the Backplane input port (Backplane Data Memory).
Ignored when BMM is set HIGH.

14 BMM

Backplane Message Mode Bit

When LOW, the channel is in Connection Mode (data to be output on channel originated in
Backplane or Local Data Memory).
When HIGH, the channel is in Message Mode (data to be output on channel originated in
Backplane Connection Memory).

Table 11 - BCM Bits for Source-to-Backplane Switching

ZL50062/4

Data Sheet

Zarlink Semiconductor Inc.

12.0 Internal Register Mappings

When the most significant bit, A14, of the address bus is set to '0', the microprocessor is performing an access to
one of the device's internal registers. Address bits A13-A0 indicate which particular register is being accessed.

Backplane Output Enable Bit

When LOW, the channel may be high impedance, either at the device output, or set by an
external buffer dependent upon the BORS pin.
When HIGH, the channel is active.

12:8

BSAB[4:0]

Source Stream Address Bits

The binary value of these 5 bits represents the input stream number.
Ignored when BMM is set HIGH.

7:0 BCAB[7:0]

Source Channel Address Bits / Message Mode Data

The binary value of these 8 bits represents the input channel number when BMM is set
LOW.
Transmitted as data when BMM is set HIGH.
Note: When BMM is set HIGH, in both ST-BUS and GCI-Bus modes, the BCAB[7:0] bits
are output sequentially to the timeslot with BCAB[7] being output first.

A14-A0

Register

0000

Control Register, CR

0001

Block Programming Register, BPR

0023

0042

Local Input Bit Delay Register 0 - 31, LIDR0 - 31

0063

0082

Backplane Input Bit Delay Register 0 - 31, BIDR0 - 31

0083

00A2

Local Output Advancement Register 0 - 31, LOAR0 - 31

00A3

00C2

Backplane Output Advancement Register 0 - 31, BOAR0 - 31

014D

Memory BIST Register, MBISTR

1001

Bit Rate Register, BRR

3FFF

Device Identification Register, DIR

Table 12 - Address Map for Registers (A14 = 0)

Bit

Name

Description

Table 11 - BCM Bits for Source-to-Backplane Switching (continued)

ZL50062/4

Data Sheet

Zarlink Semiconductor Inc.

13.0 Detailed Register Descriptions

This section describes the registers that are used in the device.

13.1 Control Register (CR)

Address 0000

The Control Register defines which memory is to be accessed. It initiates the memory block programming mode
and selects the Backplane and Local data rate modes. The Control Register (CR) is configured as follows:

Bit

Name

Reset

Value

Description

15:13

FBD_

MODE[2:0]

Frame Boundary Discriminator Mode

When set to 111

, the Frame Boundary Discriminator can handle both low

frequency and high frequency jitter.
When set to 000

, the Frame Boundary Discriminator is set to handle lower

frequency jitter only.
All other values are reserved.
These bits are ignored when FBDEN bit is LOW.

SMPL_

MODE

Sample Point Mode

When LOW the input bit sampling point is always at the 3/4 bit location. The input bit
fractional delay is programmed in 1/4 bit increments from 0 to 7 3/4 as per the value
of the LIDR0 to LIDR31 and BIDR0 to BIDR31 registers.
When HIGH, the input bit sampling point is programmed to the 3/4, 4/4, 1/4, 2/4 bit
location as per the value of the LIDR0 to LIDR31 and BIDR0 to BIDR31 registers. In
addition, the incoming data can be delayed by 0 to 7 bits in 1 bit increments.
See Table 15, Table 16, Table 17 and Table 18 for details.

Reserved

Reserved
Must be set to 0 for normal operation

FBDEN

Frame Boundary Discriminator Enable
When LOW, the frame boundary discriminator function is disabled.
When HIGH, enables frame boundary discriminator function which allows the
device to tolerate inconsistent frame boundaries, hence improving the tolerance to
cycle-to-cycle variation on the input clock.

Reserved

Reserved
Must be set to 0 for normal operation

FPW

Frame Pulse Width
When LOW, the user must apply a 122ns frame pulse on FP8i; the FP8o pin will
output a 122ns wide frame pulse; FP16o will output a 61ns wide frame pulse.
When HIGH, the user must apply a 244ns frame pulse on FP8i; the FP8o pin will
output a 244ns wide frame pulse; FP16o will output a 122ns wide frame pulse.

Reserved

Reserved
Must be set to 0 for normal operation

C8IPOL

8MHz Input Clock Polarity
The frame boundary is aligned to the falling or rising edge of the input clock.
When LOW, the frame boundary is aligned to the clock falling edge.
When HIGH, the frame boundary is aligned to the clock rising edge.

COPOL

Output Clock Polarity
When LOW, the output clock has the same polarity as the input clock.
When HIGH, the output clock is inverted.
This applies to both the 8MHz (C8o) and 16MHz (C16o) output clocks.

Table 13 - Control Register Bits

ZL50062/4

Data Sheet

Zarlink Semiconductor Inc.

13.2 Block Programming Register (BPR)

Address 0001

The Block Programming Register stores the bit patterns to be loaded into the connection memories when the
Memory Block Programming feature is enabled. The BPE, LBPD[2:0] and BBPD[2:0] bits in the BPR register must
be defined in the same write operation.

The BPE bit is set HIGH to commence the block programming operation. Programming is completed in one frame
period and may be initiated at any time within a frame. The BPE bit returns to LOW to indicate that the block
programming function has completed.

When BPE is HIGH, no other bits of the BPR register may be changed for at least a single frame period, except to
abort the programming operation. The programming operation may be aborted by setting either BPE to LOW, or the
Control Register bit, MBP, to LOW.

The BPR register is configured as follows.

Table 14 - Block Programming Register Bits

Bit

Name

Reset

Value

Description

15:7

Reserved

Reserved
Must be set to 0 for normal operation

6:4

BBPD[2:0]

Backplane Block Programming Data
These bits refer to the value loaded into the Backplane Connection Memory
(BCM) when the Memory Block Programming feature is activated.
When the MBP bit in the Control Register (CR) is set HIGH and BPE (in this
register) is set HIGH, the contents of bits BBPD[2:0] are loaded into bits 15-13,
respectively, of the BCM. Bits 12-0 of the BCM are set LOW.

3:1

LBPD[2:0]

Local Block Programming Data
These bits refer to the value loaded into the Local Connection Memory (LCM),
when the Memory Block Programming feature is activated.
When the MBP bit in the Control Register is set HIGH and BPE (in this register)
is set HIGH, the contents of bits LBPD[2:0] are loaded into bits 15-13,
respectively, of the LCM. Bits 12-0 of the LCM are set LOW.

BPE

Block Programming Enable
A LOW to HIGH transition of this bit enables the Memory Block Programming
function. A LOW will be returned after 125

s, upon completion of programming.

Set LOW to abort the programming operation.

ZL50062/4

Data Sheet

Zarlink Semiconductor Inc.

13.3.1 Local Input Delay Bits 4-0 (LID[4:0])

When SMPL_MODE = LOW, these five bits define the amount of input bit delay adjustment that the receiver uses to
sample each input. Input bit delay adjustment can range up to 7

bit periods forward, with resolution of

bit

period. The default sampling point is at the

bit location.

This can be described as: no. of bits delay = LID[4:0] / 4
For example, if LID[4:0] is set to 10011 (19), the input bit delay = 19 *

= 4

When SMPL_MODE = HIGH, the binary value of LID[1:0] refers to the input bit sampling point (

). LID[4:2]

refer to the integer bit delay value (0 to 7 bits). This means that bits can be delayed by an integer value of up to 7
and that the sampling point can vary from

-bit increments.

Table 16 illustrates the bit delay and sampling point selection.

LIDn

SMPL_MODE

= LOW

SMPL_MODE

= HIGH

LID4

LID3

LID2

LID1

LID0

Input Data

Bit Delay

Input Data

Bit Delay

Input Data

Sampling

Point

0 (Default)

3/4

1/4

4/4

1/2

1/4

3/4

2/4

3/4

1 1/4

4/4

1 1/2

1/4

1 3/4

2/4

3/4

2 1/4

4/4

2 1/2

1/4

2 3/4

2/4

3/4

3 1/4

4/4

3 1/2

1/4

3 3/4

2/4

3/4

4 1/4

4/4

4 1/2

1/4

4 3/4

2/4

3/4

5 1/4

4/4

5 1/2

1/4

5 3/4

2/4

3/4

6 1/4

4/4

6 1/2

1/4

6 3/4

2/4

Table 16 - Local Input Bit Delay and Sampling Point Programming Table

ZL50062/4

Data Sheet

Zarlink Semiconductor Inc.

13.4 Backplane Input Bit Delay Registers (BIDR0 to BIDR31)

Addresses 0063

to 0082

There are thirty-two Backplane Input Delay Registers (BIDR0 to BIDR31).

When the SMPL_MODE bit in the Control Register is LOW, the input data sampling point defaults to the 3/4 bit
location and BIDR0 to BIDR31 define the input bit and fractional bit delay of each Backplane stream. The possible
bit delay adjustment is up to 7

bits, in steps of

bit.

When the SMPL_MODE bit is HIGH, BIDR0 to BIDR31 define the input bit sampling point as well as the integer bit
delay of each Backplane stream. The input bit sampling point can be adjusted in 1/4 bit increments. The bit delay
can be adjusted in 1-bit increments from 0 to 7 bits.

The BIDR0 to BIDR31 registers are configured as follows:

Table 17 - Backplane Input Bit Delay Register (BIDRn) Bits

3/4

7 1/4

4/4

7 1/2

1/4

7 3/4

2/4

BIDRn Bit

(where n = 0 to 31)

Name

Reset

Value

Description

15:5

Reserved

Reserved
Must be set to 0 for normal operation

4:0

BID[4:0]

Backplane Input Bit Delay Register
When SMPL_MODE = LOW, the binary value of these
bits refers to the input bit and fractional bit delay value (0
to 7

When SMPL_MODE = HIGH, the binary value of BID[1:0]
refers to the input bit sampling point (

). BID[4:2]

refer to the integer bit delay value (0 to 7 bits).

LIDn

SMPL_MODE

= LOW

SMPL_MODE

= HIGH

LID4

LID3

LID2

LID1

LID0

Input Data

Bit Delay

Input Data

Bit Delay

Input Data

Sampling

Point

Table 16 - Local Input Bit Delay and Sampling Point Programming Table (continued)

ZL50062/4

Data Sheet

Zarlink Semiconductor Inc.

13.4.1 Backplane Input Delay Bits 4-0 (BID[4:0])

When SMPL_MODE = LOW, these five bits define the amount of input bit delay adjustment that the receiver uses to
sample each input. Input bit delay adjustment can range up to 7

bit periods forward, with resolution of

bit

period. The default sampling point is at the

bit location.

This can be described as: no. of bits delay = BID[4:0] / 4

For example, if BID[4:0] is set to 10011 (19), the input bit delay = 19 *

= 4

When SMPL_MODE = HIGH, the binary value of BID[1:0] refers to the input bit sampling point (

). BID[4:2]

refer to the integer bit delay value (0 to 7 bits). This means that bits can be delayed by an integer value of up to 7
and that the sampling point can vary from

-bit increments.

Table 18 illustrates the bit delay and sampling point selection.

BIDn

SMPL_MODE

= LOW

SMPL_MODE

= HIGH

BID4

BID3

BID2

BID1

BID0

Input Data

Bit Delay

Input Data

Bit Delay

Input Data

Sampling

Point

0 (Default)

3/4

1/4

4/4

1/2

1/4

3/4

2/4

3/4

1 1/4

4/4

1 1/2

1/4

1 3/4

2/4

3/4

2 1/4

4/4

2 1/2

1/4

2 3/4

2/4

3/4

3 1/4

4/4

3 1/2

1/4

3 3/4

2/4

3/4

4 1/4

4/4

4 1/2

1/4

4 3/4

2/4

3/4

5 1/4

4/4

5 1/2

1/4

5 3/4

2/4

3/4

6 1/4

4/4

6 1/2

1/4

Table 18 - Backplane Input Bit Delay and Sampling Point Programming Table

ZL50062/4

Data Sheet

Zarlink Semiconductor Inc.

13.5 Local Output Advancement Registers (LOAR0 to LOAR31)

Addresses 0083

to 00A2

Thirty-two Local Output Advancement Registers (LOAR0 to LOAR31) allow users to program the output
advancement for output data streams LSTo0 to LSTo31. The possible adjustment is -2 (15ns), -4 (31ns) or -6 (46ns)
cycles of the internal system clock (131.072MHz).

The LOAR0 to LOAR31 registers are configured as follows:

Table 19 - Local Output Advancement Register (LOAR) Bits

13.5.1 Local Output Advancement Bits 1-0 (LOA1-LOA0)

The binary value of these two bits indicates the amount of offset that a particular stream output can be advanced
with respect to the output frame boundary. When the advancement is 0, the serial output stream has the normal
alignment with the generated frame pulse FP8o.

6 3/4

2/4

3/4

7 1/4

4/4

7 1/2

1/4

7 3/4

2/4

LOARn Bit

(where n = 0 to 31)

Name

Reset

Value

Description

15:2

Reserved

Reserved
Must be set to 0 for normal operation

1:0

LOA[1:0]

Local Output Advancement Value

Local Output Advancement

Corresponding

Advancement Bits

Clock Rate 131.072 MHz

LOA1

LOA0

0 (Default)

-2 cycles (~15ns)

-4 cycles (~31ns)

-6 cycles (~46ns)

Table 20 - Local Output Advancement (LOAR) Programming Table

BIDn

SMPL_MODE

= LOW

SMPL_MODE

= HIGH

BID4

BID3

BID2

BID1

BID0

Input Data

Bit Delay

Input Data

Bit Delay

Input Data

Sampling

Point

Table 18 - Backplane Input Bit Delay and Sampling Point Programming Table (continued)

ZL50062/4

Data Sheet

Zarlink Semiconductor Inc.

13.6 Backplane Output Advancement Registers (BOAR0 - BOAR31)

Addresses 00A3

to 00C2

Thirty-two Backplane Output Advancement Registers (BOAR0 to BOAR31) allow users to program the output
advancement for output data streams BSTo0 to BSTo31. The possible adjustment is -2 (15ns), -4 (31ns) or -6
(46ns) cycles of the internal system clock (131.072MHz).

The BOAR0 to BOAR31 registers are configured as follows:

Table 21 - Backplane Output Advancement Register (BOAR) Bits

13.6.1 Backplane Output Advancement Bits 1-0 (BOA1-BOA0)

13.7 Memory BIST Register

Address 014D

The Memory BIST Register enables the self-test of chip memory. Two consecutive write operations are required to
start MBIST: the first with only Bit 12 (LV_TM) set HIGH (i.e. 1000h); the second with Bit 12 maintained HIGH but
with the required start bit(s) also set HIGH.

The MBISTR register is configured as follows:

BOARn Bit

(where n = 0 to 31)

Name

Reset

Value

Description

15:2

Reserved

Reserved
Must be set to 0 for normal operation

1:0

BOA[1:0]

Backplane Output Advancement Value

Backplane Output Advancement

Corresponding

Advancement Bits

Clock Rate 131.072 MHz

BOA1

BOA0

0 (Default)

-2 cycles (~15ns)

-4 cycles (~31ns)

-6 cycles (~46ns)

Table 22 - Backplane Output Advancement (BOAR) Programming Table

Bit

Name

Reset

Value

Description

15:13

Reserved

Reserved

Must be set to 0 for normal operation

Table 23 - Memory BIST Register (MBISTR) Bits

ZL50062/4

Data Sheet

Zarlink Semiconductor Inc.

LV_TM

MBIST Test Enable

Set HIGH to enable MBIST mode.
Set LOW for normal operation.

BISTSDB

Backplane Data Memory Start BIST Sequence

Sequence enabled on LOW to HIGH transition.

BISTCDB

Backplane Data Memory BIST Sequence Completed (Read-only)

This bit must be polled - when HIGH, indicates completion of Backplane Data
Memory BIST sequence.

BISTPDB

Backplane Data Memory Pass/Fail Bit (Read-only)

This bit indicates the Pass/Fail status following completion of the Backplane
Data Memory BIST sequence (indicated by assertion of BISTCDB).
A HIGH indicates Pass, a LOW indicates Fail.

BISTSDL

Local Data Memory Start BIST Sequence

Sequence enabled on LOW to HIGH transition.

BISTCDL

Local Data Memory BIST Sequence Completed (Read-only)

This bit must be polled - when HIGH, indicates completion of Local Data
Memory BIST sequence.

BISTPDL

Local Data Memory Pass/Fail Bit (Read-only)

This bit indicates the Pass/Fail status following completion of the Local Data
Memory BIST sequence (indicated by assertion of BISTCDL).
A HIGH indicates Pass, a LOW indicates Fail.

BISTSCB

Backplane Connection Memory Start BIST Sequence

Sequence enabled on LOW to HIGH transition.

BISTCCB

Backplane Connection Memory BIST Sequence Completed (Read-only)

This bit must be polled - when HIGH, indicates completion of Backplane
Connection Memory BIST sequence.

BISTPCB

Backplane Connection Memory Pass/Fail Bit (Read-only)

This bit indicates the Pass/Fail status following completion of the Backplane
Connection Memory BIST sequence (indicated by assertion of BISTCCB).
A HIGH indicates Pass, a LOW indicates Fail.

BISTSCL

Local Connection Memory Start BIST Sequence

Sequence enabled on LOW to HIGH transition.

BISTCCL

Local Connection Memory BIST Sequence Completed (Read-only)

This bit must be polled - when HIGH, indicates completion of Local Connection
Memory BIST sequence.

BISTPCL

Local Connection Memory Pass/Fail Bit (Read-only)

This bit indicates the Pass/Fail status following completion of the Local
Connection Memory BIST sequence (indicated by assertion of BISTCCL).
A HIGH indicates Pass, a LOW indicates Fail.

Bit

Name

Reset

Value

Description

Table 23 - Memory BIST Register (MBISTR) Bits (continued)

ZL50062/4

Data Sheet

Zarlink Semiconductor Inc.

15.0 AC Electrical Characteristics

AC Electrical Characteristics

Timing Parameter Measurement: Voltage Levels

Characteristics

Sym

Level

Units

Conditions

CMOS Threshold

0.5V

DD_IO

3.0V < V

DD_IO

< 3.6V

Rise/Fall Threshold Voltage High

0.7V

DD_IO

3.0V < V

DD_IO

< 3.6V

Rise/Fall Threshold Voltage Low

0.3V

DD_IO

3.0V < V

DD_IO

< 3.6V

Input and Output Clock Timing

Characteristic

Sym

Min

Typ

Max

Units

Notes

FP8i, Input Frame Pulse Width

IFPW244

IFPW122

210

244
122

350
220

Input Frame Pulse Setup Time
(before C8i clock falling/rising edge)

IFPS244

IfPS122

5
5

110

Input Frame Pulse Hold Time
(from C8i clock falling/rising edge)

IFPH244

IFPH122

0
0

110

C8i Clock Period (Average value, does not
consider the effects of jitter)

ICP

120

122

124

C8i Clock Pulse Width High

ICH

C8i Clock Pulse Width Low

ICL

C8i Clock Rise/Fall Time

rIC

, t

fIC

C8i Cycle to Cycle Variation
(This values is with respect to the typical C8i
Clock Period, and using mid-bit sampling)

CCVIC

-7.0

-8.5

7.0

8.5

16Mbps
or lower.

Output Frame Boundary Offset

OFBOS

9.5

FP8o Frame Pulse Width

OFPW8_244

OFPW8_122

224

117

244
122

264
127

FPW =1
FPW=0
C

=60pF

FP8o Output Delay
(from frame pulse edge to output frame
boundary)

FPFBF8_244

FPFBF8_122

117

122

127

FPW =1
FPW=0
C

=60pF

FP8o Output Delay
(from output frame boundary to frame pulse
edge)

FBFPF8_244

FBFPF8_122

117

122

127

FPW =1
FPW=0
C

=60pF

C8o Clock Period

OCP8

117

122

127

=60pF

C8o Clock Pulse Width High

OCH8

C8o Clock Pulse Width Low

OCL8

C8o Clock Rise/Fall Time

rOC8

, t

fOC8

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