2.2
YTD423
P
eripheral
LSI
In
terface
Blo
c
k
Diagram
YTD423
Memory
System data bus (D0 ~ D15)
Control signal bus
Peripheral LSI
B1 , B2
CLK
MPU
System interrupt
controller
(8086 , 68000 etc.)
A0 ~
A23
D0 ~
D15
CS
CS
A0 ~
A23
D0 ~
D7
R/W
CS
A0 ~
A23
D0 ~
D15
HRD
LRD
HTD
LTD
YTD421
or
YTD428
Decoder
System address bus (A0 ~ A23)
A0 ~
A23
D0 ~
D15
Figure
2:
P
eripheral
LSI
In
terface
Blo
c
k
Diagram
5