April 15, 2001
Nallatech Limited
10-14 Market Street
Kilsyth, Glasgow
G65 0BD
Scotland
Phone:
+1 44 7020 986532
Fax:
+1 44 7020 986534
E-mail:
info@nallatech.com
Website:
www.nallatech.com
Introduction
This board allows designers to quickly evaluate the perfor-
mance of Xilinx's 64-bit / 66 MHz PCI core including data
throughput capabilities across the PCI bus to an on-board
SDRAM SODIMM module. In addition it serves as a proto-
typing platform for PCI and different system applications.
Expansion capability is provided through an interface stan-
dard known as DIME. Two DIME module sites are present
on the PCI card providing users with the ability to build cus-
tom systems from a variety of solutions provided by this
royalty free, open module standard.
Features
Fully compliant universal PCI Slot Card
-
Automatically adjusts I/O buffers to match V
IO
using
auto-sensing circuitry
PCI 2.2 compliant
Supports 32 & 64 bit PCI in frequencies up to 66 MHz
Expansion capability for additional functionality through
2 DIME Module Sites
Requires only a 5V supply from the host motherboard
Configured over SelectMap Interface from Flash
memory via 95144XL CPLD
Flash memory reconfigured via Xilinx MultiLINX
download cable
Sub-10 ms configuration time compliant with 64-bit PCI
specification requirements
-
50Mbytes per second configuration rate
Direct SelectMAP Virtex configuration using MultiLINX
download cable
PCI & SDRAM demonstration bitstream
Demonstration software
4M x 64 (32Mbytes) SDRAM in SODIMM socket
12 LEDs showing:
-
Power good for 5V, 3.3V, 2.5V & 1.8V
-
V
IO
level and 3.3V or 5V bitstream loaded
-
FPGA DONE pin
-
Three user LEDs - Expandable to 23 LEDs
50MHz and programmable oscillator
Figure 1: Ballyinx PCI64 Prototyping Board
Ballyinx PCI64 PCI Prototyping
Board
April 15, 2001
Data Sheet
Ballyinx PCI64 PCI Prototyping Board
April 15, 2001
General Description
The Nallatech PCI64 Prototyping Card is provided with the
Xilinx PCI64/66 Design Kit, available from Xilinx. This card
allows designers to quickly evaluate the performance of the
Xilinx PCI64/66 LogiCORE design in their system. More-
over, it serves as a prototyping platform for custom PCI and
system applications. The firmware and software provided
clearly demonstrate the capabilities of the LogiCORE
design along with the performance enhancements that the
Virtex offers for SDRAM applications.
Further, the Nallatech PCI64 board demonstrates how to
build a universal PCI card. A universal PCI interface
requires the inclusion of diode clamps to 3.3 V for a 3.3 V
signaling environment, and the exclusion of these in a 5 V
signaling environment. To accomplish this, the Virtex FPGA
must load different bitstreams depending on the signalling
environment. This card demonstrates one way of achieving
this.
The Xilinx PCI64 Design Kit provides the user with a PCI
design example. This includes a demonstration bitstream
with:
Xilinx Real 64/66 PCI interface
Xilinx PCI Bridge interface core
Xilinx SDRAM Interface core
The block diagram, seen in Figure 2, shows the basic inter-
connectivity of the various interfaces to the Virtex FPGA.
Two pieces of software demonstrate the performance of the
PCI bus and the SDRAM interface capabilities of the Virtex
FPGA.
Figure 2: PCI64 Card Block Diagram
The Virtex FPGA is configured at power on over its Select
Map interface from an high speed Flash memory. An
XC95144 CPLD controls the Flash and the transfer of data
to the FPGAs Select Map port. This data is transferred over
the selectmap port at 50MBytes/Sec, thus allowing the
FPGA to be configured in under 10 milliseconds. This is a
50x improvement over the fast serial mode transfer rate.
Two DIME Module sites provide the user with access to an
ever growing variety of interfaces and data processing
nodes. In fact, full system solutions can be developed with
just this card and one or two DIME modules. Therefore the
user often need not bother with the development of custom
PCBs for a solution to their system problem. For more
details on available DIME modules and more information
on the standard, go to the Nallatech web site,
http://www.nallatech.com
Configuration
The FPGA must be configured in less than 100 mS in order
for the PCI interface to detect the PCI bus width (32- or 64-
bits). In order to achieve this the Select Map configuration
mode is utilized together with an Intel Fast Flash memory.
An XC95144 CPLD is used to control the booting process.
The Flash memory can be erased and reprogrammed with
new bitstreams using the Xilinx MultiLINX Download Cable.
The CPLD, under the control of either the PCI signalling
voltage (Vio) or the MultiLINX cable, if connected, will enter
one of several modes:
Default Mode (no MultiLINX cable connected)
Load 3.3 V PCI bitstream from Flash Memory
Load 5 V PCI bitstream from Flash Memory
Program Mode (MultiLINX cable connected)
Erase 3.3 V PCI bitstream
Erase 5 V PCI bitstream
Program 3.3 V PCI bitstream
Program 5 V PCI bitstream
Pass-through mode for direct programming of Virtex
The default mode demonstrates how a universal PCI card
can be built. The Program mode gives the user control over
the flash chip.
Alternatively, Nallatech provides a product that can be
added to a user's PCI interface that allows the Flash Con-
figuration Memory to be reprogrammed directly over the
PCI interface using a software Utility. This allows users of
the PCI logicore to easily integrate Firmware Field
upgrades into their products.
Software
Two software programs are included, one demonstrating
the performance of the PCI bus and the SDRAM interface
capabilities of the Virtex FPGA and the other allows the
user to program the flash and FPGA via the MultiLINX
cable.
Device Driver Program
This demonstration program, shown in Figure 3 and Figure
4, provides a GUI interface to the PCI Bridge Design part of
the PCI LogiCORE. The SDRAM is connected to the back
of this bridge and DMA transfers to and from this memory
Flash
Memory
Select Map I/F
Config
Control
EPLD
D
I
M
E
S
l
o
t
0
D
I
M
E
S
l
o
t
1
XCV300
VIRTEX
FPGA
4Mx64
SDRAM
SODIMM
Module
93
24
20
64
68
PCI BUS 64 Bit, 66MHz
x9024
MultiLINX
Interface
R
April 15, 2001
can be performed and the transfer rate is displayed. This
interface also provides the user with the basic operation of
the Xilinx PCI Bridge Design.
This programs also allows the user to download an image
to the SDRAM memory and retrieve it. Any errors in the
transfer will be recorded and graphically displayed on the
GUI. For more details on the inner working of the FPGA
design, refer to the Bridge Design for the Ballyinx PCI64
Prototyping Board data sheet, available in the PCI64
lounge.
Figure 3: Image Transfer Demonstration
Figure 4: Block Mode DMA Transfer Demonstration
Ballyinx PCI64 PCI Prototyping Board
April 15, 2001
Figure 5: MultiLINX Access Program
Options
All options are available directly from Nallatech.
Additional Ballyinx boards
Ballyinx boards with Virtex V800 FPGA
JTAG FPGA Configuration Software (for FPGAs on
DIME Modules)
Reprogram Bitstream in Boot Flash Via PCI Interface
(for easy field upgrades)
Ballyvision - NTSC/PAL Video Capture and Display
DIME Module
Ballyblue - Dual V1000 Virtex FPGA DIME Module for
over 2 Million Gates
Ballytest - DIME Connector Breakout Module
Ballydiff - Low Voltage Differential Signalling, LVDS,
DIME Module
Custom DIME Module Design Service is Available
For the latest information on new DIME modules, visit the
Nallatech web site:
http://www.nallatech.com
Ordering Information
The PCI64 board is available from Xilinx as part of the
PCI64 Design Kit.
The Design Kit includes:
Xilinx Real 64/66 PCI LogiCORE Interface
Ballyinx PCI64 Prototyping board
Compuware Driver Bundle with SoftICE
-
Includes Full Production License
MultiLINX Download cable
MultiLINX - Ballyinx connectors
Printed documentation
Training
Contact your local Xilinx sales office to purchase these
parts.
MultiLINX Access
The MultiLINX access program, as seen here in Fig-
ure 5, provides a means for the user to erase and
program the 3.3 V and 5 V bitstreams in the on-board
flash device, and to directly program the FPGA via a
pass-through mode in the CPLD. The CPLD handles
the details of programming the flash device, accept-
ing data from the MultiLINX cable via the SelectMAP
interface.
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