Xicor, Inc. 2000 Patents Pending
7025-1.4 9/6/00 EP
Characteristics subject to change without notice.
1 of 16
BLOCK DIAGRAM
Logic
CS
SCL
SDA
RST
Interface
8K Byte
Data Transfer
Array Access
Enable
Reset
Response Register
Password Array
and Password
Verification Logic
Chip Enable
Retry Counter
SerialFlash Array
32 Byte
SerialFlash Array
Array 0
Array 1
(Password Protected)
(Password Protected)
64K
X76F640
8Kx8+32x8
Secure SerialFlash
FEATURES
64-bit Password Security
--Five 64-bit passwords for read, program
and reset
8192 Byte+32 Byte Password Protected Arrays
--Seperate read passwords
--Seperate write passwords
--Reset password
Programmable Passwords
Retry Counter Register
--Allows 8 tries before clearing of both arrays
--Password protected reset
32-Bit Response to Reset (RST Input)
32 Byte Sector Program
400kHz Clock Rate
2 Wire Serial Interface
Low Power CMOS
--2.7 to 5.5V operation
--Standby current less than 1A
--Active current less than 3 mA
High Reliability Endurance:
--100,000 write cycles
Data Retention: 100 Years
Available in:
--8-lead SOIC
--SmartCard module
DESCRIPTION
The X76F640 is a Password Access Security Supervisor,
containing one 65536-bit Secure SerialFlash array and
one 256-bit Secure SerialFlash array. Access to each
memory array is controlled by two 64-bit passwords.
These passwords protect read and write operations of
the memory array. A separate RESET password is used
to reset the passwords and clear the memory arrays in
the event the read and write passwords are lost.
The X76F640 features a serial interface and software
protocol allowing operation on a popular two wire bus.
The bus signals are a clock Input (SCL) and a bidirec-
tional data input and output (SDA). Access to the
device is controlled through a chip select (CS) input,
allowing any number of devices to share the same bus.
The X76F640 also features a synchronous response
to reset providing an automatic output of a hard-wired
32-bit data stream conforming to the industry standard
for memory cards.
The X76F640 utilizes Xicor's proprietary Direct Write
TM
cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.
X76F640
Characteristics subject to change without notice.
2 of 16
PIN DESCRIPTIONS
Serial Clock (SCL)
The SCL input is used to clock all data into and out of
the device.
Serial Data (SDA)
SDA is a true three state serial data input/output pin.
During a read cycle, data is shifted out on this pin. Dur-
ing a write cycle, data is shifted in on this pin. In all
other cases, this pin is in a high impedance state.
Chip Enable (CS)
When CS is high, the X76F640 is deselected and the
SDA pin is at high impedance and unless an internal
write operation is underway, the X76F640 will be in
standby mode. CS low enables the X76F640, placing it
in the active mode.
Reset (RST)
RST is a device reset pin. When RST is pulsed high
while CS is low the X76F640 will output 32 bits of fixed
data which conforms to the standard for "synchronous
response to reset". CS must remain LOW and the part
must not be in a write cycle for the response to reset to
occur. See Figure 11. If at any time during the
response to reset CS goes HIGH, the response to
reset will be aborted and the part will return to the
standby state. The response to reset is "mask pro-
grammable" only!
DEVICE OPERATION
There are two primary modes of operation for the
X76F640; Protected READ and protected WRITE. Pro-
tected operations must be performed with one of four
8-byte passwords.
The basic method of communication for the device is
established by first enabling the device (CS LOW),
generating a start condition, then transmitting a com-
mand, followed by the correct password. All parts will
be shipped from the factory with all passwords equal to
`0'. The user must perform ACK Polling to determine
the validity of the password, before starting a data
transfer (see Acknowledge Polling.) Only after the cor-
rect password is accepted and a ACK polling has been
performed, can the data transfer occur.
To ensure the correct communication, RST must
remain LOW under all conditions except when running
a "Response to Reset sequence".
Data is transferred in 8-bit segments, with each trans-
fer being followed by an ACK, generated by the receiv-
ing device.
If the X76F640 is in a nonvolatile write cycle a "no
ACK" (SDA=High) response will be issued in response
to loading of the command byte. If a stop is issued prior
to the nonvolatile write cycle the write operation will be
terminated and the part will reset and enter into a
standby mode.
The basic sequence is illustrated in Figure 1.
PIN NAMES
PIN CONFIGURATION
After each transaction is completed, the X76F640 will
reset and enter into a standby mode. This will also be
the response if an unsuccessful attempt is made to
access a protected array.
Symbol
Description
CS
Chip Select Input
SDA
Serial Data Input/Output
SCL
Serial Clock Input
RST
Reset Input
Vcc
Supply Voltage
Vss
Ground
NC
No Connect
CS
SDA
V
CC
RST
SCL
NC
1
2
3
4
7
8
6
5
SOIC
V
CC
RST
SCL
V
SS
NC
SDA
Smart Card
CS
NC
NC
GND
X76F640
Characteristics subject to change without notice.
3 of 16
Figure 1. X76F640 Device Operation
Retry Counter
The X76F640 contains a retry counter. The retry
counter allows 8 accesses with an invalid password
before any action is taken. The counter will increment
with any combination of incorrect passwords. If the
retry counter overflows, all memory areas are cleared
and the device is locked by preventing any read or
write array password matches. The passwords are
unaffected. If a correct password is received prior to
retry counter overflow, the retry counter is reset and
access is granted. In order to reset the operation of a
locked up device, a special reset command must be
used with a RESET password.
Device Protocol
The X76F640 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as a receiver. The device controlling the transfer
is a master and the device being controlled is the
slave. The master will always initiate data transfers and
provide the clock for both transmit and receive opera-
tions. Therefore, the X76F640 will be considered a
slave in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW. SDA changes during SCL HIGH are
reserved for indicating start and stop conditions. Refer
to Figure 2 and Figure 3.
Start Condition
All commands are preceeded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The X76F640 continuously monitors the SDA
and SCL lines for the start condition and will not
respond to any command until this condition is met.
A start may be issued to terminate the input of a con-
trol byte or the input data to be written. This will reset
the device and leave it ready to begin a new read or
write command. Because of the push/pull output, a
start cannot be generated while the part is outputting
data. Starts are inhibited while a write is in progress.
Stop Condition
All communications must be terminated by a stop con-
dition. The stop condition is a LOW to HIGH transition
of SDA when SCL is HIGH. The stop condition is also
used to reset the device during a command or data
input sequence and will leave the device in the standby
power mode. As with starts, stops are inhibited when
outputting data and while a write is in progress.
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting
eight bits. During the ninth clock cycle the receiver will
pull the SDA line LOW to acknowledge that it received
the eight bits of data.
The X76F640 will respond with an acknowledge after
recognition of a start condition and its slave address. If
both the device and a write condition have been
selected, the X76F640 will respond with an acknowl-
edge after the receipt of each subsequent eight-bit
word.
Reset Device Command
The reset device command is used to clear the retry
counter and reactivate the device. When the reset
device command is used prior to the retry counter over-
flow, the retry counter is reset and no arrays or pass-
words are affected. If the retry counter has overflowed,
all memory areas are cleared and all commands are
Load Command Byte
Load 2 Byte Address
Load 8-Byte
Password
Verify Password
Acceptance by
Use of Password ACK Polling
Read/Write
Data Bytes
TWC or Data Ack Polling
X76F640
Characteristics subject to change without notice.
4 of 16
blocked and the retry counter is disabled. Issuing a valid
reset device command (with reset password) to the
device resets and re-enables the retry counter and re-
enables the other commands. Again, the passwords are
not affected.
Reset Password Command
A reset password command will clear both arrays and
set all passwords to all zero.
Figure 2. Data Validity
Figure 3. Definition of Start and Stop Conditions
Table 1. X76F640 Instruction Set
Notes:
Illegal command codes will be disregarded. The part will respond with a "no-ACK" to the illegal byte and then return to the standby
mode. All write/read operations require a password.
1st Byte after
Start
1st Byte after
Password
2nd Byte after
Password
Command Description
Password
Used
1000 0000
High Address
Low address
Read (Array 0)
Read 0
1000 1000
High Address
Low address
Read (Array 1)
Read 1
1001 0000
High Address
Low address
Sector Write (Array 0)
Write 0
1001 1000
High Address
Low address
Sector Write (Array 1)
Write 1
1010 0000
0000 0000
0000 0000
Change Read 0 Password
Read 0
1010 1000
0000 0000
0000 0000
Change Read 1 Password
Read 1
1011 0000
0000 0000
0000 0000
Change Write 0 Password
Write 0
1011 1000
0000 0000
0000 0000
Change Write 1 Password
Write 1
1100 0000
0000 0000
0000 0000
Change Reset Password
Reset
1110 0000
not used
not used
Reset Password Command
Reset
1110 1000
not used
not used
Reset Device Command
Reset
1111 0000
not used
not used
ACK Polling command (Ends Password operation)
None
All the rest
Reserved
SCL
SDA
Data Stable
Data
Change
SCL
SDA
Start Condition
Stop Condition
X76F640
Characteristics subject to change without notice.
5 of 16
PROGRAM OPERATIONS
Sector Programming
The sector program mode requires issuing the 8-bit
write command followed by the password, password
Ack command, the address and then the data bytes
transferred as illustrated in figure 4. Up to 32 bytes
may be transferred. After the last byte to be transferred
is acknowledged a stop condition is issued which
starts the nonvolatile write cycle.
Figure 4. Sector Programming
Data 31
A
CK
A
CK
S
Star
t
Command
A
CK
A
CK
A
CK
A
CK
A
CK
A
CK
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Write
Password
7
Write
Password
0
A
CK
Data 0
S
SDA
Wait t
WC
Data ACK Polling
Wait t
WC
OR
Stop
ACK Polling
A
CK
S
ACK Polling
Repeated
Command
Command
NA
CK
If ACK, then
Password Matches
Star
t
X76F640
Characteristics subject to change without notice.
6 of 16
ACK Polling
Once a stop condition is issued to indicate the end of
the host's write sequence, the X76F640 initiates the
internal nonvolatile write cycle. In order to take advan-
tage of the typical 5ms write cycle, ACK polling can
begin immediately. This involves issuing the start con-
dition followed by the new command code of 8 bits (1st
byte of the protocol.) If the X76F640 is still busy with
the nonvolatile write operation, it will issue a "no-ACK"
in response. If the nonvolatile write operation has com-
pleted, an "ACK" will be returned and the host can then
proceed with the rest of the protocol.
Data ACK Polling Sequence
After the password sequence, there is always a nonvol-
atile write cycle. This is done to discourage random
guesses of the password if the device is being tampered
with. In order to continue the transaction, the X76F640
requires the master to perform an ACK polling with the
specific code of F0h. As with regular Acknowledge
polling the user can either time out for 10ms, and then
issue the ACK polling once, or continuously loop as
described in the flow.
Password ACK Polling Sequence
If the password that was inserted was correct, then an
"ACK" will be returned once the nonvolatile cycle is
over, in response to the ACK polling cycle immediately
following it.
If the password that was inserted was incorrect, then a
"no ACK" will be returned even if the nonvolatile cycle
is over. Therefore, the user cannot be certain that the
password is incorrect until the 10ms write cycle time
has elapsed.
ACK
returned?
Issue New
Command code
Write Sequence Completed
Enter ACK Polling
Issue START
NO
YES
PROCEED
ACK
returned?
Issue Password
ACK Command
Password Load Completed
Enter ACK Polling
Issue START
NO
YES
PROCEED
Figure 5. Acknowledge Polling
8th Clk
of 8th
Pwd. Byte
`ACK'
Clk
8th
Clk
`ACK'
Clk
`ACK'
START
Condition
8th Bit
ACK or
no ACK
SCL
SDA
X76F640
Characteristics subject to change without notice.
7 of 16
READ OPERATIONS
Read operations are initiated in the same manner as
write operations but with a different command code.
Random Read
The master issues the start condition and a Read
instruction and password, performs a Password Ack
Polling, then issues the word address. Once the pass-
word has been acknowledged and first byte has been
read, another start can be issued followed by a new 8-
bit address. Random reads are allowed, but only the
low order 8 bits can change. This limits random reads
to a 256 byte block. Therefore, with a single password
cycle only a 256 byte block of array 0 may be accessed
randomly. To randomly access another block of array 0,
a stop must be issued followed by a new command/
address/password sequence. A random read of the
array 1 can access all locations without another pass-
word command sequence.
Sequential Read
The host can read sequentially within an array after the
password acceptance sequence. The data output is
sequential, with the data from address n followed by
the data from n+1. The address counter for read opera-
tions increments all address bits, allowing the entire
memory array contents to be serially read during one
operation. At the end of the address space (address
1FFFh for array 0, 1Fh for array 1), the counter "rolls
over" to address 0 and the X76F640 continues to out-
put data for each acknowledge received. Refer to fig-
ure 7 for the address, acknowledge and data transfer
sequence. An acknowledge must follow each 8-bit data
transfer. After the last bit has been read, a stop condi-
tion is generated without a preceding acknowledge.
Figure 6. Random Read
S
A
CK
Stop
A7 A6 A5 A4 A3 A2 A1 A0
Data Y
S
Star
t
Star
t
Command
A
CK
A
CK
A
CK
A
CK
Read
Password
7
Read
Password
0
S
SDA
A
CK
A
CK
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Data X
Wait t
WC
OR
Star
t
ACK Polling
A
CK
S
ACK Polling
Repeated
Command
Command
NA
CK
If ACK, then
Password Matches
X76F640
Characteristics subject to change without notice.
8 of 16
Figure 7. Sequential Read
Data X
A
CK
S
Star
t
Command
A
CK
A
CK
A
CK
A
CK
Read
Password
7
Read
Password
0
S
SDA
A
CK
A
CK
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
A
CK
Data 0
If ACK, then
Wait t
WC
OR
Star
t
ACK Polling
A
CK
S
ACK Polling
Repeated
Command
Command
NA
CK
Password Matches
Stop
PASSWORDS
The sequence in Figure 8 shows how to change (pro-
gram) the passwords. The programming of passwords
is done twice prior to the nonvolatile write cycle in
order to verify that the new password is consistent.
After the eight bytes are entered in the second pass, a
comparison takes place. A mismatch will cause the
part to reset and enter into the standby mode.
Data ACK polling can be used to determine if a pass-
word has been loaded correctly, however the data ACK
command must be issued less than 2ms after the stop
bit. After this time, it cannot be determined if the pass-
word has been loaded correctly, without trying the new
password. To determine if the new password has been
loaded correctly the data ACK polling command is
issued immediately following the stop bit. If it returns
an ACK, then the two passes of the new password
entry do not match. If it returns a "no ACK" then the
passwords match and a high voltage cycle is in
progress. The high voltage cycle is complete when a
subsequent data ACK command returns an "ACK".
There is no way to read any of the passwords.
Figure 8. Change Passwords
Star
t
Command
A
CK
A
CK
A
CK
A
CK
Old
Password
7
Old
Password
0
S
SDA
A
CK
A
CK
A
CK
New
Password
7
Password
0
A
CK
A
CK
A
CK
New
Password
7
New
Password
0
A
CK
S
Stop
If ACK, then
A
CK
Two Bytes of "0"
Wait t
WC
OR
Star
t
ACK Polling
A
CK
S
ACK Polling
Repeated
Command
Command
NA
CK
Password Matches
If immediate ACK,
then New Password error
Data ACK
Polling
If immediate NACK,
then New Password OK
followed by ACK after ~5ms
X76F640
Characteristics subject to change without notice.
9 of 16
Figure 9. Reset Password
Figure 10. Reset Device
Star
t
Reset Password
A
CK
A
CK
A
CK
A
CK
Reset
Password
7
Reset
Password
0
S
SDA
Wait t
WC
OR
Star
t
ACK Polling
A
CK
S
ACK Polling
Repeated
Command
Command
NA
CK
Stop
S
If ACK, then
Device reset
Command
Star
t
Reset Device
A
CK
A
CK
A
CK
A
CK
Reset
Password
7
Reset
Password
0
S
SDA
Wait t
WC
OR
Star
t
ACK Polling
A
CK
S
ACK Polling
Repeated
Command
Command
NA
CK
Stop
S
If ACK, then
Device Reset
Command
RESPONSE TO RESET (DEFAULT =19 64 AA 55)
The ISO Response to reset is controlled by the RST,
CS and CLK pins. When RST is pulsed high, while CS
is low, the device will output 32 bits of data, one bit per
clock. This conforms to the ISO standard for "synchro-
nous response to reset". CS must remain LOW and the
part must not be in a write cycle for the response to
reset to occur.
After initiating a nonvolatile write cycle is complete. If
not, the ISO response will not be activated. Also, any
attempt to pulse the RST pin in the middle of an ISO
transaction will stop the transaction with the SDA pin in
high impedance. The user will have to issue a stop
condition and start the transaction again. If at any time
during the Response to Reset CS goes HGIH, the
response to reset will be aborted and the part will
return to the standby state. A Response to Reset is not
available during a nonvolatile write cycle.
Continued clocks after the 32 bits, will output the 32 bit
sequence again, starting at byte 0.
Figure 11. Response to RESET(RST)
CS
SCK
SO
0 1
1 0 1 0 1 0 1 0
1 0 0 1 1 0 0 0
0 0 1 0 0 1 1 0
0 1 0 1 0 1
RST
LSB
MSB LSB
MSB LSB
MSB LSB
MSB
Byte
0
1
2
3
X76F640
Characteristics subject to change without notice.
10 of 16
ABSOLUTE MAXIMUM RATINGS
Temperature under bias ................... 65C to +135C
Storage temperature ........................65C to +150C
Voltage on any pin with
respect to V
SS
....................................... 1V to +7V
D.C. output current ............................................... 5mA
Lead temperature (soldering, 10 seconds).........300C
COMMENT
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating con-
ditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temp
Min.
Max.
Commercial
0C
+70C
Extended
20C
+85C
Supply Voltage
Limits
X76F640
4.5V to 5.5V
X76F640 2.7
2.7V to 3.6V
D.C. OPERATING CHARACTERISTICS
(Over the recommended operating conditions unless otherwise specified.)
CAPACITANCE
T
A
= +25C, F = 1MHZ, V
CC
= 5V
Notes:
(1) Must perform a stop command after a read command prior to measurement
(2) V
IL
min. and V
IH
max. are for reference only and are not tested.
(3) This parameter is periodically sampled and not 100% tested.
Symbol
Parameter
Limits
Units
Test Conditions
Min.
Max.
I
CC1
V
CC
Supply Current
(Read)
1
mA
f
SCL
= V
CC
x 0.1/V
CC
x 0.9 Levels @ 400 KHz,
SDA = Open
RST = CS = V
SS
I
CC2
(3)
V
CC
Supply Current
(Write)
3
mA
f
SCL
= V
CC
x 0.1/V
CC
x 0.9 Levels @ 400 KHz,
SDA = Open
RST = CS = V
SS
I
SB1
(1)
V
CC
Supply Current
(Standby)
50
A
V
IL
= V
CC
x 0.1, V
IH
= V
CC
x 0.9
f
SCL
= 400 KHz, f
SDA
= 400 KHz
I
SB2
(1)
V
CC
Supply Current
(Standby)
1
A
V
SDA
= V
SCC
= V
CC
Other = GND or V
CC
0.3V
I
LI
Input Leakage Current
10
A
V
IN
= V
SS
to V
CC
I
LO
Output Leakage Current
10
A
V
OUT
= V
SS
to V
CC
V
IL1
(2)
Input LOW Voltage
0.5
V
CC
x 0.3
V
V
CC
= 5.5V
V
IH1
(2)
Input HIGH Voltage
V
CC
x 0.7
V
CC
+ 0.5
V
V
CC
= 5.5V
V
IL2
(2)
Input LOW Voltage
0.5
V
CC
x 0.1
V
V
CC
= 3.0V
V
IH2
(2)
Input HIGH Voltage
V
CC
x 0.9
V
CC
+ 0.5
V
V
CC
= 3.0V
V
OL
Output LOW Voltage
0.4
V
I
OL
= 3mA
Symbol
Test
Max.
Units
Conditions
C
OUT
(3)
Output Capacitance (SDA)
8
pF
V
I/O
= 0V
C
IN
(3)
Input Capacitance (RST, SCL, CS)
6
pF
V
IN
= 0V
X76F640
Characteristics subject to change without notice.
11 of 16
EQUIVALENT A.C. LOAD CIRCUIT
A.C. TEST CONDITIONS
3V
1.3K
Output
100pF
5V
1533
Output
100pF
Input pulse levels
V
CC
x 0.1 to V
CC
x 0.9
Input rise and fall times
10ns
Input and output timing level
V
CC
x 0.5
Output load
100pF
AC CHARACTERISTICS
AC Specifications (Over the recommended operating conditions)
Notes: 1.
Typical values are for T
A
= 25C and V
CC
= 5.0V
2.
C
b
= Total Capacitance of one bus line in pf.
Symbol
Parameter
Min.
Typ.
(1)
Max.
Units
f
SCL
SCL Clock Frequency
0
400
KHz
t
IN
(1)
Pulse width of spikes which must be suppressed by the input
filter
50
100
ns
t
AA
SCL LOW to SDA Data Out Valid
0.1
0.3
0.9
s
t
BUF
Time the bus must be free before a new transmit can start
1.3
s
t
LOW
Clock LOW Time
1.3
s
t
HIGH
Clock HIGH Time
0.6
s
t
SU:STA
Start Condition Setup Time
0.6
s
t
HD:STA
Start Condition Hold Time
0.6
s
t
SU:DAT
Data In Setup Time
100
ns
t
HD:DAT
Data In Hold Time
0
s
t
SU:STO
Stop Condition Setup Time
0.6
s
t
DH
Data Output Hold Time
50
300
ns
t
R
SDA and SCL Rise Time
20 + 0.1 x C
b
(2)
300
ns
t
F
SDA and SCL Fall Time
20 + 0.1 x C
b
(2)
300
ns
t
SU:CS
CS Setup Time
200
ns
t
HD:CS
CS Hold Time
100
ns
f
SCL_RST
SCL Clock Frequency during Response to Reset
400
kHz
t
SR
Device Select to RST active
200
ns
t
NOL
RST to SCL Non-Overlap
500
ns
t
RST
RST High Time
2.25
s
t
SU:RST
Response to Reset Setup Time
1.25
s
t
LOW_RST
Clock LOW during Response to Reset
1.25
s
t
HIGH_RST
Clock HIGH during Response to Reset
1.25
s
t
RDV
RST LOW to SDA Valid During Response to Reset
0
500
ns
t
CDV
CLK LOW to SDA Valid During Response to Reset
0
500
ns
t
DHZ
Device Deselect to SDA high impedance
0
500
ns
X76F640
Characteristics subject to change without notice.
12 of 16
RESET AC SPECIFICATIONS
Power Up Timing
Notes: (1) Delays are measured from the time V
CC
is stable until the specified operation can be initiated. These parameters are periodically
sampled and not 100% tested.
(2) Typical values are for T
A
= 25C and V
CC
= 5.0V
Nonvolatile Write Cycle Timing
Notes: 1.
t
WC
is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle.
*It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
TIMING DIAGRAMS
Bus Timing
Write Cycle Timing
Symbol
Parameter
Min.
Typ
(2)
Max.
Units
t
PUR
(1)
Time from Power Up to Read
1
mS
t
PUW
(1)
Time from Power Up to Write
5
mS
Symbol
Parameter
Min.
Typ.
(1)
Max.
Units
t
WC
(1)
Write Cycle Time
5
10
mS
t
SU:STO
t
DH
t
HIGH
t
SU:ST
t
HD:STA
t
HD:DAT
t
SU:DAT
SCL
SDA IN
SDA OUT
t
F
t
LOW
t
BUF
t
AA
t
R
SCL
SDA
t
WC
8th Bit of Last Byte
ACK
Stop
Condition
Start
Condition
X76F640
Characteristics subject to change without notice.
13 of 16
CS Timing Diagram (Selecting/Deselecting the Part)
RST Timing Diagram Response to a Synchronous Reset
GUIDELINES FOR CALCULATING TYPICAL VALUES OF BUS PULL UP RESISTORS
t
SU:CS
t
HD:CS
SCL
CS from
Master
t
RST
t
NOL
t
HIGH_RST
t
LOW_RST
t
CDV
t
RDV
t
SU:RST
Data Bit (1)
Data Bit (2)
1st
CLK
Pulse
2nd
CLK
Pulse
3rd
clk
pulse
CS
I/O
CLK
RST
t
NOL
t
SR
Data Bit (N)
Data Bit (N+1)
CS
I/O
CLK
RST
t
DHZ
(N+2)
100
80
60
40
20
Bus capacitance in pF
Pull Up Resistance in K
R
MIN
R
MAX
20
40
60
80
100
R
MIN
V
CCMAX
I
OLMIN
--------------------------
1.8
K
=
=
R
MAX
t
R
C
BUS
------------------
=
t
R
= maximum allowable SDA rise time
X76F640
Characteristics subject to change without notice.
14 of 16
PACKAGING INFORMATION
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
0.020 (.508)
0.012 (.305)
.080 (2.03)
.070 (1.78)
.213 (5.41)
.205 (5.21)
.330 (8.38)
.300 (7.62)
.212 (5.38)
.203 (5.16)
.035 (.889)
.020 (.508)
.010 (.254)
.007 (.178)
08 Ref.
Pin 1 ID
.050 (1.27) BSC
8-Lead Plastic, 0.200" Wide Small Outline
Gullwing Package Typ "A" (EIAJ SOIC)
.013 (.330)
.004 (.102)
NOTES:
X76F640
Characteristics subject to change without notice.
15 of 16
PACKAGING INFORMATION
8 Pad Chip on Board Smart Card Module Type X
0.465 0.002
(11.81 0.05)
A
SECTION A-A
A
R. 0.078 (2.00)
0.285 (7.24) Max.
See Note 7 Sht. 2
0.420 0.002
(10.67 0.05)
0.210 0.002
(5.33 0.05)
0.105 0.002
(2.67 0.05) Typ.
(8x)
(8x)
0.105 0.002
(2.67 0.05)
0.008 0.001
(0.20 0.03)
0.233 0.002
(5.92 0.05)
0.174 0.002
(4.42 0.05)
0.146 0.002
(3.71 0.05)
Die
0.0235 (0.60) Max.
0.015 (0.38) Max.
0.008 (0.20) Max.
Glob Size
FR4 Tape
See Detail Sheet 3
Copper, Nickel Plated, Gold Flash
R. 0.013 (0.33) (8x)
0.270 (6.86) Max.
0.069 (1.75) Min Epoxy
Free Area (Typ.)
0.088 (2.24) Min Epoxy
Free Area (Typ.)
NOTE:
1. ALL DIMENSIONS IN INCHES AND (MILLIMETERS)
V
CC
RST
SCL
NC
V
SS
CS
SDA
NC
See Note 7 Sht. 2
X76F640
Characteristics subject to change without notice.
16 of 16
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express,
statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes
no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and
without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691; 5,161,137;
5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and
correction, redundancy and back-up features to prevent such an occurence.
Xicor's products are not authorized for use in critical components in life support devices or systems.
1.
Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2.
A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
Ordering Information
V
CC
Limits
Blank = 5V 10%
2.7 = 2.7V to 3.6V
Temperature Range
Blank = Commercial = 0C to +70C
E = Extended = 20C to +85C
Package
A = 8-Lead SOIC (EIAJ)
H = Die in Waffle Packs
W = Die in Wafer Form
X = Smart Card Module
Y = Smart Card
Device
X76F640
X
X
X
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