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Preliminary Information

256K

X55621

Dual Voltage Monitor with Integrated System Battery Switch and EEPROM

FEATURES

· Dual voltage monitoring
· System battery switch-over circuitry
· Early warning low V

fail indicator

· Separate watchdog timer outputs
· Selectable watchdog timer

--(0.15s, 0.4s, 0.8s, off)

· Low V

(V1MON) and V2MON detection and

reset assertion
--Four standard reset threshold voltages
--Re-program V1

TRIP

and V2

TRIP

reset threshold

voltage using special programming sequence

--Reset signal valid to V

= 1V

· Long battery life with low power consumption

--<50µA max standby current, watchdog on
--<30µA max standby current, watchdog off
--<1.5mA max active current during read

· 256Kbits of EEPROM
· Built-in inadvertent write protection

--Power-up/power-down protection circuitry
--Protect 0, 1/4, 1/2 or all of EEPROM array with

programmable Block Lock

protection

--In circuit programmable ROM mode

· 10MHz SPI interface modes (0,0 & 1,1)
· Minimize EEPROM programming time

--64-byte page write mode
--Self-timed write cycle
--5ms write cycle time (typical)

· 2.7V to 5.5V power supply operation
· Available packages

--20-lead TSSOP

DESCRIPTION

This device combines power-on reset control, battery
switch circuit, watchdog timer, supply voltage supervi-
sion, secondary voltage supervision, block lock

protect

and serial EEPROM in one package. This combination
lowers system cost, reduces board space require-
ments, and increases reliability.

Applying power to the device activates the power on
reset circuit which holds RESET active for a period of
time. This allows the power supply and oscillator to sta-
bilize before the processor can execute code.

A system battery switch circuit compares V

(V1MON)

with V

BATT

input and connects V

OUT

to whichever is

higher. This provides voltage to external SRAM or
other circuits in the event of main power failure. The
X55621 can drive 50mA from V

and 250µA from

BATT

. The device switches to V

BATT

when V

drops

below the low V

voltage threshold and V

BATT

The Watchdog Timer provides an independent
protection mechanism for microcontrollers. When the
micro-controller fails to restart a timer within a select-
able time out interval, the device activates the WDO
signal. The user selects the interval from three preset
values. Once selected, the interval does not change,
even after cycling the power.

The device's low V

detection circuitry protects the

user's system from low voltage conditions, resetting the
system when V

(V1MON) falls below the minimum

trip point (V

TRIP

). RESET is asserted until V

returns to proper operating level and stabilizes. A second
voltage monitor circuit tracks the unregulated supply or
monitors a second power supply voltage to provide a
power fail warning. Xicor's unique circuits allow the
threshold for either voltage monitor to be reprogrammed
to meet special needs or to fine-tune the threshold for
applications requiring higher precision.

X55621 Preliminary Information

Characteristics subject to change without notice.

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PIN CONFIGURATION

PIN DESCRIPTION

Pin

Name

Function

CS/WDI

Chip Select Input.

CS HIGH, deselects the device and the SO output pin is at a high impedance

state. Unless a nonvolatile write cycle is underway, the device will be in the standby power mode.
CS LOW enables the device, placing it in the active power mode. Prior to the start of any opera-
tion after power up, a HIGH to LOW transition on CS is required.

Watchdog Input.

A HIGH to LOW transition on the WDI pin restarts the Watchdog timer. The

absence of a HIGH to LOW transition within the watchdog time out period results in RESET going
active.

No internal connections

Serial Output.

SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The

falling edge of the serial clock (SCK) clocks the data out.

WDO

Watchdog Output

WDO

is an active Low, open drain output which goes active whenever the

watchdog timer goes active.

LOWLINE

Early Low V

Detect

This CMOS output signal goes LOW when V

< V1

TRIP

and returns

HIGH when V

> V1

TRIP

. This pin goes LOW 250ns before RESET pin.

V2FAIL

V2 Voltage Fail Output.

This open drain output goes LOW when V2MON is less than V2

TRIP

and goes HIGH when V2MON exceeds V2

TRIP

. There is no power up reset delay circuitry on this

pin. This circuit works independently from the Low V

reset and battery switch circuits.

V2MON

V2 Voltage Monitor Input.

When the V2MON input is less than the V2

TRIP

voltage, V2FAIL goes

LOW. This input can monitor an unregulated power supply with an external resistor divider or can
monitor a second power supply with no external components. Connect V2MON to V

or V

when not used.

Write Protect.

The WP pin works in conjunction with a nonvolatile WPEN bit to "lock" the setting

of the Watchdog Timer control and the memory write protect bits. This pin is also used as the test
mode enable pin where the high voltage will be applied. Thus the layout for the input is different
to allow for higher punch thru.

No internal connections

Ground

20-Pin TSSOP

CS/WDI

RESET/MR

(V1MON)

BATT-ON

OUT

WDO

LOWLINE

V2FAIL

V2MON

VSS

BATT

SCK

X55621 Preliminary Information

Characteristics subject to change without notice.

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Serial Input.

SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on

this pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1),
addresses and data MSB first.

No internal connections

SCK

Serial Clock.

The Serial Clock controls the serial bus timing for data input and output. The rising

edge of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of
SCK changes the data output on the SO pin.

BATT

Battery Supply Voltage.

This input provides a backup supply in the event of a failure of the pri-

mary V

voltage. The V

BATT

voltage typically provides the supply voltage necessary to main-

tain the contents of SRAM and also powers the internal logic to "stay awake."

OUT

Output Voltage.

OUT

= V

if V

> V1

TRIP

. IF V

< V1

TRIP

, then V

OUT

= V

if V

BATT

+ 0.03, or V

OUT

= V

BATT

if V

< V

BATT

0.03.

Note:

There is hysteresis around V

BATT

± 0.03V point to avoid oscillation at or near the switcho-

ver voltage. A capacitance of 0.1µF must be connected to Vout to ensure stability.

BATT-ON

Battery On.

This CMOS output goes HIGH when the V

OUT

switches to V

BATT

and goes LOW

when V

OUT

switches to V

. It is used to drive an external PNP pass transistor when V

= V

OUT

and current requirements are greater than 50mA.
The purpose of this output is to drive an external transistor to get higher operating currents when
the V

supply is fully functional. In the event of a V

failure, the battery voltage is applied to

the V

OUT

pin and the external transistor is turned off. In this "backup condition," the battery only

needs to supply enough voltage and current to keep SRAM devices from losing their data-there
is no communication at this time.

RESET

/MR

RESET Output

This is an active LOW, open drain output which goes active whenever V

falls

below the minimum V

sense level. Then communication to the device is interrupted. It will remain

active until V

rises above the minimum V

sense level for 150ms. RESET also goes active on

power up and remains active for 150ms after the power supply stabilizes.

No internal connections

(V1MON)

Supply Voltage

V1 Voltage Monitor Input.

When the V1MON input is less than the V1

TRIP

voltage, RESET and

RESET goes ACTIVE.

PIN DESCRIPTION (CONTINUED)

Pin

Name

Function

X55621 Preliminary Information

Characteristics subject to change without notice.

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PRINCIPLES OF OPERATION

Power On Reset

Application of power to the X55621 activates a Power
On Reset Circuit. This circuit goes active at about 1V
and pulls the RESET pin active. This signal prevents the
system microprocessor from starting to operate with
insufficient voltage or prior to stabilization of the oscilla-
tor. When Vcc exceeds the device V1

TRIP

value for

150ms (nominal) the circuit releases RESET, allowing
the processor to begin executing code.

Low V

(V1MON) Voltage Monitoring

During operation, the X55621 monitors the V

level

and asserts RESET if supply voltage falls below a preset
minimum V1

TRIP

. During this time the communication

to the device is interrupted. The RESET signal also pre-
vents the microprocessor from operating in a power fail
or brownout condition. The RESET signal remains

active until the voltage drops below 1V. These also
remain active until V

returns and exceeds V1

TRIP

for

150ms.

Low V2MON Voltage Monitoring

The X55621 also monitors a second voltage level and
asserts V2FAIL if the voltage falls below a preset mini-
mum V2

TRIP

. The V2FAIL signal is either ORed with

RESET to prevent the microprocessor from operating
in a power fail or brownout condition or used to inter-
rupt the microprocessor with notification of an impend-
ing power failure. The V2FAIL signal remains active
until the V2MON drops below 1V (V2MON falling). It
also remains active until V2MON returns and exceeds
V2

TRIP

by 0.03V.

The V2MON voltage sensor is completely separate
from the operation of the low V

sense, and is inde-

pendent of V

supply.

Figure 1. Two Uses of Dual Voltage Monitoring

X55621

OUT

Reg

RESET

V2MON

V2FAIL

System
Reset

Unregulated

Supply

System
Reset

System
Interrupt

Unregulated

Supply

Resistors selected so 3V appears on V2MON when
Unregulated supply reaches 6V.

Notice: No external components required to monitor
two voltages.

V2MON

Watchdog Timer

The Watchdog Timer circuit monitors the microproces-
sor activity by monitoring the CS pin. The microproces-
sor must toggle the CS pin HIGH to LOW periodically
prior to the expiration of the watchdog time out period
to prevent the WDO signal going active. The state of
two nonvolatile control bits in the Status Register
determines the watchdog timer period. The micropro-
cessor can change these watchdog bits by writing to
the status register.

The Watchdog Timer oscillator stops when in battery
backup mode. It re-starts when V

returns.

System Battery Switch

As long as V

exceeds the low voltage detect thresh-

old V1

TRIP

, V

OUT

is connected to V

through a 5 Ohm

(typical) switch. When the V

has fallen below V

TRIP

then V

is applied to V

OUT

if V

is or equal to or

greater than V

BATT

0.03V. When V

drops to less

than V

BATT

0.03V, then V

OUT

is connected to V

BATT

through an 80 Ohm (typical) switch. V

OUT

typically

supplies the system static RAM voltage, so the
switchover circuit operates to protect the contents of
the static RAM during a power failure. Typically, when
V

has failed, the SRAMs go into a lower power state

and draw much less current than in their active mode.
When V

returns, V

OUT

switches back to V

when

exceeds V

BATT

+ 0.03V. There is a 60mV hystere-

sis around this battery switch threshold to prevent
oscillations between supplies.

While V

is connected to V

OUT

the BATT-ON pin is

pulled LOW. The signal can drive an external PNP
transistor to provide additional current to the external
circuits during normal operation.

X55621 Preliminary Information

Characteristics subject to change without notice.

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(V1MON), V2MON Threshold Reset Procedure

The X55621 is shipped with standard V

(V1MON) and

V2MON threshold (V1

TRIP

, V2

TRIP

) voltages. These val-

ues will not change over normal operating and storage
conditions. However, in applications where the standard
thresholds are not exactly right, or if higher precision is
needed in the threshold value, the X55621 trip points may
be adjusted. The procedure is described below, and uses
the application of a high voltage control signal.

Setting the V

TRIP

Voltage

This procedure is used to set the V1

TRIP

or V2

TRIP

to a

lower or higher voltage value. It is necessary to reset
the trip point before setting the new value.

To set the new voltage, apply the desired V

TRIP

thresh-

old voltage to the V

pin or the V2

TRIP

voltage to the

V2MON pin (during V2MON V2

TRIP

setting only, V

should be same as V2MON), then tie the WP pin to the

programming voltage V

. Then, send the WREN com-

mand and write to address 01h or to address 0Bh to
program V

TRIP

or V2

TRIP

, respectively (followed by

data byte 00h). The CS going high after a valid write
operation initiates the programming sequence. Bring
WP LOW to complete the operation.

Note: This operation will not alter the contents of the
EEPROM.

Manual Reset

By connecting a push-button from MR to ground or
driven by logic, the designer adds manual system reset
capability. The RESET pins are asserted when the
push-button is closed and remain asserted for t

PURST

after the push-button is released. This pin is debounced
so a push-button connected directly to the device will
have both clean falling and rising edges on MR. Also
has internal pull up thus the pin can left open if not used.

Figure 2. Example System Connection

Reg

Unregulated

Supply

Address

Decode

Enable

SRAM

Addr

OUT

NMI

RESET

SPI µC

BATT

V2MON

RESET

LOWLINE

BATT-ON

OUT

V2FAIL

RESET

CS, SCK

SI, SO

V2MON

Resetting the V

TRIP

Voltage

This procedure is used to set the V1

TRIP

or the V2

TRIP

to a "native" voltage level. For example, if the current
V

TRIP

is 4.4V and the new V

TRIP

must be 4.0V, then

the V

TRIP

must be reset. When the threshold is reset,

the new level is something less than 1.7V. This proce-
dure must be used to set the voltage to a lower value.

To reset the new V1

TRIP

or V2

TRIP

voltage, apply

greater than 3V to V

(V1MON) or V2MON pin,

respectively, and tie the WP pin to the programming

voltage V

. Then send the WREN command and write

to address 03h or 0Dh to reset the V1

TRIP

or V2

TRIP

respectively (followed by data byte 00h). The CS going
LOW to HIGH after a valid write operation initiates the
programming sequence. Bring WP LOW to complete
the operation.

Note: This operation does not change the contents of
the EEPROM array.

X55621 Preliminary Information

Characteristics subject to change without notice.

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Figure 3. Set V

TRIP

Level Sequence (V

= desired V

TRIP

)

Figure 4. Reset V

TRIP

Level Sequence (V

> 3V. WP = 10-15V)

Figure 5. Sample V

TRIP

Reset Circuit

0 1 2 3 4 5 6 7

0 1

2 3 4 5 6

SCK

16 Bits

8 9 10

20 21 22 23

= 10-15V

06h

WREN

02h

WRITE

00h

DATA

0001h/000Bh

ADDRESS

Addr 01h: Set V

(V1

TRIP

)

Addr 0Bh: Set V2MON trip

0 1 2 3 4 5 6 7

0 1

2 3 4 5 6

SCK

16 Bits

8 9 10

20 21 22 23

= 10-15V

06h

WREN

02h

WRITE

00h

DATA

0003h/000Dh

ADDRESS

Addr 03h: Update V

(V1

TRIP

)

Addr 0Dh: Update V2MON trip

Adjust

Run

TRIP

Adj.

SO
WP

RESET

SCK

X55621

4.6K

RESET

SCK

µC

X55621 Preliminary Information

Characteristics subject to change without notice.

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SPI SERIAL MEMORY

The memory portion of the device is a CMOS Serial
EEPROM array with Xicor's block lock protection. The
array is internally organized as x 8. The device features
a Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple four-wire bus.

The device utilizes Xicor's proprietary Direct Write

cell, providing a minimum endurance of 1,000,000
cycles and a minimum data retention of 100 years.

The device is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular microcontroller families. It contains an 8-bit
instruction register that is accessed via the SI input,
with data being clocked in on the rising edge of SCK.
CS must be LOW during the entire operation.

All instructions (Table 1), addresses and data are
transferred MSB first. Data input on the SI line is
latched on the first rising edge of SCK after CS goes
LOW. Data is output on the SO line by the falling edge
of SCK. SCK is static, allowing the user to stop the
clock and then start it again to resume operations
where left off.

Write Enable Latch

The device contains a Write Enable Latch. This latch
must be SET before a Write Operation is initiated. The
WREN instruction will set the latch and the WRDI
instruction will reset the latch (Figure 3). This latch is
automatically reset upon a power-up condition and
after the completion of a valid Write Cycle.

Status Register

The RDSR instruction provides access to the Status
Register. The Status Register may be read at any time,
even during a Write Cycle. The Status Register is for-
matted as follows:

The Write-In-Progress (WIP) bit is a volatile, read only
bit and indicates whether the device is busy with an
internal nonvolatile write operation. The WIP bit is read
using the RDSR instruction. When set to a "1", a non-
volatile write operation is in progress. When set to a
"0", no write is in progress.

WPEN

WD1

WD0

BL2

BL1

BL0

WEL

WIP

Table 1. Instruction Set

Notes: *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.

Table 2. Block Protect Matrix

Instruction Name

Instruction Format*

Operation

WREN

0000 0110

Set the Write Enable Latch (Enable Write Operations)

WRDI

0000 0100

Reset the Write Enable Latch

RSDR

0000 0101

Read Status Register

WRSR

0000 0001

Write Status Register (Watchdog, Block Lock, WPEN)

READ

0000 0011

Read Data from Memory Array Beginning at Selected Address

WRITE

0000 0010

Write Data to Memory Array Beginning at Selected Address

WREN CMD

Status Register

Device Pin

Block

Status Register

WEL

WPEN

WP#

Protected Block Unprotected Block

WPEN, BL0, BL1,

BL2, WD0, WD1

Protected

Writable

Protected

Writable

Protected

Writable

X55621 Preliminary Information

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The Write Enable Latch (WEL) bit indicates the Status
of the Write Enable Latch. When WEL = 1, the latch is
set HIGH and when WEL = 0 the latch is reset LOW.
The WEL bit is a volatile, read only bit. It can be set by
the WREN instruction and can be reset by the WRDS
instruction.

The block lock bits, BL0, BL1 and BL2, set the level of
block lock protection. These nonvolatile bits are pro-
grammed using the WRSR instruction and allow the
user to protect one quarter, one half, all or none of the
EEPROM array. Any portion of the array that is block
lock Protected can be read but not written. It will
remain protected until the BL bits are altered to disable
block lock protection of that portion of memory.

The Watchdog Timer bits, WD0 and WD1, select the
Watchdog Time-out Period. These nonvolatile bits are
programmed with the WRSR instruction.

The nonvolatile WPEN bit is programmed using the
WRSR instruction. This bit works in conjunction with
the WP pin to provide an In-Circuit Programmable
ROM function (Table 2). WP is LOW and WPEN bit pro-
grammed HIGH disables all Status Register Write
Operations.

In Circuit Programmable ROM Mode

This mechanism protects the block lock and Watchdog
bits from inadvertent corruption.

In the locked state (

Programmable ROM Mode) the WP

pin is LOW and the nonvolatile bit WPEN is "1". This
mode disables nonvolatile writes to the device's Status
Register.

Setting the WP pin LOW while WPEN is a "1" while an
internal write cycle to the Status Register is in progress
will not stop this write operation, but the operation dis-
ables subsequent write attempts to the Status Register.

Status Register Bits Array Addresses Protected

BL2

BL1

BL0

X55621

None

6000h7FFFh

4000h7FFFh

0000h7FFFh

0000h003Fh

0000h007Fh

0000h00FFh

0000h01FFh

Status Register Bits

Watchdog Time Out

(Typical)

WD1

WD0

800 milliseconds

400 milliseconds

150 milliseconds

disabled

Figure 7. Read EEPROM Array Sequence

20 21 22 23 24 25

26 27 28 29 30

Data Out

SCK

MSB

High Impedance

Instruction

16 Bit Address

15 14 13

X55621 Preliminary Information

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When WP is HIGH, all functions, including nonvolatile
writes to the Status Register operate normally. Setting
the WPEN bit in the Status Register to "0" blocks the
WP pin function, allowing writes to the Status Register
when WP is HIGH or LOW. Setting the WPEN bit to "1"
while the WP pin is LOW activates the Programmable
ROM mode, thus requiring a change in the WP pin
prior to subsequent Status Register changes. This
allows manufacturing to install the device in a system
with WP pin grounded and still be able to program the
Status Register. Manufacturing can then load Configu-
ration data, manufacturing time and other parameters
into the EEPROM, then set the portion of memory to
be protected by setting the block lock bits, and finally
set the "OTP mode" by setting the WPEN bit. Data
changes now require a hardware change.

Read Sequence

When reading from the EEPROM memory array, CS is
first pulled low to select the device. The 8-bit READ
instruction is transmitted to the device, followed by the
16-bit address. After the READ opcode and address
are sent, the data stored in the memory at the selected
address is shifted out on the SO line. The data stored
in memory at the next address can be read sequen-
tially by continuing to provide clock pulses. The
address is automatically incremented to the next
higher address after each byte of data is shifted out.
When the highest address is reached, the address
counter rolls over to address $0000 allowing the read
cycle to be continued indefinitely. The read operation is
terminated by taking CS high. Refer to the Read
EEPROM Array Sequence (Figure 1).

To read the Status Register, the CS line is first pulled
low to select the device followed by the 8-bit RDSR
instruction. After the RDSR opcode is sent, the contents
of the Status Register are shifted out on the SO line.
Refer to the Read Status Register Sequence (Figure 2).

Write Sequence

Prior to any attempt to write data into the device, the
"Write Enable" Latch (WEL) must first be set by issuing
the WREN instruction (Figure 3). CS is first taken LOW,
then the WREN instruction is clocked into the device.
After all eight bits of the instruction are transmitted, CS
must then be taken HIGH. If the user continues the
Write Operation without taking CS HIGH after issuing
the WREN instruction, the Write Operation will be
ignored.

To write data to the EEPROM memory array, the user
then issues the WRITE instruction followed by the 16
bit address and then the data to be written. Any
unused address bits are specified to be "0's". The
WRITE operation minimally takes 32 clocks. CS must
go low and remain low for the duration of the operation.
If the address counter reaches the end of a page and
the clock continues, the counter will roll back to the first
address of the page and overwrite any data that may
have been previously written.

For the Page Write Operation (byte or page write) to be
completed, CS can only be brought HIGH after bit 0 of
the last data byte to be written is clocked in. If it is
brought HIGH at any other time, the write operation will
not be completed (Figure 4).

To write to the Status Register, the WRSR instruction is
followed by the data to be written (Figure 5). Data bits
0 and 1 must be "0".

While the write is in progress following a Status Regis-
ter or EEPROM Sequence, the Status Register may be
read to check the WIP bit. During this time the WIP bit
will be high.

OPERATIONAL NOTES

The device powers-up in the following state:

The device is in the low power standby state.

A HIGH to LOW transition on CS is required to enter

an active state and receive an instruction.

SO pin is high impedance.

The Write Enable Latch is reset.

Reset Signal is active for t

PURST

Data Protection

The following circuitry has been included to prevent
inadvertent writes:

A WREN instruction must be issued to set the Write

Enable Latch.

CS must come HIGH at the proper clock count in

order to start a nonvolatile write cycle.

X55621 Preliminary Information

Characteristics subject to change without notice.

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Figure 10. Write Sequence

Figure 11. Status Register Write Sequence

SYMBOL TABLE

32 33 34 35 36 37 38 39

SCK

Instruction

16 Bit Address

Data Byte 1

40 41 42 43 44 45 46 47

Data Byte 2

Data Byte 3

Data Byte N

15 14 13

20 21 22 23 24 25 26 27 28 29 30 31

SCK

High Impedance

Instruction

Data Byte

11 12 13 14 15

WAVEFORM

INPUTS

OUTPUTS

Must be
steady

Will be
steady

May change
from LOW
to HIGH

Will change
from LOW
to HIGH

May change
from HIGH
to LOW

Will change
from HIGH
to LOW

Don't Care:
Changes
Allowed

Changing:
State Not
Known

N/A

Center Line
is High
Impedance

X55621 Preliminary Information

Characteristics subject to change without notice.

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ABSOLUTE MAXIMUM RATINGS

Temperature under bias ...................65°C to +135°C
Storage temperature ........................65°C to +150°C
Voltage on any pin with

respect to V

...................................... 1.0V to +7V

D.C. output current ............................................... 5mA
Lead temperature (soldering, 10 seconds).........300°C

COMMENT

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only; the functional operation of
the device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating con-
ditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

Temperature

Min.

Max.

Commercial

0°C

70°C

Industrial

40°C

+85°C

Device Option

Supply Voltage

-2.7A

2.7V-5.5V

Blank

4.5V-5.5V

D.C. OPERATING CHARACTERISTICS
(Over recommended operating conditions unless otherwise specified.)

Symbol

Parameter

Limits

Unit

Test Conditions

Min.

Typ.

Max.

CC1

(1)

Supply Current (Active)

(Excludes I

OUT

) Read Memory array

(Excludes I

OUT

) Write nonvolatile

Memory

1.5
3.0

SCK = V

x 0.1/V

x 0.9 @ 10MHz,
SO, V

OUT

, RESET,

LOWLINE = Open

CC2

(2)

Supply Current (Passive)

(Excludes I

OUT

) WDT on, 5V

(Excludes I

OUT

) WDT on, 2.7V

(Excludes I

OUT

) WDT off, 5V

50.0
40.0
30.0

90.0
60.0
50.0

µA

CS = V

, V

= V

, V

OUT

= Open

CC3

(1)

Current (Battery Backup Mode)

(Excludes I

OUT

)

µA

= 0V, V

BATT

= 2.8V,

OUT

, RESET,

LOWLINE = Open

BATT1

(3)

BATT

Current (Excludes I

OUT

)

µA

OUT

= V

BATT2

BATT

Current (Excludes I

OUT

)

(Battery Backup Mode)

0.4

1.0

µA

OUT

= V

BATT

= 2.8V,

OUT

, RESET = Open

OUT1

Output Voltage (V

> V

BATT

+ 0.03V

or V

> V

TRIP

0.05

0.5

0.02

0.2

V
V

OUT

= -5mA

OUT

= -50mA

OUT2

Output Voltage (V

< V

BATT

0.03V

and V

< V

TRIP

) {Battery Backup}

BATT

0.2

V
V

OUT

= -250µA

OLB

Output (BATT-ON) LOW Voltage

0.4

= 3.0mA (5V)

= 1.0mA (3V)

OHB

Output (BATT-ON) HIGH Voltage

OUT

0.8

= -0.4mA (3V)

BSH

Battery Switch Hysteresis
(V

< V

TRIP

)

-50

mV
mV

Power Up
Power Down

X55621 Preliminary Information

Characteristics subject to change without notice.

15 of 22

REV 1.0 6/27/00

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Notes: (1) The device enters the Active state after any start, and remains active until 9 clock cycles later if the Device Select Bits in the Slave

Address Byte are incorrect; 200ns after a stop ending a read operation; or t

after a stop ending a write operation.

(2) The device goes into Standby: 200ns after any Stop, except those that initiate a high voltage write cycle; t

after a stop that

initiates a high voltage cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave
Address Byte.

(3) Negative number indicate charging current, Positive numbers indicate discharge current.
(4) V

min. and V

max. are for reference only and are not tested.

CAPACITANCE T

= +25°C, f = 1MHz, V

= 5V

Notes: (1) This parameter is periodically sampled and not 100% tested.

RESET/MR/LOWLINE

ILM

(4)

Input (MR) LOW Voltage

-0.5

x 0.3

IHM

(4)

Input (MR) HIGH Voltage

x 0.7

+ 0.5

TRIP

Reset Trip Point Voltage

4.5

4.62

4.75

LVRH

Low V

RESET Hysteresis

OLR

Output (RESET, WDO, LOWLINE)
LOW Voltage

0.4

= 3.0mA (5V)

= 1.0mA (3V)

OHR

Output (WDO, LOWLINE) HIGH
Voltage

OUT

0.8

= -0.4mA (5V)

Second Supply Monitor

V2MON Current

µA

TRIP

V2MON Reset Trip Point Voltage

2.85

2.95

3.05

V2H

V2MON Hysteresis

OLx

Output (V2FAIL) LOW Voltage

0.4

= 3.0mA (5V)

= 1.0mA (3V)

SPI Interface

ILx

(4)

Input (CS, SI, SCK, WP) LOW Voltage

-0.5

x 0.3

IHx

(4)

Input (CS, SI, SCK, WP) HIGH Voltage

x 0.7

+ 0.5

LIx

Input Leakage Current (CS, SI, SCK,
WP)

±10

µA

OLS

Output (SO) LOW Voltage

0.4

= 3.0mA (5V)

= 1.0mA (3V)

OHS

Output (SO) HIGH Voltage

OUT

0.8

= -1.0mA (5V)

Symbol

Test

Max.

Unit

Conditions

OUT

(1)

Output Capacitance (SO, RESET, V2FAIL, WDO, LOWLINE, BATT-ON)

OUT

= 0V

(1)

Input Capacitance (SCK, SI, CS, WP)

= 0V

D.C. OPERATING CHARACTERISTICS (CONTINUED)
(Over recommended operating conditions unless otherwise specified.)

Symbol

Parameter

Limits

Unit

Test Conditions

Min.

Typ.

Max.

X55621 Preliminary Information

Characteristics subject to change without notice.

16 of 22

REV 1.0 6/27/00

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EQUIVALENT A.C. LOAD CIRCUIT AT 5V V

A.C. TEST CONDITIONS

OUT

30pF

V2MON

1.53K

RESET

30pF

2.06K

3.03K

V2FAIL

OUT

1.53K

30pF

BATT-ON/LOWLINE

Input pulse levels

x 0.1 to V

x 0.9

Input rise and fall times

10ns

Input and output timing level

x0.5

A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)

Serial Input Timing

Symbol Parameter

2.7-5.5V

Unit

Min. Max.

SCK

Clock Frequency

MHz

CYC

Cycle Time

100

LEAD

CS Lead Time

LAG

CS Lag Time

200

Clock HIGH Time

Clock LOW Time

Data Setup Time

Data Hold Time

(3)

Input Rise Time

(3)

Input Fall Time

CS Deselect Time

(4)

Write Cycle Time

SCK

MSB IN

LAG

LEAD

LSB IN

High Impedance

X55621 Preliminary Information

Characteristics subject to change without notice.

19 of 22

REV 1.0 6/27/00

www.xicor.com

RESET Output Timing

Notes: (5) This parameter is not 100% tested.

(6) This measurement is from 10% to 90% of the supply voltage.

CS/WDI vs. RESET Timing

RESET Output Timing

Symbol

Parameter

Min.

Typ.

Max.

Unit

PURST

RESET Time-out Period

150

250

RPD

(5)

TRIP

RESET (Power down only) V

TRIP

to LOWLINE

µs

RPD2

(5)

TRIP

to V2FAIL

µs

LOWLINE to RESET delay (Power down only)

100

250

800

(6)

/V2MON Fall Time

1000

µs

(6)

/V2MON Rise Time

1000

µs

RVALID

Reset Valid V

VB1

BATT

+ 0.03 v to BATT-ON (logical 0)

µs

VB2

BATT

0.03 v to BATT-ON (logical 1)

µs

Symbol

Parameter

Min.

Typ.

Max.

Unit

WDO

Watchdog Time Out Period,
WD1 = 1, WD0 = 0
WD1 = 0, WD0 = 1
WD1 = 0, WD0 = 0

200
500

150
400
800

250
600

1200

ms
ms
ms

CST

CS Pulse Width to Reset the Watchdog

400

RST

Reset Time Out

150

250

CS/WDI

CST

RESET

WDO

RST

WDO

RST

X55621 Preliminary Information

Characteristics subject to change without notice.

20 of 22

REV 1.0 6/27/00

www.xicor.com

TRIP

Set/Reset Conditions

TRIP

, V2

TRIP

Programming Specifications V

= 2.7-5.5V; Temperature = 25°C

Parameter

Description

Min.

Max.

Unit

VPS

WP V

TRIP

Program Voltage Setup time

µs

VPH

WP V

TRIP

Program Voltage Hold time

µs

TSU

TRIP

Level Setup time

µs

THD

TRIP

Level Hold (stable) time

TRIP

Write Cycle Time

VPO

WP V

TRIP

Program Voltage Off time before next cycle

Programming Voltage

TRAN

TRIP

Programed Voltage Range

2.5

5.0

ta1

Initial V

TRIP

Program Voltage accuracy (V

applied--V

TRIP

) (Programmed

at 25°C.)

-0.2

+0.4

ta2

Subsequent V

TRIP

Program Voltage accuracy [(V

applied--V

ta1

)--V

TRIP

)

(Programmed at 25°C.)

-25

+25

TRIP

Program Voltage repeatability (Successive program operations.)

(Programmed at 25°C.)

-25

+25

TRIP

Program variation after programming (075°C). (Programmed at 25°C.)

-25

+25

TRIP

Programming parameters are periodically sampled and are not 100% tested.

SCK

* 0001h Set V1

TRIP

02h

/V2MON

THD

VPH

VPS

TRIP

VPO

PCS

* 0003h Set V2

TRIP

06h

* 000Bh Reset V1

TRIP

* 000Dh Reset V2

TRIP

X = 1, 2

TSU

* all others reserved

X55621 Preliminary Information

Characteristics subject to change without notice.

22 of 22

LIMITED WARRANTY

Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.

Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.

TRADEMARK DISCLAIMER:

Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.

U.S. PATENTS

Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.

LIFE RELATED POLICY

In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.

Xicor's products are not authorized for use in critical components in life support devices or systems.

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to

perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life

support device or system, or to affect its safety or effectiveness.

REV 1.0 6/27/00

www.xicor.com

Ordering Information

Part Mark Information

Range

TRIP

Range

TRIP

Range

Package

Operating

Temperature Range

Part Number

4.55.5V

4.54.75V

2.552.7V

20L TSSOP

0°C70°C

X55621V20-4.5A

-40°C85°C

X55621V20I-4.5A

4.55.5V

4.54.75V

2.853.0V

20L TSSOP

0°C70°C

X55621V20

-40°C85°C

X55621V20I

2.75.5V

2.853.0V

4.54.75V

20L TSSOP

0°C70°C

X55621V20-2.7A

-40°C85°C

X55621V20I-2.7A

2.75.5V

2.552.75V

4.54.75V

20L TSSOP

0°C70°C

X55621V20-2.7

-40°C85°C

X55621V20I-2.7

V20 = 20-Lead TSSOP

Blank = 5V ±10%, 0°C to +70°C, V1

TRIP

=4.54.75, V2

TRIP

=2.552.7

AL =5V±10%, 0°C to +70°C, V1

TRIP

=4.54.75, V2

TRIP

=2.853.0

I = 5V ±10%, 40°C to +85°C, V1

TRIP

=4.54.75, V2

TRIP

=2.552.7

AM = 5V ±10%, 40°C to +85°C, V1

TRIP

=4.54.75, V2

TRIP

=2.853.0

F = 2.7V to 5.5V, 0°C to +70°C, V1

TRIP

=2.853.0, V2

TRIP

=4.54.75

AN = 2.7V to 5.5V, 0°C to +70°C, V1

TRIP

=2.552.7, V2

TRIP

=4.54.75

G = 2.7V to 5.5V, 40°C to +85°C, V1

TRIP

=2.853.0, V2

TRIP

=4.54.75

AP = 2.7V to 5.5V, 40°C to +85°C, V1

TRIP

=2.552.7, V2

TRIP

=4.54.75

X55621

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