REV 1.3 10/04/02
Characteristics subject to change without notice.
1 of 23
www.xicor.com
Preliminary Information
256K
X55040
Dual Voltage Monitor with Integrated System Battery Switch and EEPROM
FEATURES
Dual voltage monitoring
Active high and active low reset outputs
Four standard reset threshold voltages
(4.6/2.9, 4.6/2.6, 2.9/1.6, 2.6/1.6)
--User programmable thresholds
Lowline Output -- Zero delayed POR
Reset signal valid to V
CC
= 1V
System battery switch-over circuitry
Long battery life with low power consumption
--<50A max standby current, watchdog on
--<30A max standby current, watchdog off
Selectable watchdog timer
--(0.15s, 0.4s, 0.8s, off)
16Kbits of EEPROM
Built-in inadvertent write protection
--Power-up/power-down protection circuitry
--Protect none (0), or all of EEPROM array with
programmable Block Lock
TM
protection
--In circuit programmable ROM mode
Minimize EEPROM programming time
--64 byte page write mode
--Self-timed write cycle
--5ms write cycle time (typical)
10MHz SPI interface modes (0,0 & 1,1)
2.7V to 5.5V power supply operation
Available packages -- 20-lead TSSOP
DESCRIPTION
This device combines power-on reset control, battery
switch circuit, watchdog timer, supply voltage supervi-
sion, secondary voltage supervision, block lock
protect
and serial EEPROM in one package. This combination
lowers system cost, reduces board space require-
ments, and increases reliability.
Applying power to the device activates the power on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
BLOCK DIAGRAM
Watchdog
Timer Reset
Data
Register
Command
Decode, Test
& Control
Logic
SI
SO
SCK
CS
V
CC
Reset &
Watchdog
Timebase
Power On,
Generation
V
CC
Monitor
+
-
RESET
Reset
Low Voltage
Status
Register
Protect Logic
EEPROM Array
Watchdog Transition
Detector
WP
512 X 32
X-Decoder
V
TRIP1
Logic
V2 Monitor
+
-
V
TRIP2
Logic
System
Switch
RESET/MR
LOWLINE
V2FAIL
V2MON
V
BATT
V
OUT
(V1MON)
Battery
WDO
BATT-ON
V
OUT
V
OUT
X55040 Preliminary Information
Characteristics subject to change without notice.
2 of 23
REV 1.3 10/04/02
www.xicor.com
A system battery switch circuit compares V
CC
(V1MON)
with V
BATT
input and connects V
OUT
to whichever is
higher. This provides voltage to external SRAM or other
circuits in the event of main power failure. The X55040
can drive 50mA from V
CC
and 250A from V
BATT
. The
device switches to V
BATT
when V
CC
drops below the low
V
CC
voltage threshold and V
BATT
> V
CC
.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable time
out interval, the device activates the WDO signal. The
user selects the interval from three preset values.
Once selected, the interval does not change, even
after cycling the power.
The device's low V
CC
detection circuitry protects the
user's system from low voltage conditions, resetting the
system when V
CC
(V1MON) falls below the minimum
V
CC
trip point (V
TRIP1
). RESET/RESET is asserted until
V
CC
returns to proper operating level and stabilizes. A
second voltage monitor circuit tracks the unregulated
supply or monitors a second power supply voltage to
provide a power fail warning. Xicor's unique circuits
allow the threshold for either voltage monitor to be
reprogrammed to meet special needs or to fine-tune the
threshold for applications requiring higher precision.
ORDERING INFORMATION
X55040
Suffix
Vtrip1
Vtrip2
Temp Range
V20-4.5A
4.6
2.6
0C to 70C
V20I-4.5A
-40C to 85C
V20-4.5
4.6
2.9
0C to 70C
V20I-4.5
-40C to 85C
V20-2.7A
2.9
1.65
0C to 70C
V20I-2.7A
-40C to 85C
V20-2.7
2.6
1.65
0C to 70C
V20I-2.7
-40C to 85C
PIN CONFIGURATION
20-Pin TSSOP
CS/WDI
SO
NC
1
2
3
4
RESET/MR
V
CC
(V1MON)
BATT-ON
V
OUT
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
RESET
LOWLINE
V2FAIL
V2MON
WP
NC
VSS
V
BATT
SCK
NC
NC
SI
WDO
X55040 Preliminary Information
Characteristics subject to change without notice.
3 of 23
REV 1.3 10/04/02
www.xicor.com
PIN DESCRIPTION
Pin
Name
Function
1
CS/WDI
Chip Select Input.
CS HIGH, deselects the device and the SO output pin is at a high impedance
state. Unless a nonvolatile write cycle is underway, the device will be in the standby power mode.
CS LOW enables the device, placing it in the active power mode. Prior to the start of any opera-
tion after power up, a HIGH to LOW transition on CS is required.
Watchdog Input.
A HIGH to LOW transition on the WDI pin restarts the Watchdog timer. The
absence of a HIGH to LOW transition within the watchdog time out period results in RESET/RESET
going active.
2
NC
No internal connections
3
SO
Serial Output.
SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The
falling edge of the serial clock (SCK) clocks the data out.
4
RESET
Reset Output
.
RESET is an active HIGH, open drain output which is the inverse of the RESET
output.
5
LOWLINE
Low V
CC
Detect
.
This open drain output signal goes LOW when V
CC
< V
TRIP1
and
immediately goes HIGH when V
CC
> V
TRIP1
. This pin goes LOW 250ns before RESET pin.
6
V2FAIL
V2 Voltage Fail Output.
This open drain output goes LOW when V2MON is less than V
TRIP2
and goes HIGH when V2MON exceeds V
TRIP2
. There is no power up reset delay circuitry on this
pin.
7
V2MON
V2 Voltage Monitor Input.
When the V2MON input is less than the V
TRIP2
voltage, V2FAIL goes
LOW. This input can monitor an unregulated power supply with an external resistor divider or can
monitor a second power supply with no external components. Connect V2MON to V
SS
or V
CC
when not used.
8
WP
Write Protect.
The WP pin works in conjunction with a nonvolatile WPEN bit to "lock" the setting
of the Watchdog Timer control and the memory write protect bits.
9
NC
No internal connections
10
V
SS
Ground
11
SI
Serial Input.
SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on
this pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1),
addresses and data MSB first.
12
NC
No internal connections
13
NC
No internal connections
14
SCK
Serial Clock.
The Serial Clock controls the serial bus timing for data input and output. The rising
edge of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of
SCK changes the data output on the SO pin.
15
V
BATT
Battery Supply Voltage.
This input provides a backup supply in the event of a failure of the pri-
mary V
CC
voltage. The V
BATT
voltage typically provides the supply voltage necessary to main-
tain the contents of SRAM and also powers the internal logic to "stay awake." If unused connect
V
BATT
to ground.
X55040 Preliminary Information
Characteristics subject to change without notice.
4 of 23
REV 1.3 10/04/02
www.xicor.com
16
V
OUT
Output Voltage.
V
OUT
= V
CC
if V
CC
> V
TRIP1
.
IF V
CC
< V
TRIP1
, then,
V
OUT
= V
CC
if V
CC
> V
BATT
+0.03
V
OUT
= V
BATT
if V
CC
< V
BATT
-0.03
Note:
There is hysteresis around V
BATT
0.03V point to avoid oscillation at or near the
switchover voltage. A capacitance of 0.1F must be connected to Vout to ensure stability.
17
BATT-ON
Battery On.
This open drain output goes HIGH when the V
OUT
switches to V
BATT
and goes
LOW when V
OUT
switches to V
CC
. It is used to drive an external PNP pass transistor when V
CC
=
V
OUT
and current requirements are greater than 50mA.
The purpose of this output is to drive an external transistor to get higher operating currents when
the V
CC
supply is fully functional. In the event of a V
CC
failure, the battery voltage is applied to
the V
OUT
pin and the external transistor is turned off. In this "backup condition," the battery only
needs to supply enough voltage and current to keep SRAM devices from losing their data-there
is no communication at this time.
18
RESET
/MR
Output/Manual Reset Input
. This is an Input/Output pin.
RESET Output
.
This is an active LOW, open drain output which goes active whenever V
CC
falls
below the minimum V
CC
sense level. When RESET is active communication to the device is inter-
rupted. RESET remains active until V
CC
rises above the minimum V
CC
sense level for 150ms.
RESET also goes active on power up and remains active for 150ms after the power supply
stabilizes.
MR Input
.
This is an active LOW debounced input. When MR is active, the RESET/RESET pins
are asserted. When MR is released, the RESET/RESET remains asserted for t
PURST
, and then
released.
19
WDO
Watchdog Output.
WDO is an active low, open drain output which goes active whenever the
watchdog timer goes active. WDO remains active for 150ms, then returns to the inactive state.
20
V
CC
(V1MON)
Supply Voltage/V1 Voltage Monitor Input.
When the V1MON input is less than the VTRIP1
voltage, RESET and RESET go ACTIVE.
PIN DESCRIPTION (CONTINUED)
Pin
Name
Function
PRINCIPLES OF OPERATION
Power On Reset
Application of power to the X55040 activates a Power
On Reset Circuit. This circuit goes active at about 1V
and pulls the RESET/RESET pin active. This signal
prevents the system microprocessor from starting to
operate with insufficient voltage or prior to stabilization
of the oscillator. When V
CC
exceeds the device V
TRIP1
value for 150ms (nominal) the circuit releases RESET/
RESET, allowing the processor to begin executing
code.
Low V
CC
(V1MON) Voltage Monitoring
During operation, the X55040 monitors the V
CC
level
and asserts RESET/RESET if supply voltage falls
below a preset minimum V
TRIP1
. During this time the
communication to the device is interrupted. The RESET/
RESET signal also prevents the microprocessor from
operating in a power fail or brownout condition. The
RESET signal remains active until the voltage drops
below 1V. These also remain active until V
CC
returns
and exceeds V
TRIP1
for t
PURST
.
Low V2MON Voltage Monitoring
The X55040 also monitors a second voltage level and
asserts V2FAIL if the voltage falls below a preset mini-
mum V
TRIP2
. The V2FAIL signal is either ORed with
RESET to prevent the microprocessor from operating
in a power fail or brownout condition or used to inter-
rupt the microprocessor with notification of an impend-
ing power failure. V2FAIL remains active until V2MON
returns and exceeds V
TRIP2
.
The V2MON voltage sensor is powered by V
OUT
.
If V
CC
and V
BATT
go away (i.e. V
OUT
goes away), then
V2MON cannot be monitored.
X55040 Preliminary Information
Characteristics subject to change without notice.
5 of 23
REV 1.3 10/04/02
www.xicor.com
Figure 1. Two Uses of Dual Voltage Monitoring
X55040
X55040
V
OUT
5V
Reg
5V
Reg
3.3V
Reg
V
CC
V
CC
RESET
RESET
V2MON
V2MON
V2FAIL
V2FAIL
System
Reset
Unregulated
Supply
System
Reset
System
Interrupt
R1
R2
Unregulated
Supply
R1 and R2 selected so V2 = V2MON threshold when
Unregulated supply reaches 6V.
Notice: No external components required to monitor
two voltages.
V
OUT
V2
Watchdog Timer
The Watchdog Timer circuit monitors the microproces-
sor activity by monitoring the CS/WDI pin. The micro-
processor must toggle the CS/WDI pin HIGH to LOW
periodically prior to the expiration of the watchdog time
out period to prevent the WDO signal going active. The
state of two nonvolatile control bits in the Status Regis-
ter determines the watchdog timer period. The micro-
processor can change these watchdog bits by writing
to the status register. The factory default setting dis-
ables the watchdog timer.
The Watchdog Timer oscillator stops when in battery
backup mode. It re-starts when V
CC
returns.
System Battery Switch
As long as V
CC
exceeds the low voltage detect thresh-
old V
TRIP1
, V
OUT
is connected to V
CC
through a 5
Ohm (typical) switch. When the V
CC
has fallen below
V
TRIP
, then V
CC
is applied to V
OUT
if V
CC
is equal to or
greater than V
BATT
+ 0.03V. When V
CC
drops to less
than V
BATT
- 0.03V, then V
OUT
is connected to V
BATT
through an 80 Ohm (typical) switch. V
OUT
typically
supplies the system static RAM voltage, so the
switchover circuit operates to protect the contents of
the static RAM during a power failure. Typically, when
V
CC
has failed, the SRAMs go into a lower power state
and draw much less current than in their active mode.
When V
CC
returns, V
OUT
switches back to V
CC
when
V
CC
exceeds V
BATT
+ 0.03V. There is a 60mV hystere-
sis around this battery switch threshold to prevent
oscillations between supplies.
While V
CC
is connected to V
OUT
the BATT-ON pin is
pulled LOW. The signal can drive an external PNP
transistor to provide additional current to the external
circuits during normal operation.
Operation
The device is in normal operation with V
CC
as long as
V
CC
> V
TRIP1
. It switches to the battery backup mode
when V
CC
goes away.
Condition
Mode of Operation
V
CC
> V
TRIP1
Normal Operation.
V
CC
> V
TRIP1
&
V
BATT
= 0
Normal Operation without battery
back up capability.
0
V
CC
V
TRIP1
and V
CC
< V
BATT
Battery Backup Mode; RESET
signal is asserted. No communica-
tion to the device is allowed.
X55040 Preliminary Information
Characteristics subject to change without notice.
6 of 23
REV 1.3 10/04/02
www.xicor.com
Manual Reset
By connecting a push-button from MR to ground or
driven by logic, the designer adds manual system reset
capability. The RESET/RESET pins are asserted when
the push-button is closed and remain asserted for
t
PURST
after the push-button is released. This pin is
debounced so a push-button connected directly to the
device will have both clean falling and rising edges on
MR.
V
CC
(V1MON), V2MON Threshold Programming
Procedure
The X55040 is shipped with standard V
CC
(V1MON)
and V2MON threshold (V
TRIP1
, V
TRIP2
) voltages. These
values will not change over normal operating and stor-
age conditions. However, in applications where the stan-
dard thresholds are not exactly right, or if higher
precision is needed in the threshold value, the X55040
trip points may be adjusted. The procedure is described
below, and uses the application of a high voltage control
signal.
Setting the V
TRIP
Voltage
This procedure is used to set the V
TRIP1
or V
TRIP2
to a
lower or higher voltage value. It is necessary to reset
the trip point before setting the new value to a lower
level.
To set the new voltage, apply the desired V
TRIP1
threshold voltage to the V
CC
pin or the V
TRIP2
voltage
to the V2MON pin (when setting V
TRIP2
, V
CC
should
be same voltage as V2MON). Next, tie the WP pin to
the programming voltage V
P
. Then, send the WREN
command and write to address 01h or to address 0Bh
to program V
TRIP1
or V
TRIP2
, respectively (followed by
data byte 00h). The CS going high after a valid write
operation initiates the programming sequence. Bring
WP LOW to complete the operation.
To check if the V
TRIPX
has been set, apply a voltage
higher than V
TRIPX
to the VXMON (x = 1, 2) pin. Dec-
rement VXMON in small steps and observe where the
output switches. The voltage at which this occurs is the
V
TRIPX
(actual).
C
ASE
A
If the V
TRIPX
(actual) is lower than the V
TRIPX
(desired), then add the difference between V
TRIPX
(desired) and V
TRIPX
(actual) to the original V
TRIPX
(desired). This is your new V
TRIPX
voltage that should
be applied to VXMON and the whole sequence
repeated again (see Fig 6).
C
ASE
B
If the V
TRIPX
(actual) is higher than the V
TRIPX
(desired), perform the reset sequence as described in
the next section. The new V
TRIPX
voltage to be applied
to VXMON will now be: V
TRIPX
(desired) (V
TRIPX
(desired) V
TRIPX
(actual)).
Note: This operation will not alter the contents of the
EEPROM.
Figure 2. Example System Connection
V
CC
5V
Reg
+
Unregulated
Supply
Address
Decode
Enable
SRAM
Addr
V
CC
NMI
RESET
SPI C
V
BATT
V2MON
V
SS
BATT-ON
V
OUT
V2FAIL
RESET
CS, SCK
SI, SO
V
OUT
PNP transistor
or P-channel FET
X55040 Preliminary Information
Characteristics subject to change without notice.
7 of 23
REV 1.3 10/04/02
www.xicor.com
Figure 3. Set V
TRIPX
Level Sequence
Figure 4. Reset V
TRIPX
Level Sequence
0 1 2 3 4 5 6 7
0 1
2 3 4 5 6
CS
SCK
SI
16 Bits
7
8 9 10
20 21 22 23
WP
V
P
= 10-15V
06h
WREN
02h
WRITE
00h
DATA
0001h/000Bh
ADDRESS
Addr 01h: Set V
TRIP1
Addr 0Bh: Set V
TRIP2
0 1 2 3 4 5 6 7
0 1
2 3 4 5 6
CS
SCK
SI
16 Bits
7
8 9 10
20 21 22 23
WP
V
P
= 10-15V
06h
WREN
02h
WRITE
00h
DATA
0003h/000Dh
ADDRESS
Addr 03h: Reset V
TRIP1
Addr 0Dh: Reset V
TRIP2
Resetting the V
TRIP
Voltage
To reset V
TRIP1
, apply greater than 3V to V
CC
(V1MON). To reset V
TRIP2
, apply greater than 3V to
both V
CC
and V2MON. Next, tie the WP pin to the
programming voltage V
P
. Then send the WREN
command and write to address 03h or 0Dh to reset the
V
TRIP1
or V
TRIP2
respectively (followed by data byte
00h). The CS going LOW to HIGH after a valid write
operation initiates the programming sequence. Bring
WP LOW to complete the operation.
Note: This operation does not change the contents of
the EEPROM array.
X55040 Preliminary Information
Characteristics subject to change without notice.
8 of 23
REV 1.3 10/04/02
www.xicor.com
Figure 5. Sample V
TRIP
Circuit
Figure 6. V
TRIP
Programming Sequence Flow Chart
CS
V
CC
V
P
Adjust
Run
V
TRIP
Adj.
SO
WP
V
SS
RESET
SCK
SI
X55040
4.7K
RESET
SO
CS
SI
SCK
C
V
TRIPX
Programming
Apply V
CC
and Voltage
Decrease V
X
Actual V
TRIPX -
Desired V
TRIPX
DONE
Set Higher V
TRIPX
Sequence
Error < MDE
| Error | < | MDE |
YES
NO
Error > MDE
+
> Desired V
TRIPX
to V
X
Desired
Present Value?
V
TRIPX
<
Execute
No
YES
Execute
V
TRIPX
Reset Sequence
Set
V
X
= desired V
TRIPX
New V
X
applied =
Old V
X
applied + | Error |
New V
X
applied =
Old V
X
applied - | Error |
Execute Reset V
TRIPX
Sequence
Output Switches?
Note: X = 1, 2
Let: MDE = Maximum Desired Error
Vx = VxMON
MDE
+
Desired Value
MDE
Acceptable
Error Range
Error = Actual - Desired
X55040 Preliminary Information
Characteristics subject to change without notice.
9 of 23
REV 1.3 10/04/02
www.xicor.com
SPI SERIAL MEMORY
The memory portion of the device is a CMOS Serial
EEPROM array with Xicor's block lock protection. The
array is internally organized as x 8. The device features
a Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple four-wire bus.
The device utilizes Xicor's proprietary Direct Write
TM
cell, providing a minimum endurance of 100,000 cycles
and a minimum data retention of 100 years.
The device is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular microcontroller families. It contains an 8-bit
instruction register that is accessed via the SI input,
with data being clocked in on the rising edge of SCK.
CS must be LOW during the entire operation.
All instructions (Table 1), addresses and data are
transferred MSB first. Data input on the SI line is
latched on the first rising edge of SCK after CS goes
LOW. Data is output on the SO line by the falling edge
of SCK. SCK is static, allowing the user to stop the
clock and then start it again to resume operations
where left off.
Write Enable Latch
The device contains a Write Enable Latch. This latch
must be SET before a Write Operation is initiated. The
WREN instruction sets the latch and the WRDI instruc-
tion resets the latch (Figure 9). This latch is automati-
cally reset upon a power-up condition and after the
completion of a valid Write Cycle.
Status Register
The RDSR instruction provides access to the Status
Register. The Status Register may be read at any time,
even during a Write Cycle. The Status Register is for-
matted as follows:
The Write-In-Progress (WIP) bit is a volatile, read only
bit and indicates whether the device is busy with an
internal nonvolatile write operation. The WIP bit is read
using the RDSR instruction. When set to a "1", a non-
volatile write operation is in progress. When set to a
"0", no write is in progress.
7
6
5
4
3
2
1
0
WPEN
WD1
WD0
PUP
BL1
BL0
WEL
WIP
Table 1. Instruction Set
Note:
*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
Table 2. Block Protect Matrix
Instruction Name
Instruction Format*
Operation
WREN
0000 0110
Set the Write Enable Latch (Enable Write Operations)
WRDI
0000 0100
Reset the Write Enable Latch
RSDR
0000 0101
Read Status Register
WRSR
0000 0001
Write Status Register (Watchdog, block lock, WPEN)
READ
0000 0011
Read Data from Memory Array Beginning at Selected Address
WRITE
0000 0010
Write Data to Memory Array Beginning at Selected Address
WREN CMD
Status Register
Device Pin
Block
Block
Status Register
WEL
WPEN
WP
Protected Block Unprotected Block
WPEN, BL0, BL1,
PUP, WD0, WD1
0
X
X
Protected
Protected
Protected
1
1
0
Protected
Writable
Protected
1
0
X
Protected
Writable
Writable
1
X
1
Protected
Writable
Writable
X55040 Preliminary Information
Characteristics subject to change without notice.
10 of 23
REV 1.3 10/04/02
www.xicor.com
The Write Enable Latch (WEL) bit indicates the Status
of the Write Enable Latch. When WEL = 1, the latch is
set HIGH and when WEL = 0 the latch is reset LOW.
The WEL bit is a volatile, read only bit. It can be set by
the WREN instruction and can be reset by the WRDS
instruction.
The block lock bits, BL0 and BL1, set the level of block
lock protection. These nonvolatile bits are programmed
using the WRSR instruction and allow the user to pro-
tect one quarter, one half, all or none of the EEPROM
array. Any portion of the array that is block lock pro-
tected can be read but not written. It will remain pro-
tected until the BL bits are altered to disable block lock
protection of that portion of memory.
The power on reset time (t
PURST
) bit, PUP sets the
initial power or reset time. There are two standard
settings.
The Watchdog Timer bits, WD0 and WD1, select the
Watchdog Time-out Period. These nonvolatile bits are
programmed with the WRSR instruction.
The nonvolatile WPEN bit is programmed using the
WRSR instruction. This bit works in conjunction with
the WP pin to provide an In-Circuit Programmable
ROM function (Table 2). WP tied to V
SS
and WPEN bit
programmed HIGH disables all Status Register Write
Operations.
Note 1. Watchdog timer is shipped disabled.
2. The t
PURST
time is set to 150ms at the factory.
In Circuit Programmable ROM Mode
This mechanism protects the block lock and Watchdog
bits from inadvertent corruption.
In the locked state (Programmable ROM Mode) the
WP pin is LOW and the nonvolatile bit WPEN is "1".
This mode disables nonvolatile writes to the device's
Status Register.
Setting the WP pin LOW while WPEN is a "1" while an
internal write cycle to the Status Register is in progress
will not stop this write operation, but the operation dis-
ables subsequent write attempts to the Status Register.
Status Register Bits
Array Addresses Protected
BL1
BL0
X55040
0
0
None (factory setting)
0
1
None
1
0
None
1
1
000h7FFh (All)
PUP
Time
0
150 milliseconds (factory settings)
1
800 milliseconds
Status Register Bits
Watchdog Time Out
(Typical)
WD1
WD0
0
0
800 milliseconds
0
1
400 milliseconds
1
0
150 milliseconds
1
1
disabled (factory setting)
Figure 7. Read EEPROM Array Sequence
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25
26 27 28 29 30
7
6
5
4
3
2
1
0
Data Out
CS
SCK
SI
SO
MSB
High Impedance
Instruction
16 Bit Address
15 14 13
3
2
1
0
X55040 Preliminary Information
Characteristics subject to change without notice.
11 of 23
REV 1.3 10/04/02
www.xicor.com
When WP is HIGH, all functions, including nonvolatile
writes to the Status Register operate normally. Setting
the WPEN bit in the Status Register to "0" blocks the
WP pin function, allowing writes to the Status Register
when WP is HIGH or LOW. Setting the WPEN bit to "1"
while the WP pin is LOW activates the Programmable
ROM mode, thus requiring a change in the WP pin
prior to subsequent Status Register changes. This
allows manufacturing to install the device in a system
with WP pin grounded and still be able to program the
Status Register. Manufacturing can then load Configu-
ration data, manufacturing time and other parameters
into the EEPROM, then set the portion of memory to
be protected by setting the block lock bits, and finally
set the "OTP mode" by setting the WPEN bit. Data
changes to protected areas of the device now require a
hardware change.
Read Sequence
When reading from the EEPROM memory array, CS is
first pulled low to select the device. The 8-bit READ
instruction is transmitted to the device, followed by the
16-bit address. After the READ opcode and address are
sent, the data stored in the memory at the selected
address is shifted out on the SO line. The data stored in
memory at the next address can be read sequentially by
continuing to provide clock pulses. The address is auto-
matically incremented to the next higher address after
each byte of data is shifted out. The read operation is
terminated by taking CS high. Refer to the Read
EEPROM Array Sequence (Figure 7).
To read the Status Register, the CS line is first pulled
low to select the device followed by the 8-bit RDSR
instruction. After the RDSR opcode is sent, the contents
of the Status Register are shifted out on the SO line.
Refer to the Read Status Register Sequence (Figure 8).
Refer to the Serial Output Timing on page 18.
Write Sequence
Prior to any attempt to write data into the device, the
"Write Enable" Latch (WEL) must first be set by issuing
the WREN instruction (Figure 9). CS is first taken LOW,
then the WREN instruction is clocked into the device.
After all eight bits of the instruction are transmitted, CS
must then be taken HIGH. If the user continues the
Write Operation without taking CS HIGH after issuing
the WREN instruction, the Write Operation will be
ignored.
To write data to the EEPROM memory array, the user
then issues the WRITE instruction followed by the 16
bit address and then the data to be written. Any
unused address bits are specified to be "0's". The
WRITE operation minimally takes 32 clocks. CS must
go low and remain low for the duration of the operation.
If the address counter reaches the end of a page and
the clock continues, the counter will roll back to the first
address of the page and overwrite any data that may
have been previously written.
For the Page Write Operation (byte or page write) to be
completed, CS can only be brought HIGH after bit 0 of
the last data byte to be written is clocked in. If it is
brought HIGH at any other time, the write operation will
not be completed (Figure 10).
To write to the Status Register, the WRSR instruction is
followed by the data to be written (Figure 11). Data
bits.
While the write is in progress following a Status Regis-
ter or EEPROM Sequence, the Status Register may be
read to check the WIP bit. During this time the WIP bit
will be high. Refer to Serial Input timing on page 17.
OPERATIONAL NOTES
The device powers-up in the following state:
The device is in the low power standby state.
A HIGH to LOW transition on CS is required to enter
an active state and receive an instruction.
SO pin is high impedance.
The Write Enable Latch is reset.
Reset Signal is active for t
PURST
.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
A WREN instruction must be issued to set the Write
Enable Latch.
A valid write command and address must be sent to
the device.
CS must come HIGH after a multiple of 8 data bits in
order to start a nonvolatile write cycle.
X55040 Preliminary Information
Characteristics subject to change without notice.
12 of 23
REV 1.3 10/04/02
www.xicor.com
Figure 8. Read Status Register Sequence
Figure 9. Write Enable Latch Sequence
0
1
2
3
4
5
6
7
8
9
10
11 12 13 14
7
6
5
4
3
2
1
0
Data Out
CS
SCK
SI
SO
MSB
High Impedance
Instruction
0
1
2
3
4
5
6
7
CS
SI
SCK
High Impedance
SO
X55040 Preliminary Information
Characteristics subject to change without notice.
13 of 23
REV 1.3 10/04/02
www.xicor.com
Figure 10. Write Sequence
Figure 11. Status Register Write Sequence
Symbol Table
32 33 34 35 36 37 38 39
SCK
SI
CS
0
1
2
3
4
5
6
7
8
9
10
SCK
SI
Instruction
16 Bit Address
Data Byte 1
7
6
5
4
3
2
1
0
CS
40 41 42 43 44 45 46 47
Data Byte 2
7
6
5
4
3
2
1
0
Data Byte 3
7
6
5
4
3
2
1
0
Data Byte N
15 14 13
3
2
1
0
20 21 22 23 24 25 26 27 28 29 30 31
6
5
4
3
2
1
0
0
1
2
3
4
5
6
7
8
9
CS
SCK
SI
SO
High Impedance
Instruction
Data Byte
7
6
5
4
3
2
1
0
10
11 12 13 14 15
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don't Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
X55040 Preliminary Information
Characteristics subject to change without notice.
14 of 23
REV 1.3 10/04/02
www.xicor.com
ABSOLUTE MAXIMUM RATINGS
Temperature under bias ...................65C to +135C
Storage temperature ........................65C to +150C
Voltage on any pin with
respect to V
SS
...................................... 1.0V to +7V
D.C. output current
(all output pins except V
OUT
) ............................ 5mA
D.C. Output Current V
OUT
.................................. 50mA
Lead temperature (soldering, 10 seconds).........300C
COMMENT
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only; the functional operation of
the device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating con-
ditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature
Min.
Max.
Commercial
0C
70C
Industrial
40C
+85C
D.C. OPERATING CHARACTERISTICS
(Over recommended operating conditions unless otherwise specified. (V
CC
= 2.7V to 5.5V))
Symbol
Parameter
Limits
Unit
Test Conditions
Min.
Typ.
(5)
Max.
I
CC1
(1)
V
CC
Supply Current (Active)
(Excludes I
OUT
) Read Memory array
(Excludes I
OUT
) Write nonvolatile
Memory
1.5
3.0
mA
SCK = V
CC
x 0.1/V
CC
x 0.9
@ 10MHz
I
CC2
(2)
V
CC
Supply Current (Passive)
(Excludes I
OUT
) WDT on, 5V
(Excludes I
OUT
) WDT on, 2.7V
(Excludes I
OUT
) WDT off, 5V
50.0
40.0
30.0
90.0
60.0
50.0
A
CS = V
CC
, Any Input = V
SS
or V
CC
, V
OUT
, RESET,
RESET, LOWLINE = Open
I
CC3
(1)
V
CC
Current (Battery Backup Mode)
(Excludes I
OUT
)
1
A
V
CC
= 0V, V
BATT
= 2.8V,
V
OUT
, RESET = Open
I
BATT1
(3)
V
BATT
Current (Excludes I
OUT
)
1
A
V
OUT
= V
CC
I
BATT2
V
BATT
Current (Excludes I
OUT
)
(Battery Backup Mode)
0.4
1.0
A
V
OUT
= V
BATT
,
V
BATT
= 2.8V
V
OUT
, RESET = Open
V
OUT1
Output Voltage (V
CC
> V
BATT
+ 0.03V
or V
CC
> V
TRIP1
)
V
CC
0.05
V
CC
0.5
V
CC
-0.02
V
CC
-0.2
V
V
I
OUT
= -5mA
I
OUT
= -50mA
V
OUT2
Output Voltage (V
CC
< V
BATT
0.03V
and V
CC
< V
TRIP1
) {Battery Backup}
V
BATT
0.2
V
V
I
OUT
= -250A
V
OLB
Output (BATT-ON) LOW Voltage
0.4
V
I
OL
= 3.0mA (5V)
I
OL
= 1.0mA (3V)
V
BSH
Battery Switch Hysteresis
(V
CC
< V
TRIP1
)
30
-30
mV
mV
Power Up
Power Down
X55040 Preliminary Information
Characteristics subject to change without notice.
15 of 23
REV 1.3 10/04/02
www.xicor.com
Notes: (1) The device enters the Active state after any start, and remains active until 9 clock cycles later if the Device Select Bits in the Slave
Address Byte are incorrect; 200ns after a stop ending a read operation; or t
WC
after a stop ending a write operation.
(2) The device goes into Standby: 200ns after any Stop, except those that initiate a high voltage write cycle; t
WC
after a stop that
initiates a high voltage cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave
Address Byte.
(3) Negative number indicate charging current, Positive numbers indicate discharge current.
(4) V
IL
min. and V
IH
max. are for reference only and are not tested.
(5) V
CC
= 5V at 25C.
(6) V
TRIP1
and V
TRIP2
are programmable. See page 22 and 23 for programming specifications and pages 6, 7 and 8 for programming
procedure. For custom programmed levels, contact factory.
(7) Based on characterization data.
CAPACITANCE T
A
= +25C, f = 1MHz, V
CC
= 5V
Note:
(1) This parameter is periodically sampled and not 100% tested.
RESET/RESET/LOWLINE/WDO
V
TRIP1
(6)
V
CC
Reset Trip Point Voltage
4.5
4.62
4.75
V
-4.5A and -4.5 versions
2.85
3.0
V
-2.7A version
2.55
2.75
V
-2.7 version
V
OLR
Output (RESET, RESET, LOWLINE,
WDO) LOW Voltage
0.4
V
I
OL
= 3.0mA (5V)
I
OL
= 1.0mA (3V)
Second Supply Monitor
V
TRIP2
(6)
V2MON Reset Trip Point Voltage
2.85
3.0
V
-4.5 version
2.55
2.7
V
-4.5A version
1.6
1.7
V
-2.7A and -2.7 version
V
OLx
Output (V2FAIL) LOW Voltage
0.4
V
I
OL
= 3.0mA (5V)
I
OL
= 1.0mA (3V)
SPI Interface
V
ILx
(4)
Input (CS, SI, SCK, WP) LOW Voltage
-0.5
V
CC
x 0.3
V
V
IHx
(4)
Input (CS, SI, SCK, WP) HIGH Voltage
V
CC
x 0.7
V
CC
+
0.5
V
I
LIx
Input Leakage Current (CS, SI,
SCK, WP)
10
A
V
OLS
Output (SO) LOW Voltage
0.4
V
I
OL
= 3.0mA (5V)
I
OL
= 1.0mA (3V)
V
OHS
Output (SO) HIGH Voltage
V
OUT
0.8
V
I
OH
= -1.0mA (5V)
Symbol
Test
Max.
Unit
Conditions
C
OUT
(1)
Output Capacitance (SO, RESET, V2FAIL, RESET, LOWLINE, BATT-ON,
WDO)
8
pF
V
OUT
= 0V
C
IN
(1)
Input Capacitance (SCK, SI, CS, WP)
6
pF
V
IN
= 0V
D.C. OPERATING CHARACTERISTICS (CONTINUED)
(Over recommended operating conditions unless otherwise specified. (V
CC
= 2.7V to 5.5V))
Symbol
Parameter
Limits
Unit
Test Conditions
Min.
Typ.
(5)
Max.
X55040 Preliminary Information
Characteristics subject to change without notice.
16 of 23
REV 1.3 10/04/02
www.xicor.com
EQUIVALENT A.C. LOAD CIRCUIT AT 5V V
CC
A.C. TEST CONDITIONS
V
OUT
SO
30pF
RESET/RESET
2.06K
3.03K
V
OUT
1.53K
30pF
BATT-ON/LOWLINE/
V2FAIL, WDO
Input pulse levels
V
CC
x 0.1 to V
CC
x 0.9
Input rise and fall times
10ns
Input and output timing level
V
CC
x0.5
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)
Serial Input Timing
Symbol Parameter
V
CC
= 2.75.5V
Unit
Min. Max.
f
SCK
Clock Frequency
10
MHz
t
CYC
Cycle Time
100
ns
t
LEAD
CS Lead Time
50
ns
t
LAG
CS Lag Time
200
ns
t
WH
Clock HIGH Time
40
ns
t
WL
Clock LOW Time
40
ns
t
SU
Data Setup Time
10
ns
t
H
Data Hold Time
10
ns
t
RI
(3)
Input Rise Time
20
ns
t
FI
(3)
Input Fall Time
20
ns
t
CS
CS Deselect Time
50
ns
t
WC
(4)
Write Cycle Time
10
ms
X55040 Preliminary Information
Characteristics subject to change without notice.
17 of 23
REV 1.3 10/04/02
www.xicor.com
Serial Input Timing
Serial Output Timing
Notes: (3) This parameter is periodically sampled and not 100% tested.
(4) t
WC
is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile
write cycle.
Symbol Parameter
2.75.5V
Unit
Min. Max.
f
SCK
Clock Frequency
10
MHz
t
DIS
Output Disable Time
50
ns
t
V
Output Valid from Clock Low
40
ns
t
HO
Output Hold Time
0
ns
t
RO
(3)
Output Rise Time
25
ns
t
FO
(3)
Output Fall Time
25
ns
SCK
CS
SI
SO
MSB IN
t
SU
t
RI
t
LAG
t
LEAD
t
H
LSB IN
t
CS
t
FI
High Impedance
X55040 Preliminary Information
Characteristics subject to change without notice.
18 of 23
REV 1.3 10/04/02
www.xicor.com
Serial Output Timing
Power-Up and Power-Down Timing
SCK
CS
SO
SI
MSB Out
MSB1 Out
LSB Out
ADDR
LSB IN
t
CYC
t
V
t
HO
t
WL
t
WH
t
DIS
t
LAG
t
VB1
RESET
t
VB2
t
PURST
t
PURST
t
RPD
V
BATT
V
CC
V
BAT
0V
V
OUT
V
OUT
V
TRIP1
0V
V
OUT
V
CC
RESET
BATT-ON
X55040 Preliminary Information
Characteristics subject to change without notice.
19 of 23
REV 1.3 10/04/02
www.xicor.com
V
CC
to LOWLINE Timings
V2MON to V2FAIL Timings
RESET/RESET/LOWLINE Output Timing
Notes: (1) This parameter is not 100% tested.
(2) This measurement is from 10% to 90% of the supply voltage.
(3) V
CC
= 5V at 25C.
(4) Based on characterization data only.
Symbol
Parameter
Min.
Typ.
(3)
Max.
Unit
t
PURST
RESET/RESET Time-out Period
PUP = 0
PUP = 1
75
500
150
800
250
1200
ms
t
RPD
(1)
V
TRIP1
to RESET/RESET (Power down only) V
TRIP1
to LOWLINE
10
20
s
t
RPD2
(1)
V
TRIP2
to V2FAIL
10
20
s
t
LR
LOWLINE to RESET/RESET delay (Power down only)
100
250
(4)
800
ns
t
F
(2)
V
CC
/V2MON Fall Time
1000
s
t
R
(2)
V
CC
/V2MON Rise Time
1000
s
V
RVALID
Reset Valid V
CC
1
V
t
VB1
V
BATT
+ 0.03 v to BATT-ON (logical 0)
20
(4)
s
t
VB2
V
BATT
- 0.03 v to BATT-ON (logical 1)
20
(4)
s
V
CC
LOWLINE
V
TRIP
V
BATT
V
TRIP1
0V
V
OH
V
OL
V
TRIP1
0V
t
R
t
RPD
t
RPD
t
F
V
TRIP2
0V
t
R
t
RPD2
t
RPD2
t
F
V2MON
V2FAIL
V
OUT
X55040 Preliminary Information
Characteristics subject to change without notice.
20 of 23
REV 1.3 10/04/02
www.xicor.com
CS/WDI vs. WDO Timing
RESET/RESET Output Timing
Notes: (1) V
CC
= 5V at 25C.
(2) Based on characterization data only.
V
TRIP
Set/Reset Conditions
Symbol
Parameter
Min.
Typ.
(1)
Max.
Unit
t
WDO
Watchdog Time Out Period,
WD1 = 1, WD0 = 0
WD1 = 0, WD0 = 1
WD1 = 0, WD0 = 0
75
200
500
150
400
(2)
800
(2)
250
600
1200
ms
ms
ms
t
CST
CS Pulse Width to Reset the Watchdog
400
ns
t
RST
Reset Time Out
75
150
250
ms
CS/WDI
t
CST
WDO
t
WDO
t
RST
t
WDO
t
RST
SCK
CS
* 0001h Set V
TRIP1
02h
V
CC
/V2MON
WP
t
THD
t
VPH
t
VPS
V
P
V
TRIPX
t
WC
t
VPO
t
PCS
* 0003h Set V
TRIP2
06h
* 000Bh Reset V
TRIP1
* 000Dh Reset V
TRIP2
SI
X = 1, 2
t
TSU
* all others reserved
0n
8
clocks
X55040 Preliminary Information
Characteristics subject to change without notice.
21 of 23
REV 1.3 10/04/02
www.xicor.com
V
TRIP1
, V
TRIP2
Programming Specifications V
CC
= 2.7-5.5V; Temperature = 25C
Parameter
Description
Min.
Max.
Unit
t
VPS
WP V
TRIPX
Program Voltage Setup time
10
s
t
VPH
WP V
TRIPX
Program Voltage Hold time
10
s
t
TSU
V
TRIPX
Level Setup time
10
s
t
THD
V
TRIPX
Level Hold (stable) time
10
ms
t
WC
V
TRIPX
Write Cycle Time
10
ms
t
VPO
WP V
TRIPX
Program Voltage Off time before next cycle
1
ms
V
P
Programming Voltage
10
15
V
V
TRAN
V
TRIPX
Programed Voltage Range
2.5
5.0
V
V
tv
V
TRIPX
Program variation after programming (075C). (Programmed at 25C
according to the procedure defined on pages 6, 7 and 8.)
-25
+25
mV
V
TRIPX
programming parameters are periodically sampled and are not 100% tested.
X55040 Preliminary Information
Characteristics subject to change without notice.
22 of 23
REV 1.3 10/04/02
www.xicor.com
PACKAGING INFORMATION
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
20-Lead Plastic, TSSOP, Package Type V
See Detail "A"
.031 (.80)
.041 (1.05)
.169 (4.3)
.177 (4.5)
.252 (6.4) BSC
.025 (.65) BSC
.193 (4.9)
.200 (5.1)
.002 (.05)
.006 (.15)
.047 (1.20)
.0075 (.19)
.0118 (.30)
0 - 8
.010 (.25)
.019 (.50)
.029 (.75)
Gage Plane
Seating Plane
Detail A (20X)
X55040 Preliminary Information
Characteristics subject to change without notice.
23 of 23
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor's products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
Xicor, Inc. 2001 Patents Pending
REV 1.3 10/04/02
www.xicor.com
Part Mark Information
V20 = 20-Lead TSSOP
W
X55040
X
YYww
Date
Code
Part
Mark
V
TRIP1
Range
V
TRIP2
Range
Operating
Temperature Range
Part Number
Blank
4.54.75V
2.552.7V
0C70C
X55040V20-4.5A
I
-40C85C
X55040V20I-4.5A
AL
4.54.75V
2.853.0V
0C70C
X55040V20-4.5
AM
-40
C85
C
X55040V20I-4.5
F
2.853.0V
1.61.7V
0C70C
X55040V20-2.7A
G
-40
C85
C
X55040V20I-2.7A
AN
2.552.75V
1.61.7V
0C70C
X55040V20-2.7
AP
-40
C85
C
X55040V20I-2.7
PDF 
ZIP