Xicor, Inc. 2000 Patents Pending

9900-3003.5 4/24/00 EP

Characteristics subject to change without notice.

1 of 17

64K

X40620

BLOCK DIAGRAM

Command

Decode

and

Control

Logic

HV Generation

Timing and Control

X Decoder

Y Decoder

Data Register

Write Control

SCL

SDA

V2FAIL

) Control Signal

V2MON

RESET

Logic

Power on and

Generation

2TRIP

Reset

Low Voltage

TRIP

Reset &

Watchdog

Timebase

Watchdog

Timer Reset

EEPROM Array

(64Kbits)

Dual Voltage CPU Supervisor with 64K Serial EEPROM

FEATURES

· Dual Voltage Detection and Reset Assertion

--Three standard reset threshold settings. (3.1V/

2.6V, 3.1V/1.7V, 2.9V/2.3V)

--Adjust low voltage reset threshold voltages

using special programming sequence

--RESET signal valid down to V

=1V

· Watchdog Timer (150ms)
· Power On Reset (150ms)
· Low Power CMOS

--10µA typical standby current, watchdog on
--400µA typical standby current, watchdog off

· 64kbit 2-Wire Serial EEPROM

--1MHz serial interface speed
--64-byte page write mode
--Self-timed write cycle
--5ms write cycle time (typical)

· 2.5 to 3.7V Power Supply Operation
· 8-Lead TSSOP package

DESCRIPTION

The X40620 combines several functions into one
device. The first is a dual voltage monitoring, power-on
reset control, watchdog timer and 64Kbit serial

EEPROM memory in one package. This combination
lowers system cost, reduces board space require-
ments, and increases reliability.

Applying voltage to V

activates the power on reset

circuit which holds RESET active for a period of time.
This allows the power supply and system oscillator to
stabilize before the processor can execute code.

Low V

detection circuitry protects the user's system

from low voltage conditions, resetting the system when
V

falls below the set minimum Vtrip point. RESET is

active until V

returns to proper operating level and

stabilizes.

A second voltage monitor circuit (V2MON) tracks the
unregulated supply to provide a power fail warning or
monitors different power supply voltage. When the
second monitored voltage drops below a preset
V2

TRIP

voltage. V2FAIL is active until V2 returns to

proper operating level and above the V2

TRIP

voltage.

Five common low voltage combinations are available,
however, Xicor's unique circuits allows the threshold
for either voltage monitor to be reprogrammed to meet
special needs or to fine-tune the threshold for applica-
tions requiring higher precision.

X40620

Characteristics subject to change without notice.

2 of 17

PACKAGE/PINOUTS

PIN NAMES

PIN DESCRIPTIONS

Serial Clock (SCL)

The SCL input is used to clock all data into and out of
the device.

Serial Data (SDA)

SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with other open drain or open col-
lector outputs. An open drain requires the use of a
pull-up resistor.

Write Protect (WP)

The WP pin should be tied HIGH at all time. (This WP
pin is reserved for internal factory testing only).

Reset Output (RESET)

RESET is an active LOW, open drain output which
goes active whenever V

falls below the minimum

Vtrip sense level. It will remain active until V

rises

above the minimum Vtrip sense level for 150ms.
RESET goes active if the Watchdog Timer is enabled
and there is no start bit before the end of the select-
able Watchdog time-out period. A serial start bit will
reset the Watchdog Timer. RESET also goes active on
power up at 1V and remains active for 150ms after the
power supply stabilizes.

V2 Voltage Fail Output (V2FAIL)

V2FAIL is an active LOW, open drain output which
goes active whenever V2MON falls below the mini-
mum V2trip sense level. It will remain active until
V2MON rises above the minimum V2MON sense level.

DEVICE OPERATION

Power On Reset

Application of power to the X40620 activates a Power
On Reset Circuit. This circuit goes active at 1V and
pulls the RESET pin active. This signal prevents the
system microprocessor from starting to operate with
insufficient voltage or prior to stabilization of the oscil-
lator. When V

exceeds the device V

TRIP

value for

200ms (nominal) the circuit releases RESET allowing
the processor to begin executing code.

Low Voltage V

(V1) Monitoring

During operation, the X40620 monitors the V

level

and asserts RESET if supply voltage falls below a pre-
set minimum V

TRIP

. The RESET signal prevents the

microprocessor from operating in a power fail or
brownout condition. The RESET signal remains active
until the voltage drops below 1V. It also remains active
until V

returns and exceeds V

TRIP

for 200ms.

When the internal low voltage detect circuitry senses
that V

is low, the following happens:

The RESET pin goes active.

Communication to the device is interrupted and any

command is aborted. If a serial nonvolatile store is in
progress when power fails, the circuitry does not
stop the nonvolatile store operation, but attempts to
complete the operation.

The low V

threshold is typically set to 3.1V for a 2.5

to 3.7V operating range.

LOW VOLTAGE V2 MONITORING

The X40620 also monitors a second voltage level and
asserts V2FAIL if the voltage falls below a preset mini-
mum V2

TRIP

. The V2FAIL signal is either ORed with

RESET to prevent the microprocessor from operating
in a power fail or brownout condition or used to inter-
rupt the microprocessor with notification of an impend-
ing power failure. The V2FAIL signal remains active
until the V

drops below 1V. It also remains active

until V2MON returns and exceeds V2

TRIP

by 0.2V

Ground

SDA

Serial Data

Power

SCL

Serial Clock

Write Protect

V2MON

Voltage monitor input

RESET

Low Voltage Detect Output

V2FAIL

V2 Voltage Fail Output

V2FAIL

SCL

V2MON

SDA

RESET

8L TSSOP

X40620

Characteristics subject to change without notice.

3 of 17

When the internal low voltage detect circuitry senses
that V2MON is low, the V2FAIL pin goes active. Typi-
cally this would be used by the processor as an inter-
rupt to stop the execution of the code or to do
housekeeping in preparation for an impending power
failure.

The RESET and V2FAIL signals remain active until
V

voltage drops below 1V. RESET remains active

until V

returns and exceeds V

TRIP

for 200ms.

V2FAIL remains active until immediately after V2MON
returns and exceeds it's minimum voltage.

Watchdog Timer

The Watchdog Timer circuit monitors the microproces-
sor activity by monitoring the Start bit. The micropro-
cessor must send a start bit periodically to prevent a
RESET signal. The start bit must occur prior to the
expiration of the watchdog time-out period. The watch-
dog timer period is set at 150msec.

SERIAL MEMORY OPERATION

There are two primary modes of operation for the
X40620; READ and WRITE of the memory arrays.

The basic method of communication to the memory
areas of the device is established by generating a start
condition, then transmitting a command, followed by
the address. The user must perform ACK Polling to
determine the validity of the address, before starting a
data transfer (see Acknowledge Polling.)

Data is transferred in 8-bit segments, with each trans-
fer being followed by an ACK, generated by the receiv-
ing device.

If the X40620 is in a nonvolatile write cycle a "no ACK"
(SDA=HIGH) response will be issued in response to
loading of the command byte. If a stop is issued prior
to the start of a nonvolatile write cycle the write opera-
tion will be terminated and the part will reset and enter
into a standby mode.

The basic sequence is illustrated in Figure 1.

After each transaction is completed, the X40620 will
reset and enter into a standby mode.

Figure 1. X40620 Device Operation

V2FAIL

RESET

V2MON

SCL

SDA

Volt

Reg

SCL

SDA

INTR

RESET

µC

OTP Mode

Enabled

Recommended Connection

Pin 1

Load Command Byte

Load 2 Byte Address

Read/Write

Data Bytes

TWC or Data ACK Polling

X40620

Characteristics subject to change without notice.

4 of 17

Figure 2. Set V

TRIP

Level Sequence (V

TRIP

)

Figure 3. Set V2

TRIP

Level Sequence (V

TRIP

)

Figure 4. Reset V

TRIP

Level Sequence (V

> 3V, WEL is set.)

SDA

D8h

00h

RESET

= 15V

01h

TRIP

01h sets V

SCL

2 3

5 6

0 1

2 3

5 6

0 1

2 3

5 6

0 1

2 3

5 6

00h

SDA

D8h

00h

RESET

= 15V

0Dh

TRIP

V2MON

0Dh sets V2MON

SCL

2 3

5 6

0 1

2 3

5 6

0 1

2 3

5 6

0 1

2 3

5 6

00h

SDA

D8h

00h

RESET

= 15V

TRIP

03h

03h resets V

SCL

2 3

5 6

0 1

2 3

5 6

0 1

2 3

5 6

0 1

2 3

5 6

00h

X40620

Characteristics subject to change without notice.

5 of 17

Figure 5. Reset V2

TRIP

Level Sequence (V

> 3V, WEL is set.)

SDA

D8h

00h

RESET

= 15V

TRIP

03h

03h resets V

SCL

2 3

5 6

0 1

2 3

5 6

0 1

2 3

5 6

0 1

2 3

5 6

00h

AND V2MON THRESHOLD RESET PROCEDURE

The X40620 is shipped with standard V

TRIP

and

TRIP

voltages. These values will not change over

normal operating and storage conditions. However, in
applications where the standard thresholds are not
exactly right, or if higher precision is needed in the
threshold value, the X40620 trip points may be
adjusted. The procedure is described below, and uses
the application of a high voltage control signal.

Setting the V

TRIP

Voltage

This procedure is used to set the V

TRIP

,V2

TRIP

to a

higher voltage value. For example, if the current V

TRIP

is 4.4V and the new V

TRIP

is 4.6V, this procedure will

directly make the change. If the new setting is to be
lower than the current setting, then it is necessary to
reset the trip point before setting the new value.

To set the new voltages, apply the desired V

TRIP

thresh-

old voltage to the V

pin, the V2

TRIP

voltage to the

V2MON pin, then tie the RESET pin to the programming
voltage V

. Then, write data 01h or 0Dh at address

00h to program V

TRIP

, V2

TRIP

respectively. The stop

bit following a valid write operation initiates the pro-
gramming sequence. Bring RESET

LOW to complete

the operation. Note: this operation also writes 01h or
0Dh to address 00h.

Resetting the V

TRIP

Voltage

This procedure is used to set the V

TRIP

, the V2

TRIP

a "native" voltage level. For example, if the current
V

TRIP

is 4.4V and the new V

TRIP

must be 4.0V, then

the V

TRIP

must be reset. When the threshold is reset,

the new level is something less than 1.7V. This proce-
dure must be used to set the voltage to a lower value.

To reset the new V

TRIP

, V2

TRIP

voltage, apply the

desired V

TRIP

or V2

TRIP

threshold voltage to the

or V2MON pin, respectively, and tie the RESET

pin to the programming voltage V

. Then write 03h or

0Fh to address 00h. The stop bit of a valid write opera-
tion initiates the programming sequence. Bring
RESET

LOW to complete the operation. Note: this

operation also writes 03h or 0Fh to address 00h of the
EEPROM array.

Figure 6. Sample V

TRIP

Reset Circuit

X40620

TRIP

Adj.

RESET

4.7K

SDA

SCL

µC

Adjust

Run

V2FAIL

TRIP

Adj.

X40620

Characteristics subject to change without notice.

7 of 17

Device Protocol

The X40620 supports a bidirectional bus oriented pro-
tocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device
as a receiver. The device controlling the transfer is a
master and the device being controlled is the slave.
The master will always initiate data transfers and pro-
vide the clock for both transmit and receive operations.
Therefore, the X40620 will be considered a slave in all
applications.

After each byte written to or read from the X40620, the
address pointer is incremented by 1. This allows the
user to read from the entire device after sending only a
single address. It also allows an entire page to be writ-
ten in one operation. An exception to this address
incrementation occurs during a read. After reading
address 1FFFh the device goes into an idle mode, so
additional reads return all "1s".

Clock and Data Conventions

Data states on the SDA line can change only during
SCL LOW. SDA changes during SCL HIGH are
reserved for indicating start and stop conditions. Refer
to Figure 7 and Figure 8.

Start Condition

All commands are preceeded by the start condition,
which is a HIGH to LOW transition of SDA when SCL
is HIGH. The X40620 continuously monitors the SDA
and SCL lines for the start condition and will not
respond to any command until this condition is met.

A start may be issued to terminate the input of a con-
trol byte or the input data to be written. This will reset
the device and leave it ready to begin a new read or
write command. A start bit generated while the part is
outputting data is accepted as a start as long as the
device is not outputting a 'zero'.

Stop Condition

All communications are be terminated by a stop condi-
tion. The stop condition is a LOW to HIGH transition of
SDA when SCL is HIGH. The stop condition is also
used to reset the device during a command or data
input sequence and will leave the device in the
standby power mode. As with starts, stops are recog-
nized while the device outputs data, as long as the
data output is not a `zero'.

Figure 7. Data Validity

Figure 8. Definition of Start and Stop Conditions

Acknowledge

Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device,
either master or slave, will release the bus after trans-
mitting eight bits. During the ninth clock cycle the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data.

The X40620 will respond with an acknowledge after
recognition of a start condition and its slave address. If
both the device and a write condition have been
selected, the X40620 will respond with an acknowledge
after the receipt of each subsequent eight-bit word.

SCL

SDA

Data

Change

Stable

SCL

SDA

Start Condition

Stop Condition

Table 1. X40620 Instruction Set

Notes: Illegal command codes will be disregarded. The part will respond with a "no-ACK" to the illegal byte and then return to the standby mode.

1st Byte after Start

1st Byte after Command

2nd Byte after Command

Command Description

1100 1000

High Address

Low address

Memory Array Read

1101 1000

High Address

Low address

Memory Array Write

X40620

Characteristics subject to change without notice.

8 of 17

PROGRAM OPERATIONS

Memory Array Programming

The memory array program mode requires issuing the 8-bit
Write command followed by the address and then the data
bytes transferred as illustrated in Figure 9. Up to 64 bytes

(or more) may be transferred. Sending more than 64
bytes results in data wrapping and over-writing previ-
ous data. After the last byte to be transferred is
acknowledged a stop condition is issued which starts
the nonvolatile write cycle.

Figure 9. Memory Array Programming

Command

SDA

A15

A14

A13

A12

A11

A10

Data 0

Data 63

Wait t

Data ACK

· · ·

Polling

Write

ACK Polling

Once a stop condition is issued to indicate the end of
the host's write sequence, the X40620 initiates the
internal nonvolatile write cycle. In order to take advan-
tage of the typical 5ms write cycle, ACK polling can
begin immediately. This involves issuing the start con-
dition followed by the new command code of 8 bits (1st
byte of the protocol.) If the X40620 is still busy with the
nonvolatile write operation, it will issue a "no-ACK" in
response. If the nonvolatile write operation has com-
pleted, an "ACK" will be returned and the host can then
proceed with the rest of the protocol.

Data ACK Polling Sequence

ACK

Returned

Issue New

Command Code

Write Sequence

Completed

Enter Ack Polling

Issue Start

YES

Proceed

X40620

Characteristics subject to change without notice.

9 of 17

Figure 10. Acknowledge Polling

8th CLK

`ACK'

CLK

8th

CLK

`ACK'

CLK

`ACK'

Start

Condition

8th Bit

ACK or

no ACK

SCL

SDA

MEMORY READ OPERATIONS

Memory read operations are initiated in the same
manner as write operations but with a different com-
mand code.

Random Read

The master issues the start condition, then a Read
instruction, then issues the word address. Once the
first byte has been read, another start can be issued
followed by a new 8-bit address. See Figure 11.

Sequential Read

The host can read sequentially within the memory
array after receiving the Read Command and an
address within the address space. The data output is

sequential, with the data from address n followed by
the data from n+1. The address counter for read oper-
ations increments all address bits, allowing the entire
memory array contents to be serially read during one
operation. At the end of the address space (address
1FFFh) the device goes into an idle state and a new
read sequence must be initiated to continue reading at
another address. Refer to Figure 12 for the address,
acknowledge and data transfer sequence. An acknowl-
edge must follow each 8-bit data transfer. After the last
bit has been read, the host sends a stop condition with
or without a preceding acknowledge.

Figure 11. Random Read

Figure 12. Sequential Read

A7 A6 A5 A4 A3 A2 A1 A0

Data 0

Command

SDA

A15

A14

A13

A12

A11

A10

Data 0

Read

Data X

Command

SDA

A15

A14

A13

A12

A11

A10

Data 0

Read

X40620

Characteristics subject to change without notice.

10 of 17

ABSOLUTE MAXIMUM RATINGS

Temperature under bias ................... 65°c to +135°C
Storage temperature ........................65°C to +150°C
Voltage on any pin with respect to V

..... 1V to +7V

D.C. output current ............................................... 5mA
Lead temperature (soldering, 10 seconds).........300°C

COMMENT

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those

listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating con-
ditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

Temp

Min.

Max.

Commercial

0°C

+70°C

Extended

20°C

+85°C

Device

Supply Voltage Limits

X40620

2.5V to 3.7V

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)

CAPACITANCE (T

= +25°C, F = 1MHZ, V

= 3V)

Notes: (1) Must perform a stop command after a read command prior to measurement

(2) V

min. and V

max. are for reference only and are not tested.

(3) This parameter is periodically sampled and not 100% tested.

Symbol

Parameter

Limits

Units

Test Conditions

Min.

Max.

CC1

Supply Current (Read)

SCL

= 1MHz,

RESET = V2FAIL = V

w/ pull up resistor

2MON

= V

CC2

(3)

Supply Current (Write)

SCL

= 1MHz,

RESET = V2FAIL = V

w/ pull up resistor

RST = V

SB1

(1)

Supply Current (Standby)

µA

= V

x 0.1, V

= V

x 0.9

SCL

= 1MHz, f

SDA

= 400 KHz

SB2

(1)

Supply Current (Standby)

µA

SDA

= V

SCL

= V

2MON

= V

Other = GND or V

0.3V

Input Leakage Current

µA

= V

to V

Output Leakage Current

µA

OUT

= V

to V

IL1

(2)

Input LOW Voltage

0.5

x 0.3

= 3.0V

IH1

(2)

Input HIGH Voltage

x 0.7 V

+ 0.5

= 3.0V

IL2

(2)

Input LOW Voltage

0.5

x 0.1

= 3.0V

IH2

(2)

Input HIGH Voltage

x 0.9 V

+ 0.5

= 3.0V

Output LOW Voltage

0.4

= 3mA

Symbol

Test

Max.

Units

Conditions

OUT

(3)

Output Capacitance (SDA)

I/O

= 0V

(3)

Input Capacitance (WP, SCL, V

2MON

)

= 0V

X40620

Characteristics subject to change without notice.

11 of 17

EQUIVALENT A.C. LOAD CIRCUIT

A.C. TEST CONDITIONS

1.3K

Output

100pF

Input pulse levels

x 0.1 to V

x 0.9

Input rise and fall times

10ns

Input and output timing level

x 0.5

Output load

100pF

AC CHARACTERISTICS

AC Specifications (Over the recommended operating conditions)

RESET AC SPECIFICATIONS

Nonvolatile Write Cycle Timing

Notes: (1) t

is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle.

It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.

Symbol Parameter

Min.

Typ.

(1)

Max.

Units

SCL

SCL Clock Frequency

1000

KHz

Pulse width of spikes which must be suppressed by the input filter

SCL LOW to SDA Data Out Valid

0.05

0.55

µs

BUF

Time the bus must be free before a new transmit can start

0.5

µs

LOW

Clock LOW Time

0.6

µs

HIGH

Clock HIGH Time

0.4

µs

SU:STA

Start Condition Setup Time

0.25

µs

HD:STA

Start Condition Hold Time

0.25

µs

SU:DAT

Data In Setup Time

100

HD:DAT

Data In Hold Time

µs

SU:STO

Stop Condition Setup Time

0.25

µs

Data Output Hold Time

100

SDA and SCL Rise Time (10% to 90% of V

)

100

SDA and SCL Fall Time

100

Symbol Parameter

Min.

Typ.

(1)

Max.

Units

(1)

Write Cycle Time

X40620

Characteristics subject to change without notice.

12 of 17

TIMING DIAGRAMS

Bus Timing

Write Cycle Timing

GUIDELINES FOR CALCULATING TYPICAL VALUES OF BUS PULL UP RESISTORS

SU:STO

HIGH

SU:STA

HD:STA

HD:DAT

SU:DAT

SCL

SDA IN

SDA OUT

LOW

BUF

SCL

SDA

8th Bit of Last Byte

ACK

Stop

Condition

Start

Condition

Bus capacitance in pF

Pull Up Resistance in K

RMIN

PMAX

For V

= 0.9V

MIN

CCMAX

0.4

OLMIN

-----------------------------------------

1100

Vcc 1

RMAX

PMAX

BUS

---------------------------------------

PMAX

2.3 C

BUS

(

)

-------------------------------

RMAX

= maximum allowable SDA rise time

100ns Max Rise

Time

X40620

Characteristics subject to change without notice.

13 of 17

POWER-UP AND POWER-DOWN TIMING

RESET Output Timing

V2FAIL Output Timing

Notes: (5) This parameter is periodically sampled and not 100% tested.

(6) Typical values not tested.

Symbol

Parameter

Min.

Typ.

Max.

Units

TRIP

RESET Trip Point Voltage

2.4

3.5

2TRIP

V2FAIL Trip Point Voltage

1.7

3.5

TRIP

Hysteresis (HIGH to LOW vs. LOW to HIGH V

TRIP

voltage)

2TA

2TRIP

Hysteresis (HIGH to LOW vs. LOW to HIGH V

TRIP

voltage)

PURST

Power-up Reset Timeout

150

225

DVC

(5)

Detect V

Low Voltage to Reset Output (V

= 2.3V)

DVB

(5)

Detect V

2MON

Low Voltage to Reset Output (V

= 2.5-3.7V)

100

(5)

Fall Time

100

(5)

Rise Time

100

(5)

2MON

Fall Time

500

(5)

2MON

Rise Time

500

RVALID

Reset Valid V

PURST

DVC

RESET

0 Volts

VTRIP

PURST

V2MON

V2FAIL

DVB

0 Volts

2TRIP

X40620

Characteristics subject to change without notice.

17 of 17

LIMITED WARRANTY

Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express,
statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes
no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and
without notice.

Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.

TRADEMARK DISCLAIMER:

Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.

U.S. PATENTS

Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691; 5,161,137;
5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.

LIFE RELATED POLICY

In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and
correction, redundancy and back-up features to prevent such an occurence.

Xicor's products are not authorized for use in critical components in life support devices or systems.

Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.

A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.

Part Mark Convention

8-Lead TSSOP

EYWW

XXXX XX

4062 AR =

TRIP

2TRIP

Temp

4062 AS =
4062 AT =
4062 AU =
4062 AV =
4062 AW =

2.6
2.6
1.7
1.7
2.3
2.3

0 to 70°C

-20 to 85°C

0 to 70°C

-20 to 85°C

0 to 70°C

-20 to 85°C

3.1
3.1
3.1
3.1
2.9
2.9

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: X40620

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: X40620