Document Outline
- WM8950
- ADC with Microphone Input and Programmable Digital Filters
- DESCRIPTION
- FEATURES
- APPLICATIONS
- TABLE OF CONTENTS
- PIN CONFIGURATION
- ORDERING INFORMATION
- PIN DESCRIPTION
- ABSOLUTE MAXIMUM RATINGS
- RECOMMENDED OPERATING CONDITIONS
- ELECTRICAL CHARACTERISTICS
- SIGNAL TIMING REQUIREMENTS
- SYSTEM CLOCK TIMING
- AUDIO INTERFACE TIMING MASTER MODE
- AUDIO INTERFACE TIMING SLAVE MODE
- CONTROL INTERFACE TIMING 3-WIRE MODE
- CONTROL INTERFACE TIMING 2-WIRE MODE
- DEVICE DESCRIPTION
- INTRODUCTION
- INPUT SIGNAL PATH
- ANALOGUE TO DIGITAL CONVERTER (ADC)
- INPUT LIMITER / AUTOMATIC LEVEL CONTROL (ALC)
- DIGITAL AUDIO INTERFACES
- AUDIO SAMPLE RATES
- MASTER CLOCK AND PHASE LOCKED LOOP (PLL)
- GENERAL PURPOSE INPUT/OUTPUT
- CONTROL INTERFACE
- RESETTING THE CHIP
- POWER SUPPLIES
- POWER MANAGEMENT
- REGISTER MAP
- DIGITAL FILTER CHARACTERISTICS
- TERMINOLOGY
- ADC FILTER RESPONSES
- DE-EMPHASIS FILTER RESPONSES
- HIGHPASS FILTER
- 5-BAND EQUALISER
- APPLICATIONS INFORMATION
- RECOMMENDED EXTERNAL COMPONENTS
- PACKAGE DIAGRAM
- IMPORTANT NOTICE
- ADDRESS
w
WM8950
ADC with Microphone Input and Programmable Digital Filters
WOLFSON MICROELECTRONICS plc
To receive regular email updates, sign up
at
http://www.wolfsonmicro.com/enews/
Preliminary Technical Data, June 2005, Rev 2.1
Copyright
2005 Wolfson Microelectronics plc
DESCRIPTION
The WM8950 is a low power, high quality mono ADC designed
for portable applications such as Digital Still Camera, Digital
Voice Recorder or games console accessories.
The device integrates support for a differential or single ended
mic. External component requirements are reduced as no
separate microphone amplifiers are required.
Advanced Sigma Delta Converters are used along with digital
decimation filters to give high quality audio at sample rates
from 8 to 48ks/s. Additional digital filtering options are
available, to cater for application filtering such as wind noise
reduction, noise rejection, plus an advanced mixed signal ALC
function with noise gate is provided.
An on-chip PLL is provided to generate the required Master
Clock from an external reference clock. The PLL clock can
also be output if required elsewhere in the system.
The WM8950 operates at supply voltages from 2.5 to 3.6V,
although the digital supplies can operate at voltages down to
1.71V to save power. Different sections of the chip can also be
powered down under software control by way of the selectable
two or three wire control interface.
WM8950 is supplied in a very small 4x4mm QFN package,
offering high levels of functionality in minimum board area,
with high thermal performance.
FEATURES
Mono ADC:
Audio sample rates:8, 11.025, 16, 22.05, 24, 32, 44.1, 48kHz
SNR 95dB, THD -85dB (`A'-weighted @ 8 48ks/s)
Multiple auxiliary analog inputs
Mic Preamps:
Differential or single end Microphone Interface
- Programmable preamp gain
- Psuedo differential inputs with common mode rejection
- Programmable ALC / Noise Gate in ADC path
Low-noise bias supplied for electret microphones
OTHER FEATURES
5 band EQ
Programmable High Pass Filter (wind noise reduction)
Fully Programmable IIR Filter (notch filter)
On-chip PLL
Low power, low voltage
- 2.5V to 3.6V (digital: 1.71V to 3.6V)
- power consumption TBD all-on 48ks/s mode
4x4x0.9mm 24 pin QFN package
APPLICATIONS
Digital Still Camera
General Purpose low power audio ADC
Games console accessories
Voice recorders
WM8950
Preliminary Technical Data
w
PTD Rev 2.1 June 2005
2
TABLE OF CONTENTS
DESCRIPTION .......................................................................................................1
FEATURES.............................................................................................................1
APPLICATIONS .....................................................................................................1
TABLE OF CONTENTS .........................................................................................2
PIN CONFIGURATION...........................................................................................3
ORDERING INFORMATION ..................................................................................3
RECOMMENDED OPERATING CONDITIONS .....................................................5
ELECTRICAL CHARACTERISTICS ......................................................................6
TERMINOLOGY ............................................................................................................ 7
SIGNAL TIMING REQUIREMENTS .......................................................................8
SYSTEM CLOCK TIMING ............................................................................................. 8
AUDIO INTERFACE TIMING MASTER MODE .......................................................... 8
AUDIO INTERFACE TIMING SLAVE MODE.............................................................. 9
CONTROL INTERFACE TIMING 3-WIRE MODE .................................................... 10
CONTROL INTERFACE TIMING 2-WIRE MODE .................................................... 11
DEVICE DESCRIPTION .......................................................................................12
INTRODUCTION ......................................................................................................... 12
INPUT SIGNAL PATH ................................................................................................. 13
ANALOGUE TO DIGITAL CONVERTER (ADC).......................................................... 18
INPUT LIMITER / AUTOMATIC LEVEL CONTROL (ALC) .......................................... 21
DIGITAL AUDIO INTERFACES................................................................................... 29
AUDIO SAMPLE RATES ............................................................................................. 35
MASTER CLOCK AND PHASE LOCKED LOOP (PLL) ............................................... 35
GENERAL PURPOSE INPUT/OUTPUT...................................................................... 37
CONTROL INTERFACE.............................................................................................. 38
RESETTING THE CHIP........................................................................................39
POWER SUPPLIES .................................................................................................... 39
POWER MANAGEMENT ............................................................................................ 39
REGISTER MAP...................................................................................................41
DIGITAL FILTER CHARACTERISTICS ...............................................................42
TERMINOLOGY .......................................................................................................... 42
ADC FILTER RESPONSES .................................................................................43
DE-EMPHASIS FILTER RESPONSES........................................................................ 44
HIGHPASS FILTER..............................................................................................45
5-BAND EQUALISER .................................................................................................. 46
APPLICATIONS INFORMATION .........................................................................50
RECOMMENDED EXTERNAL COMPONENTS .......................................................... 50
PACKAGE DIAGRAM ..........................................................................................51
IMPORTANT NOTICE ..........................................................................................52
ADDRESS ................................................................................................................... 52
Preliminary Technical Data
WM8950
w
PTD Rev 2.1 June 2005
3
PIN CONFIGURATION
TOP VIEW
ORDERING INFORMATION
ORDER CODE
TEMPERATURE
RANGE
PACKAGE
MOISTURE SENSITIVITY
LEVEL
PACKAGE BODY
TEMPERATURE
WM8950GEFL/V
-25
C to +85C
24-pin QFN (4x4x0.9mm)
(lead free)
MSL3
260
o
C
WM8950GEFL/RV
-25
C to +85C
24-pin QFN (4x4x0.9mm)
(lead free, tape and reel)
MSL3
260
o
C
Note:
Reel Quantity = 3,500
WM8950
Preliminary Technical Data
w
PTD Rev 2.1 June 2005
4
PIN DESCRIPTION
PIN NO
NAME
TYPE
DESCRIPTION
1
MICBIAS
Analogue Output
Microphone bias
2
AVDD
Supply
Analogue supply (feeds ADC)
3
AGND
Supply
Analogue ground (feeds ADC)
4
DCVDD
Supply
Digital core supply
5
DBVDD
Supply
Digital buffer (input/output) supply
6
DGND
Supply
Digital ground
7
ADCDAT
Digital Output
ADC digital audio data output
8
TP
Test Pin
Connect to ground
9
FRAME
Digital Input / Output
ADC sample rate clock or frame synch
10
BCLK
Digital Input / Output
Digital audio bit clock
11
MCLK
Digital Input
Master clock input
12
CSB/GPIO
Digital Input / Output
3-Wire MPU chip select or general purpose input/output pin.
13
SCLK
Digital Input
3-Wire MPU clock Input / 2-Wire MPU Clock Input
14
SDIN
Digital Input / Output
3-Wire MPU data Input / 2-Wire MPU Data Input
15
MODE
Digital Input
Control interface mode selection pin.
16
DNC
Do not connect
Leave this pin floating
17
DNC
Do not connect
Leave this pin floating
18
AGND2
Supply
Analogue ground
19
DNC
Do not connect
Leave this pin floating
20
AVDD2
Supply
Analogue supply
21
AUX
Analogue Input
Auxiliary analogue input
22
VMID
Reference
Decoupling for midrail reference voltage
23
MICN
Analogue Input
Microphone negative input
24
MICP
Analogue Input
Microphone positive input (common mode)
Note:
It is recommended that the QFN ground paddle should be connected to analogue ground on the application PCB.
Preliminary Technical Data
WM8950
w
PTD Rev 2.1 June 2005
5
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously
operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given
under Electrical Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to
damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this
device.
Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage
conditions prior to surface mount assembly. These levels are:
MSL1 = unlimited floor life at <30
C / 85% Relative Humidity. Not normally stored in moisture barrier bag.
MSL2 = out of bag storage for 1 year at <30
C / 60% Relative Humidity. Supplied in moisture barrier bag.
MSL3 = out of bag storage for 168 hours at <30
C / 60% Relative Humidity. Supplied in moisture barrier bag.
The Moisture Sensitivity Level for each package type is specified in Ordering Information.
CONDITION
MIN
MAX
DBVDD, DCVDD, AVDD, AVDD2 supply voltages
-0.3V
+4.2
Voltage range digital inputs
DGND -0.3V
DVDD +0.3V
Voltage range analogue inputs
AGND -0.3V
AVDD +0.3V
Operating temperature range, T
A
-25
C
+85
C
Storage temperature prior to soldering
30
C max / 85% RH max
Storage temperature after soldering
-65
C
+150
C
Notes
1.
Analogue and digital grounds must always be within 0.3V of each other.
2.
All digital and analogue supplies are completely independent from each other.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Digital supply range (Core)
DCVDD
1.71
1
3.6
V
Digital supply range (Buffer)
DBVDD
1.71
3.6
V
Analogue supplies range
AVDD, AVDD2
2.5
3.6
V
Ground
DGND, AGND, AGND2
0
V
Notes
1.
When using PLL, DCVDD must be 1.9V or higher.