Document Outline
- WM8727
- DESCRIPTION
- FEATURES
- APPLICATIONS
- BLOCK DIAGRAM
- TABLE OF CONTENTS
- PIN CONFIGURATION
- ORDERING INFORMATION
- PIN DESCRIPTION
- ABSOLUTE MAXIMUM RATINGS
- DC ELECTRICAL CHARACTERISTICS
- ELECTRICAL CHARACTERISTICS
- MASTER CLOCK TIMING
- DIGITAL AUDIO INTERFACE
- DEVICE DESCRIPTION
- GENERAL INTRODUCTION
- DAC CIRCUIT DESCRIPTION
- CLOCKING SCHEMES
- DIGITAL AUDIO INTERFACE
- AUDIO DATA SAMPLING RATES
- DIGITAL FILTER CHARACTERISTICS
- TYPICAL PERFORMANCE
- APPLICATIONS INFORMATION
- RECOMMENDED EXTERNAL COMPONENTS
- RECOMMENDED EXTERNAL COMPONENTS VALUES
- RECOMMENDED ANALOGUE LOW PASS FILTER (OPTIONAL)
- PCB LAYOUT RECOMMENDATIONS
- PACKAGE DRAWING
- IMPORTANT NOTICE
- ADDRESS:
w
WM8727
24-bit 192kHz Stereo DAC
WOLFSON MICROELECTRONICS plc
www.wolfsonmicro.com
Production Data, April 2004, Rev 4.1
Copyright
2004 Wolfson Microelectronics plc
DESCRIPTION
The WM8727 is a high performance stereo DAC designed
for audio applications such as DVD, home theatre systems,
and digital TV. The WM8727 supports data input word
lengths from 16 to 24-bits and sampling rates up to 192kHz.
The WM8727 consists of a serial interface port, digital
interpolation filters, multi-bit sigma delta modulators and
stereo DAC in a very small 8-pin SOIC package.
The WM8727 supports a 16-24-bit I
2
S digital audio
interface.
The WM8727 is an ideal device to interface to AC-3
,
DTS
, and MPEG audio decoders for surround sound
applications, or for use in DVD players, including supporting
the implementation of 2 channels at 192kHz for high-end
DVD-Audio applications.
FEATURES
Stereo DAC
Audio Performance
-
98dB SNR (`A' weighted @ 48kHz) DAC
-
-84dB THD
DAC Sampling Frequency: 8kHz 192kHz
Audio Data Interface Format
-
16-24-Bit I
2
S
2.7V 5.5V Supply Operation
8-pin SOIC Package
Exceeds Dolby Class A Performance Requirements
APPLICATIONS
DVD Players
Digital TV
Digital Set Top Box
BLOCK DIAGRAM
SERIAL
INTERFACE
MUTE
BCKIN
VOUTL
VOUTR
SIGMA
DELTA
MODULATOR
LRCIN
DIN
MUTE
SIGMA
DELTA
MODULATOR
DIGITAL FILTERS
MCLK
LOW
PASS
FILTER
LOW
PASS
FILTER
RIGHT
DAC
LEFT
DAC
GND
VDD
W
WM8727
WM8727
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TABLE OF CONTENTS
DESCRIPTION ............................................................................................................1
FEATURES..................................................................................................................1
APPLICATIONS ..........................................................................................................1
BLOCK DIAGRAM ......................................................................................................1
TABLE OF CONTENTS ..............................................................................................2
PIN CONFIGURATION................................................................................................3
ORDERING INFORMATION .......................................................................................3
PIN DESCRIPTION .....................................................................................................3
ABSOLUTE MAXIMUM RATINGS ..............................................................................4
DC ELECTRICAL CHARACTERISTICS .....................................................................4
ELECTRICAL CHARACTERISTICS ...........................................................................5
TERMINOLOGY................................................................................................................. 6
MASTER CLOCK TIMING .................................................................................................. 6
DIGITAL AUDIO INTERFACE ............................................................................................ 6
DEVICE DESCRIPTION ..............................................................................................8
GENERAL INTRODUCTION .............................................................................................. 8
DAC CIRCUIT DESCRIPTION ........................................................................................... 8
CLOCKING SCHEMES ...................................................................................................... 9
DIGITAL AUDIO INTERFACE ............................................................................................ 9
AUDIO DATA SAMPLING RATES.....................................................................................10
DIGITAL FILTER CHARACTERISTICS ....................................................................11
DAC FILTER RESPONSES...............................................................................................11
TYPICAL PERFORMANCE.......................................................................................12
APPLICATIONS INFORMATION ..............................................................................13
RECOMMENDED EXTERNAL COMPONENTS ................................................................13
RECOMMENDED EXTERNAL COMPONENTS VALUES .................................................13
RECOMMENDED ANALOGUE LOW PASS FILTER (OPTIONAL) ...................................14
PCB LAYOUT RECOMMENDATIONS ..............................................................................14
PACKAGE DRAWING...............................................................................................15
IMPORTANT NOTICE ...............................................................................................16
ADDRESS: ........................................................................................................................16
WM8727
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PIN CONFIGURATION
8
7
6
5
WM8727
1
2
3
4
VDD
VOUTR
VOUTL
GND
MCLK
LRCIN
DIN
BCKIN
ORDERING INFORMATION
DEVICE
TEMPERATURE
RANGE
PACKAGE
MOISTURE
SENSITIVITY LEVEL
PEAK SOLDERING
TEMPERATURE
WM8727ED
-25 to +85
o
C
8-pin SOIC
MSL1
240
o
C
WM8727ED/R
-25 to +85
o
C
8-pin SOIC
(tape and reel)
MSL1
240
o
C
WM8727GED/V
-25 to +85
o
C
8-pin SOIC
(lead free)
MSL2
260
o
C
WM8727GED/RV
-25 to +85
o
C
8-pin SOIC
(lead free, tape and reel)
MSL2
260
o
C
Note:
Reel Quantity = 3,000
PIN DESCRIPTION
PIN
NAME
TYPE
DESCRIPTION
1
DIN
Digital input
Serial audio data input
2
BCKIN
Digital input
Bit clock input
3
LRCIN
Digital input
Sample rate clock input
4
MCLK
Digital input
System clock input
5
VOUTR
Analogue output
Right channel DAC output
6
GND
Supply
Analogue ground supply
7
VDD
Supply
Positive supply
8
VOUTL
Analogue output
Left channel DAC output
Note:
Digital input pins have Schmitt trigger input buffers.
WM8727
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ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at
or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage
conditions prior to surface mount assembly. These levels are:
MSL1 = unlimited floor life at <30
C / 85% Relative Humidity. Not normally stored in moisture barrier bag.
MSL2 = out of bag storage for 1 year at <30
C / 60% Relative Humidity. Supplied in moisture barrier bag.
MSL3 = out of bag storage for 168 hours at <30
C / 60% Relative Humidity. Supplied in moisture barrier bag.
CONDITION
MIN
MAX
Supply voltage
-0.3V
+7V
Voltage range digital inputs
GND -0.3V
VDD +0.3V
Master Clock Frequency
50MHz
Operating temperature range, T
A
-25
C
+85
C
Storage temperature prior to soldering
30
C max / 85% RH max
Storage temperature after soldering
-65
C
+150
C
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Supply range
VDD
2.7
5.5
V
Ground
GND
0
V
Supply current
VDD = 5V
27
mA
Supply current
VDD = 3.3V
23
mA
Power down current (note 3)
VDD = 3.3V
0.5
mA
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ELECTRICAL CHARACTERISTICS
Test Conditions
VDD = 5V, GND = 0V, T
A
= +25
o
C, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Digital Logic Levels (TTL Levels)
Input LOW level
V
IL
0.8
V
Input HIGH level
V
IH
2
V
Output LOW
V
OL
I
OL
= 2mA
0.10 x VDD
V
Output HIGH
V
OH
I
OH
= 2mA
0.9 x VDD
V
DAC Output (Load
= 10k
50pF)
0dBFs Full scale output voltage
At DAC outputs
1.2 x
VDD/5
V
RMS
SNR (Note 1,2)
A-weighted,
@ fs = 48kHz
98
dB
SNR (Note 1,2)
A-weighted
@ fs = 96kHz
95
dB
SNR (Note 1,2)
A-weighted
@ fs = 192kHz
92
dB
SNR (Note 1,2)
A-weighted,
@ fs = 48kHz
VDD = 3.3V
95
dB
SNR (Note 1,2)
A-weighted
@ fs = 96kHz
VDD = 3.3V
95
dB
SNR (Note 1,2)
Non `A' weighted @ fs
= 48kHz
92
dB
THD
1kHz, 0dBFs
-84
dB
Dynamic range (Note 2)
1kHz, THD+N @
-60dBFs
98
dB
Analogue Output Levels
Load = 10k
, 0dBFS
1.2
V
RMS
Output level
Load = 10k
, 0dBFS,
(VDD = 3.3V)
0.79
V
RMS
Gain mismatch
channel-to-channel
1
%FSR
To midrail or a.c.
coupled
1
k
Minimum resistance load
To midrail or a.c.
coupled
(VDD = 3.3V)
1
k
Maximum capacitance load
5V or 3.3V
100
pF
Output d.c. level
VDD/2
V
Power On Reset (POR)
POR threshold
1.8
V
Notes:
1.
Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured `A' weighted
over a 20Hz to 20kHz bandwidth.
2.
All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use such a
filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical
Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification
values.
3.
Power down occurs 1.5
s after MCLK stops.
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TERMINOLOGY
1.
Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output with no
signal applied. (No Auto-zero or Automute function is employed in achieving these results).
2.
Dynamic range (dB) - DNR is a measure of the difference between the highest and lowest portions of a signal. Normally a
THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g.
THD+N @ -60dB= -32dB, DR= 92dB).
3.
THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal.
4.
Stop band attenuation (dB) - Is the degree to which the frequency spectrum is attenuated (outside audio band).
5.
Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from the
other. Normally measured by sending a full scale signal down one channel and measuring the other.
MASTER CLOCK TIMING
MCLK
t
MCLKL
t
MCLKH
t
MCLKY
Figure 1 Master Clock Timing Requirements
Test Conditions
VDD = 5V, GND = 0V, T
A
= +25
o
C, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
System Clock Timing Information
MCLK Master clock pulse width high
t
MCLKH
8
ns
MCLK Master clock pulse width low
t
MCLKL
8
ns
MCLK Master clock cycle time
t
MCLKY
20
ns
MCLK Duty cycle
40:60
60:40
Time from MCLK stopping to power
down.
1.5
12
s
DIGITAL AUDIO INTERFACE
BCKIN
LRCIN
t
BCH
t
BCL
t
BCY
DIN
t
LRSU
t
DS
t
LRH
t
DH
Figure 2 Digital Audio Data Timing
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Test Conditions
VDD = 5V, GND = 0V, T
A
= +25
o
C, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCKIN cycle time
t
BCY
40
ns
BCKIN pulse width high
t
BCH
16
ns
BCKIN pulse width low
t
BCL
16
ns
LRCIN set-up time to
BCKIN rising edge
t
LRSU
8
ns
LRCIN hold time from
BCKIN rising edge
t
LRH
8
ns
DIN set-up time to BCKIN
rising edge
t
DS
8
ns
DIN hold time from BCKIN
rising edge
t
DH
8
ns
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DEVICE DESCRIPTION
GENERAL INTRODUCTION
The WM8727 is a high performance DAC designed for digital consumer audio applications. The
range of features make it ideally suited for use in DVD players, AV receivers and other
consumer audio equipment.
The WM8727 is a complete 2-channel stereo audio digital-to-analogue converter, including
digital interpolation filter, multi-bit sigma delta with dither, and switched capacitor multi-bit
stereo DAC and output smoothing filters. It is fully compatible and an ideal partner for a range
of industry standard microprocessors, controllers and DSPs. A novel multi bit sigma-delta DAC
design is used, utilising a 128x oversampling rate, to optimise signal to noise performance and
offer increased clock jitter tolerance. (In `high-rate' operation, the oversampling ratio is 64x for
system clocks of 128fs or 192fs)
Operation using master clocks of 256fs, 384fs, 512fs or 768fs is provided, selection between
clock rates being automatically controlled. Sample rates (fs) from less than 8ks/s to 96ks/s are
allowed, provided the appropriate system clock is input. Support is also provided for up to
192ks/s using a master clock of 128fs or 192fs.
The audio data interface supports 16-24-bit I
2
S (Philips left justified, one bit delayed) interface
format. A DSP interface is also supported, enhancing the interface options for the user.
A single 2.7-5.5V supply may be used, the output amplitude scaling with absolute supply level.
Low supply voltage operation and low current consumption combined with the low pin count
small package make the WM8727 attractive for many consumer applications.
The device is packaged in a small 8-pin SOIC.
DAC CIRCUIT DESCRIPTION
The WM8727 DAC is designed to allow playback of 24-bit PCM audio or similar data with high
resolution and low noise and distortion. Sample rates up to 192ks/s may be used, with much
lower sample rates acceptable provided that the ratio of sample rate (LRCIN) to system clock
(MCLK) is maintained at one of the required rates.
The two DACs on the WM8727 are implemented using sigma-delta oversampled conversion
techniques. These require that the PCM samples are digitally filtered and interpolated to generate
a set of samples at a much higher rate than the up to 192ks/s input rate. This sample stream is
then digitally modulated to generate a digital pulse stream that is then converted to analogue
signals in a switched capacitor DAC. The advantage of this technique is that the DAC is
linearised using noise shaping techniques, allowing the 24-bit resolution to be met using non-
critical analogue components. A further advantage is that the high sample rate at the DAC output
means that smoothing filters on the output of the DAC need only have fairly crude characteristics
in order to remove the characteristic steps, or images, on the output of the DAC. To ensure that
generation of tones characteristic to sigma-delta convertors is not a problem, dithering is used in
the digital modulator and a higher order modulator is used. The multi-bit switched capacitor
technique used in the DAC reduces sensitivity to clock jitter, and dramatically reduces out of
band noise compared to switched current or single bit techniques used in other implementations.
The outputs of the 2 DACs are buffered out of the device by buffer amplifiers. These amplifiers
will source load currents of several mA and sink current up to 1.5mA allowing significant loads
to be driven. The output source is active and the sink is Class A, i.e. fixed value, so greater
loads might be driven if an external `pull-down' resistor is connected at the output.
Typically an external low pass filter circuit will be used to remove residual out of band noise
characteristic of delta sigma converters. However, the advanced multi-bit DAC used in
WM8727 produces far less out of band noise than single bit traditional sigma delta DACs, and
so in many applications this filter may be removed, or replaced with a simple RC pole.
WM8727
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CLOCKING SCHEMES
In a typical digital audio system there is only one central clock source producing a reference
clock to which all audio data processing is synchronised. This clock is often referred to as the
audio system's Master Clock. The external master clock can be applied directly through the
MCLK input pin with no configuration necessary for sample rate selection.
Note that on the WM8727, MCLK is used to derive clocks for the DAC path. The DAC path
consists of DAC sampling clock, DAC digital filter clock and DAC digital audio interface timing.
In a system where there are a number of possible sources for the reference clock it is
recommended that the clock source with the lowest jitter be used to optimise the performance
of the DAC.
The device can be powered down by stopping MCLK. In this state the power consumption is
substantially reduced.
DIGITAL AUDIO INTERFACE
Audio data is applied to the internal DAC filters via the Digital Audio Interface. The WM8727
supports the popular I
2
S audio interface format. The WM8727 supports word lengths of 16-24
bits (MSB first). The word length may be any value up to 24-bits. (If a word length shorter than
24-bits is used, the unused bits will be padded with zeros).
`Packed' mode (i.e. only 32 or 48 clocks per LRCIN period) operation is also supported. If a
`packed' format of 16-bit word length is applied (16 BCKINS per LRCIN half period), the device
auto-detects this mode and switches to 16-bit data length.
The digital audio interface receives data on the DIN input. Audio Data is time multiplexed with
LRCIN indicating whether the left or right channel is present. LRCIN is also used as a timing
reference to indicate the beginning or end of the data words.
The minimum number of BCKINs per LRCIN period is 2 times the selected word length. LRCIN
must be high for a minimum of word length BCKINs and low for a minimum of word length
BCKINs. Any mark to space ratio on LRCIN is acceptable provided the above requirements are
met.
In the I
2
S mode, the MSB is sampled on the second rising edge of BCKIN following a LRCIN
transition. LRCIN is low during the left samples and high during the right samples.
LEFT CHANNEL
RIGHT CHANNEL
LRCIN
BCKIN
DIN
1/fs
n
3
2
1
n-2 n-1
LSB
MSB
n
3
2
1
n-2 n-1
LSB
MSB
1 BCKIN
1 BCKIN
Figure 3 I
2
S Mode Timing Diagram
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AUDIO DATA SAMPLING RATES
The master clock for WM8727 supports audio sampling rates from 128fs to 768fs, where fs is
the audio sampling frequency (LRCIN) typically 32kHz, 44.1kHz, 48kHz, 96kHz or 192kHz. The
master clock is used to operate the digital filters and the noise shaping circuits.
The WM8727 has a master clock detection circuit that automatically determines the relation
between the master clock frequency and the sampling rate (to within +/- 8 master clocks). If
there is a greater than 8 clocks error, the interface shuts down the DAC and mutes the output.
The master clock should be synchronised with LRCIN, although the WM8727 is tolerant of
phase differences or jitter on this clock.
MASTER CLOCK FREQUENCY (MHZ) (MCLK)
SAMPLING
RATE
(LRCIN)
128fs
192fs
256fs
384fs
512fs
768fs
32kHz
4.096
6.144
8.192
12.288
16.384
24.576
44.1kHz
5.6448
8.467
11.2896
16.9344
22.5792
33.8688
48kHz
6.144
9.216
12.288
18.432
24.576
36.864
96kHz
12.288
18.432
24.576
36.864
Unavailable Unavailable
192kHz
24.576
36.864
Unavailable Unavailable Unavailable Unavailable
Table 1 Master Clock Frequencies Versus Sampling Rate
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DIGITAL FILTER CHARACTERISTICS
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Passband Edge
-3dB
0.487fs
Passband Ripple
f < 0.444fs
0.05
dB
Stopband Attenuation
f > 0.555fs
-60
dB
Table 2 Digital Filter Characteristics
DAC FILTER RESPONSES
-120
-100
-80
-60
-40
-20
0
0
0.5
1
1.5
2
2.5
3
Response (dB)
Frequency (Fs)
Figure 4 DAC Digital Filter Frequency Response
-44.1, 48 and 96kHz
-0.2
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
0.2
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Response (dB)
Frequency (Fs)
Figure 5 DAC Digital Filter Ripple -44.1, 48 and 96kHz
-80
-60
-40
-20
0
0
0.2
0.4
0.6
0.8
1
Response (dB)
Frequency (Fs)
Figure 6 DAC Digital Filter Frequency Response 192kHz
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Response (dB)
Frequency (Fs)
Figure 7 DAC Digital Filter Ripple 192kHz
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TYPICAL PERFORMANCE
-120
-65
-115
-110
-105
-100
-95
-90
-85
-80
-75
-70
d
B
r
B
-160
+0
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
dBFS
Figure 8 WM8727 Functionality THD+N VDD = 5V
-120
-70
-117.5
-115
-112.5
-110
-107.5
-105
-102.5
-100
-97.5
-95
-92.5
-90
-87.5
-85
-82.5
-80
-77.5
-75
-72.5
d
B
r
B
-160
+0
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
dBFS
Figure 9 WM8727 Functionality THD+N VDD = 3V
WM8727
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APPLICATIONS INFORMATION
RECOMMENDED EXTERNAL COMPONENTS
VDD
GND
7
6
WM8727
Notes: 1. C2 should be positioned as close to the WM8727 as possible.
2. Capacitor types should be carefully chosen. Capacitors with very low ESR are recommended for optimum performance.
3. C3 and C4 not required if using the recommended low pass filter in Figure 9.
C
2
VDD
C
1
VOUTR
8
C
3
VOUTL
C
4
AC-Coupled
VOUTR/L
to External LPF
5
4
MCLK
2
BCKIN
1
DIN
Audio Serial Data I/F
AGND
3
LRCIN
+
+
+
Figure 10 External Component Diagram
RECOMMENDED EXTERNAL COMPONENTS VALUES
COMPONENT
REFERENCE
SUGGESTED
VALUE
DESCRIPTION
C1
10
F
De-coupling for VDD
C2
0.1
F
De-coupling for VDD
C3 and C4
10
F
Output AC coupling caps to remove midrail DC level from outputs
Table 3 External Components Description
WM8727
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RECOMMENDED ANALOGUE LOW PASS FILTER (OPTIONAL)
+
_
+
+VS
-VS
10uF
51
7.5K
680pF
1.8k
47k
4.7k
4.7k
1.0nF
Figure 11 Recommended Low Pass Filter (Optional)
An external low pass filter is recommended (see Figure 20) if the device is driving a wideband
amplifier. In some applications, a passive RC filter may be adequate.
PCB LAYOUT RECOMMENDATIONS
Care should be taken in the layout of the PCB that the WM8727 is to be mounted to. The
following notes will help in this respect:
1.
The VDD supply to the device should be as noise free as possible. This can be
accomplished to a large degree with a 10uF bulk capacitor placed locally to the device and a
0.1uF high frequency decoupling capacitor placed as close to the VDD pin as possible. It is
best to place the 0.1uF capacitor directly between the VDD and GND pins of the device on
the same layer to minimize track inductance and thus improve device decoupling
effectiveness.
2.
Separate analogue and digital track routing from each other. The device is split into
analogue (pins 5 8) and digital (pins 1 4) sections that allow the routing of these signals
to be easily separated. By physically separating analogue and digital signals, crosstalk from
the PCB can be minimized.
3.
Use an unbroken solid GND plane. To achieve best performance from the device, it is
advisable to have either a GND plane layer on a multilayer PCB or to dedicate one side of a
2 layer PCB to be a GND plane. For double sided implementations it is best to route as
many signals as possible on the device mounted side of the board, with the opposite side
acting as a GND plane. The use of a GND plane greatly reduces any electrical emissions
from the PCB and minimizes crosstalk between signals.
An evaluation board is available for the WM8727 that demonstrates the above techniques and
the excellent performance achievable from the device. This can be ordered or the User manual
downloaded from the Wolfson web site at
www.wolfsonmicro.com
WM8727
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PACKAGE DRAWING
DM009.B
D: 8 PIN SOIC 3.9mm Wide Body
Symbols
Dimensions
(mm)
Dimensions
(Inches)
MIN
MAX
MIN
MAX
A
1.35
1.75
0.0532
0.0688
A
1
0.10
0.25
0.0040
0.0098
B
0.33
0.51
0.0130
0.0200
C
0.19
0.25
0.0075
0.0098
D
4.80
5.00
0.1890
0.1968
e
1.27 BSC
0.050 BSC
E
3.80
4.00
0.1497
0.1574
h
0.25
0.50
0.0099
0.0196
H
5.80
6.20
0.2284
0.2440
L
0.40
1.27
0.0160
0.0500
0
o
8
o
0
o
8
o
REF:
JEDEC.95, MS-012
NOTES:
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS (INCHES).
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM (0.010IN).
D. MEETS JEDEC.95 MS-012, VARIATION = AA. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
C
h x 45
o
L
A
A1
SEATING PLANE
-C-
0.10 (0.004)
4
1
D
5
8
E
H
B
e
WM8727
Production Data
w
PD Rev 4.1 April 2004
16
IMPORTANT NOTICE
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without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that
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Specific testing of all parameters of each device is not necessarily performed, except those mandated by government
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