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Электронный компонент: WM8146

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WM8146
12-bit (8+4-bit) Linear Sensor Image Processor
Product Preview, January 2000 Rev 1.1
WOLFSON MICROELECTRONICS LTD
Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK
Tel: +44 (0) 131 667 9386
Fax: +44 (0) 131 667 5176
Email: sales@wolfson.co.uk
http://www.wolfson.co.uk
Product Preview data sheets contain
specifications for products in the formative
phase of development. These products may
be changed or discontinued without notice.
1999 Wolfson Microelectronics Ltd
.
DESCRIPTION
The WM8146 is a 12-bit analogue front end/digitiser IC,
which processes and digitises the analogue output signals
from linear CCD sensors at pixel sample rates of up to
6MSPS.
The device includes three analogue signal processing
channels each of which contains Reset Level Clamping,
Correlated Double Sampling and Programmable Gain and
Offset adjust functions. The output from each of these
channels is time multiplexed into a single high-speed 12-bit
Analogue to Digital Converter. The digital output data is
available in 8+4-bit wide multiplexed format, with no missing
codes.
The WM8146 is controlled via a configurable serial
interface, which is compatible with all of Wolfson's imaging
devices.
Powered from an analogue supply voltage of 5V and a
digital interface supply of either 5V or 3.3V, the WM8146
typically only consumes 175mW when operating from 5V
supplies.
FEATURES
No missing codes guaranteed
6MSPS sample rate
Colour pixel by pixel or line by line sampling
Monochrome sampling
Selectable reset level clamp voltage
Pixel by pixel or line by line clamping
Correlated double sampling
5-bit programmable gain amplifier
8-bit + sign offset adjustment
5V or 3.3V digital interface compatibility
Serial control interface
28-pin SOIC package
APPLICATIONS
Flatbed scanners
Multi-function peripherals
Copier scanners
CCD sensor interfaces
BLOCK DIAGRAM
+
+
OFFSET
+
+
+
+
M
U
X
RINP
GINP(28)
BINP(27)
TIMING CONTROL
V S M P
(5)
M C L K
(7)
RLC
(6)
DGND
(8)
12-bit
ADC
8+4
M U X
CONFIGURABLE
SERIAL CONTROL
INTERFACE
SDI
SCK
SEN
M U X
VMID
VRLC
(26)
VRT
(24)
VRB
(23)
VMID
(25)
CL
RS
VS
AGND2
(2)
VMID
OFFSET
OFFSET
PGA
PGA
5-BIT REG
CDS
5-BIT REG
5-BIT REG
PGA
VMID
VMID
CDS
CDS
S/H
S/H
S/H
S/H
S/H
S/H
8-BIT +
SIGN DAC
8-BIT +
SIGN DAC
8-BIT +
SIGN DAC
W M 8 1 4 6
DVDD1
(3)
DVDD2
(10)
AGND1
(22)
AVDD
(21)
(9)
(12)
(11)
OEB
(4)
(13) OP[0]
(14) OP[1]
(20)
(15)
(16)
(17)
(18)
(19)
OP[2]
OP[3]
OP[4]
OP[5]
OP[6]
OP[7]
(1)
WM8146
Product Preview
WOLFSON MICROELECTRONICS LTD
PP Rev 1.1 January 2000
2
PIN CONFIGURATION
ORDERING INFORMATION
DEVICE
TEMP. RANGE
PACKAGE
XWM8146CDW/V
0 to 70
o
C
28-pin SOIC
S E N
OP[1]
OP[0]
S C K
SDI
D V D D 2
OP[7]
OP[2]
OP[3]
OP[4]
OP[5]
OP[6]
GINP
A G N D 1
V R B
V R T
VMID
V R L C
BINP
A V D D
D G N D
A G N D 2
D V D D 1
O E B
V S M P
R L C
M C L K
RINP
W M 8 1 4 6
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
1 6
1 5
PIN DESCRIPTION
PIN
NAME
TYPE
DESCRIPTION
1
RINP
Analogue input
Red channel input video.
2
AGND2
Supply
Analogue ground (0V).
3
DVDD1
Supply
Digital supply (5V) for logic and clock generator. This must be operated at the same
potential as AVDD.
4
OEB
Digital input
Output Hi-Z control, all digital outputs disabled when OEB = 1.
5
VSMP
Digital input
Video sample synchronisation pulse.
6
RLC
Digital input
Selects reset level clamp on a pixel-by-pixel basis active high. Tie high to use on
every pixel.
7
MCLK
Digital input
Master clock. This clock is applied at N times the input pixel rate (N = 2, 3, 6, 8 or
any multiple of 2 thereafter depending on input sample mode).
8
DGND
Supply
Digital ground (0V).
9
SEN
Digital input
Enables the serial interface when high.
10
DVDD2
Supply
Digital supply (5V/3.3V), all digital I/O pins.
11
SDI
Digital input
Serial interface data input.
12
SCK
Digital input
Serial interface clock.
13
OP[0]
Digital output
14
OP[1]
Digital output
15
OP[2]
Digital output
16
OP[3]
Digital output
17
OP[4]
Digital output
18
OP[5]
Digital output
19
OP[6]
Digital output
20
OP[7]
Digital output
Digital multiplexed output data bus.
OEB = 0: ADC output data is available in (8+4bit) multiplexed format on pins OP[7] to
OP[0]. See Operational Timing diagrams for details.
OEB = 1: Output is Hi=Z.
21
AVDD
Supply
Analogue supply (5V). This must be operated at the same potential as DVDD1.
22
AGND1
Supply
Analogue ground (0V).
23
VRB
Analogue output
Lower reference point of ADC reference string
This pin must be connected to AGND via a decoupling capacitor.
24
VRT
Analogue output
Upper reference point of ADC reference string
This pin must be connected to AGND via a decoupling capacitor.
25
VMID
Analogue output
Buffered mid-point of ADC reference string
This pin must be connected to AGND via a decoupling capacitor.
26
VRLC
Analogue output
Selectable analogue output voltage for RLC.
This pin must be connected to AGND via a decoupling capacitor.
27
BINP
Analogue input
Blue channel input video.
28
GINP
Analogue input
Green channel input video.
Product Preview
WM8146
WOLFSON MICROELECTRONICS LTD
PP Rev 1.1 January 2000
3
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at
or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
As per JEDEC specifications A112-A and A113-B, this product requires specific storage conditions prior to surface mount
assembly.
CONDITION
MIN
MAX
Analogue supply voltage: AVDD
GND - 0.3V
GND + 7V
Digital supply voltages: DVDD1
-
2
GND - 0.3V
GND + 7V
Digital ground: DGND
GND - 0.3V
GND + 0.3V
Analogue grounds: AGND1
-
2
GND - 0.3V
GND + 0.3V
Digital inputs, digital outputs and digital I/O pins
GND - 0.3V
DVDD2 + 0.3V
Analogue inputs (RINP, GINP, BINP)
GND - 0.3V
AVDD + 0.3V
Other pins
GND - 0.3V
AVDD + 0.3V
Operating temperature range: T
A
0
C
+70
C
Storage temperature
-65
C
+150
C
Lead temperature (soldering, 10 sec)
+260
C
Lead temperature (soldering, 2 mins)
+183
C
Notes: 1.
GND denotes the voltage of any ground pin.
2.
AGND1, AGND2 and DGND pins are intended to be operated at the same potential. Differential voltages
between these pins will degrade performance.
RECOMMENDED OPERATING CONDITIONS
CONDITION
SYMBOL
MIN
TYP
MAX
UNITS
Operating temperature range
T
A
0
70
C
Analogue supply voltage
AVDD
4.75
5.0
5.25
V
Digital core supply voltage
DVDD1
4.75
5.0
5.25
V
5V I/O
DVDD2
4.75
5.0
5.25
V
Digital I/O supply voltage
3.3V I/O
DVDD2
2.97
3.3
3.63
V
WM8146
Product Preview
WOLFSON MICROELECTRONICS LTD
PP Rev 1.1 January 2000
4
ELECTRICAL CHARACTERISTICS
Test Conditions
AVDD = DVDD1 = DVDD2 =4.75 to 5.25V, AGND = DGND = 0V, T
A
= 0 to 70
C, MCLK = 12MHz unless otherwise stated.
PARAMETER
SYMBOL
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
Overall System Specification (including 12-bit ADC, PGA, Offset and CDS functions)
NO MISSING CODES GUARANTEED
Full-scale transition error
25
100
mV
Zero-scale transition error
25
100
mV
Differential non-linearity
DNL
+1.5
LSB
References
Upper reference voltage
VRT
AVDD = 5V
3.47
3.5
3.53
V
Lower reference voltage
VRB
AVDD = 5V
1.47
1.5
1.53
V
DAC reference voltage
VMID
AVDD = 5V
2.47
2.5
2.53
V
RLC switching impedance
500
1.46
1.5
1.54
V
2.46
2.5
2.54
V
Reset level clamp options
VRLC
AVDD = 5V
Voltage set by register
configuration
3.46
3.5
3.54
V
Impedance VRT to VRB
250
500
750
Input Multiplexer
CDS mode full scale input range
(V
VS
-V
RS
)
x denotes the channel selected
Gx
2
Vp-p
Channel to channel gain matching
1
%
Offset DAC (monotonicity guaranteed)
Resolution
8 (+sign)
bits
Zero code voltage
VMID-20
VMID+20
mV
Full scale voltage error
0
20
mV
Differential non-linearity
DNL
0.1
0.5
LSB
Integral non-linearity
INL
0.25
1
LSB
Step size
DACRNG=0
DACRNG=1
4.9
7.4
mV/step
mV/step
Output voltage
DACRNG=0
DACRNG=1
+/-1.25
+/-1.875
V
V
Programmable Gain Amplifier (monotonicity guaranteed)
Resolution
5
bits
Max gain, each channel
G
MAX
8.25
V/V
Min gain, each channel
G
MIN
0.5
V/V
Gain error, each channel
1
%
DIGITAL SPECIFICATIONS
Digital Inputs
High level input voltage
V
IH
0.8
DVDD2
V
Low level input voltage
V
IL
0.2
DVDD2
V
High level input current
I
IH
1
A
Low level input current
I
IL
1
A
Input capacitance
C
I
5
pF
Digital Outputs
High level output voltage
V
OH
I
OH
= 1mA
DVDD2 -
0.5
V
Low level output voltage
V
OL
I
OL
= 1mA
DGND +
0.5
V
High impedance output current
I
OZ
1
A
Product Preview
WM8146
WOLFSON MICROELECTRONICS LTD
PP Rev 1.1 January 2000
5
Test Conditions
AVDD = DVDD1 = DVDD2 =4.75 to 5.25V, AGND = DGND = 0V, T
A
= 0 to 70
C, MCLK = 12MHz unless otherwise stated.
PARAMETER
SYMBOL
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
Supply Currents
Total supply current
-
active
35
mA
Supply current
-
full power down
mode
5
mA
INPUT VIDEO SAMPLING
MCLK
VSMP
INPUT
VIDEO
t
PER
t
VSMPSU
t
VSMPH
t
VSU
t
VH
t
RSU
t
RH
t
MCLKL
t
MCLKH
Figure 1 Input Video Timing
Test Conditions
AVDD = DVDD1 = DVDD2 = 4.75 to 5.25V, AGND = DGND = 0V, T
A
= 0 to 70
C, MCLK = 12MHz unless otherwise stated
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
MCLK period
t
PER
83.3
ns
MCLK high period
t
MCLKH
37.5
ns
MCLK low period
t
MCLKL
37.5
ns
VSMP set-up time
t
VSMPSU
10
ns
VSMP hold time
t
VSMPH
10
ns
Video level set-up time
t
VSU
10
ns
Video level hold time
t
VH
15
ns
Reset level set-up time
t
RSU
10
ns
Reset level hold time
t
RH
15
ns
Notes: 1.
t
VSU
and t
RSU
denote the set-up time required after the input video signal has settled.
2.
Parameters are measured at 50% of the rising/falling edge.
OUTPUT DATA TIMING
M C L K
OP[7:0]
t
P D
Figure 2 Output Data Timing