WM2636

12-bit Serial Input Voltage Output DAC

with Internal Reference

Production Data, July 1999, Rev 1.0

WOLFSON MICROELECTRONICS LTD

Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK
Tel: +44 (0) 131 667 9386
Fax: +44 (0) 131 667 5176
Email: sales@wolfson.co.uk
http://www.wolfson.co.uk

Production Data contain final specifications

current on publication date. Supply of

products conforms to Wolfson

Microelectronics' Terms and Conditions.

1999 Wolfson Microelectronics Ltd

FEATURES

12-bit voltage output DAC

Single supply from 2.7V to 5.5V

DNL

0.5 LSBs, INL

2.0 LSBs

Very low power consumption (3V supply):
-

4.2mW, slow mode

8.1mW, fast mode

TMS320, (Q)SPI

, and Microwire

compatible serial

interface

Programmable settling time of 3.5

s or 1

s typical

High impedance reference input buffer

Power down mode 10nA

APPLICATIONS

Battery powered test instruments

Digital offset and gain adjustment

Battery operated/remote industrial controls

Machine and motion control devices

Wireless telephone and communication systems

Speech synthesis

Arbitrary waveform generation

ORDERING INFORMATION

DEVICE

TEMP. RANGE

PACKAGE

WM2636CD

0° to 70°C

8-pin SOIC

WM2636ID

-40° to 85°C

8-pin SOIC

DESCRIPTION

The WM2636 is a 12-bit voltage output, resistor string digital-to-
analogue converter that can be powered down under software
control. Power down reduces current consumption to 10nA.

An internal precision voltage reference is provided which can
source up to 1mA. This can therefore be used as an external
system reference.

The device has been designed to interface efficiently to industry
standard microprocessors and DSPs, including the TMS320
family. The WM2636 is programmed with a 16-bit serial word
comprising 4 control bits and 12 data bits.

Excellent performance is delivered with a typical DNL of 0.5
LSBs. The settling time of the DAC is programmable to allow
the designer to optimize speed versus power dissipation. The
output stage is buffered by a x2 gain near rail-to-rail amplifier.

The device is available in an 8-pin SOIC package. Commercial
temperature (0

to 70

C) and Industrial temperature (-40

C) variants are supported.

BLOCK DIAGRAM

TYPICAL PERFORMANCE

(7) OUT

12-BIT

DAC

LATCH

POWER-ON

RESET

DIN (1)

SCLK (2)

FS (4)

(5)

AGND

VDD

(8)

POWERDOWN/

SPEED

CONTROL

2-BIT

CONTROL

LATCH

REFERENCE INPUT

BUFFER

16-BIT
SHIFT

REGISTER

AND

CONTROL

LOGIC

data

DAC

OUTPUT
BUFFER

NCS (3)

2-BIT

REFERENCE

SELECT

LATCH

1.024V/2.048V
SELECTABLE

REFERENCE

OUTPUT BUFFER

WITH OUPUT

ENABLE

REF(6)

WM2636

-1

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

512

1024

1536

2048

2559

3071

3583

4095

DIGITAL CODE

DNL

VDD = 5V, V

REF

= External, Speed = Fast mode, Load = 10k/100pF

WM2636

Production Data

WOLFSON MICROELECTRONICS LTD

PD Rev 1.0 July 1999

PIN CONFIGURATION

NCS

DIN

SCLK

AGND

REF

VDD

OUT

PIN DESCRIPTION

PIN NO

NAME

TYPE

DESCRIPTION

DIN

Digital input

Serial data input.

SCLK

Digital input

Serial clock input.

NCS

Digital input

Chip select. This pin is active low.

Digital input

Frame synchronisation for serial input data.

AGND

Supply

Analogue ground.

REF

Analogue I/O

Analogue reference voltage input/output.

OUT

Analogue output

DAC analogue output

VDD

Supply

Positive power supply.

ABSOLUTE MAXIMUM RATINGS

Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at
or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified

ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.

CONDITION

MIN

MAX

Supply voltage, VDD to AGND

Digital input voltage

-0.3V

VDD + 0.3V

Reference input voltage

-0.3V

VDD + 0.3V

Operating temperature range, T

WM2636CD

WM2636ID

-40

Storage temperature

-65

150

Lead temperature 1.6mm (1/16 inch) soldering for 10 seconds

260

RECOMMENDED OPERATING CONDITIONS

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Supply voltage

VDD

2.7

5.5

High-level digital input voltage

VDD = 2.7V to 5.5V

Low-level digital input voltage

VDD = 2.7V to 5.5V

0.8

Reference voltage to REF

REF

See Note

VDD - 1.5

Load resistance

Load capacitance

100

Serial clock rate

SCLK

MHz

WM2636CD

°C

Operating free-air temperature

WM2636ID

-40

°C

Note: Reference voltages greater than VDD/2 will cause saturation for large DAC codes.

WM2636

Production Data

WOLFSON MICROELECTRONICS LTD

PD Rev 1.0 July 1999

ELECTRICAL CHARACTERISTICS

Test Conditions:
R

= 10k

, C

= 100pF. VDD

= 5V

10%, V

REF

= 2.048V and VDD

= 3V

10%, V

REF

= 1.024V over recommended operating

free-air temperature range (unless noted otherwise).

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Static DAC Specifications

Resolution

bits

Integral non-linearity

INL

See Note 1

2.0

4.0

LSB

Differential non-linearity

DNL

See Note 2

0.5

1.0

LSB

Zero code error

ZCE

See Note 3

Gain error

See Note 4

0.6

% FSR

D.c. power supply rejection ratio

DC PSRR

See Note 5

0.5

mV/V

Zero code error temperature coefficient

See Note 6

ppm/

Gain error temperature coefficient

See Note 6

ppm/

DAC Output Specifications

Output voltage range

VDD - 0.1

Output load regulation

to 10k

load

See Note 7

0.1

0.25

Power Supplies

No load, V

= VDD, V

= 0V

VDD = 5V,

REF

= 2.048V Slow

1.6

1.9

VDD = 5V,

REF

= 2.048V Fast

2.9

3.4

VDD = 3V,

REF

= 1.024V Slow

1.4

Active supply current

VDD = 3V,

REF

= 1.024V Fast

See Note 8

2.7

Power down supply current

No load,

all digital inputs 0V or VDD

See Note 9

0.01

Dynamic DAC Specifications

Slew rate

DAC code 128 to 4095,

10%-90% See Note 10

Slow

Fast

Settling time

DAC code 128 to 4095

See Note 11

Slow

Fast

3.5
1.0

Glitch energy

Code 2047 to 2048

nV-s

Signal to noise ratio

SNR

fs = 400ksps, f

OUT

= 1kHz,

BW = 20kHz
See Note 12

Signal to noise and distortion ratio

SNRD

fs = 400ksps, f

OUT

= 1kHz,

BW = 20kHz See Note 12

Total harmonic distortion

THD

= 400ksps, f

OUT

= 1kHz,

BW = 20kHz See Note 12

-67

-59

Spurious free dynamic range

SPFDR

= 400ksps, f

OUT

= 1kHz,

BW = 20kHz See Note 12

WM2636

Production Data

WOLFSON MICROELECTRONICS LTD

PD Rev 1.0 July 1999

Test Conditions:
R

= 10k

, C

= 100pF. VDD

= 5V

10%, V

REF

= 2.048V and VDD

= 3V

10%, V

REF

= 1.024V over recommended operating

free-air temperature range (unless noted otherwise).

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Reference Configured as Input

Reference input resistance

REFIN

Reference input capacitance

REFIN

Reference feedthrough

REF

= 1V

at 1kHz

+ 1.024V dc, DAC code 0

-65

Reference input bandwidth

REF

= 0.2V

+ 1.024V dc

DAC code 2048

Slow

Fast

1.0
1.0

MHz
MHz

Reference configured as output

Low reference voltage

REFOUTL

1.003

1.024

1.045

High reference voltage

REFOUTH

VDD > 4.75V

2.027

2.048

2.069

Output source current

REFSRC

Output sink current

REFSNK

-1

Load Capacitance

100

PSRR

-48

Digital Inputs

High level input current

Input voltage = VDD

Low level input current

Input voltage = 0V

-1

Input capacitance

Notes:
1.

Integral non-linearity (INL) is the maximum deviation of the output from the line between zero and full scale (excluding the effects
of zero code and full scale errors).

Differential non-linearity (DNL) is the difference between the measured and ideal 1LSB amplitude change of any adjacent two
codes. A guarantee of monotonicity means the output voltage changes in the same direction (or remains constant) as a change in
digital input code.

Zero code error is the voltage output when the DAC input code is zero.

Gain error is the deviation from the ideal full scale output excluding the effects of zero code error.

Power supply rejection ratio is measured by varying VDD from 4.5V to 5.5V and measuring the proportion of this signal imposed
on the zero code error and the gain error.

Zero code error and Gain error temperature coefficients are normalised to full scale voltage.

Output load regulation is the difference between the output voltage at full scale with a 10k

load and 2k

load. It is expressed as

a percentage of the full scale output voltage with a 10k

load.

is measured while continuously writing code 2048 to the DAC. For V

< VDD - 0.7V and V

> 0.7V supply current will increase.

Typical supply current in power down mode is 10nA. Production test limits are wider for speed of test.

10. Slew rate results are for the lower value of the rising and falling edge slew rates
11. Settling time is the time taken for the signal to settle to within 0.5LSB of the final measured value for both rising and falling edges.

Limits are ensured by design and characterisation, but are not production tested.

12. SNR, SNRD, THD and SPFDR are measured on a synthesised sinewave at frequency f

OUT

generated with a sampling frequency fs

WM2636

Production Data

WOLFSON MICROELECTRONICS LTD

PD Rev 1.0 July 1999

SERIAL INTERFACE

SUC16FS

SUFS

SCLK

DIN

NCS

D12

D13

D14

D15

SUD

SUCSFS

WHFS

SUC16CS

Figure 1 Timing Diagram

Test Conditions:
R

= 10k

, C

= 100pF. VDD

= 5V

10%, V

REF

= 2.048V and VDD

= 3V

10%, V

REF

= 1.024V over recommended operating

free-air temperature range (unless noted otherwise).

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUCSFS

Setup time NCS low before negative FS edge.

SUFS

Setup time FS low before first negative SCLK edge.

SUC16FS

Setup time, sixteenth negative edge after FS low on
which D0 is sampled before rising edge of FS.

SUC16CS

Setup time, sixteenth positive SCLK edge (first
positive after D0 sampled) before NCS rising edge. If
FS is used instead of the sixteenth positive edge to
update the DAC, then the setup time is between the
FS rising edge and the NCS rising edge.

Pulse duration, SCLK high.

Pulse duration, SCLK low.

SUD

Setup time, data ready before SCLK falling edge.

Hold time, data held valid after SCLK falling edge.

WHFS

Pulse duration, FS high.

WM2636

Production Data

WOLFSON MICROELECTRONICS LTD

PD Rev 1.0 July 1999

TYPICAL PERFORMANCE GRAPHS

VDD = 5V, V

REF

= External 2.048V, Speed = Fast mode

-3

-2

-1

512

1024

1536

2048

2559

3071

3583

4095

DIGITAL CODE

I
N

L - LS

Figure 2 Integral Non-Linearity

0.5

2.5

3.5

I
sink - mA

t
Vo

l
t
ag

e - V

low

Fas

VDD = 3V, V

= 1V, Input Code =

0.5

1.5

2.5

3.5

4.5

0.5

1.5

2.5

3.5

Isink - mA

t
Vo

l
t
ag

e - V

Slow

Fast

VDD = 5V, V

REF

= 2V, Input Code = 0

Figure 3 Sink Current VDD = 3V

Figure 4 Sink Current VDD = 5V

2.066

2.0665

2.067

2.0675

2.068

2.0685

2.069

2.0695

2.07

2.0705

2.071

0.5

1.5

2.5

3.5

Isource - mA

t
Vo

l
t
ag

e - V

Slow

Fast

VDD = 3V, V

REF

= 1V, Input Code = 4095

4.129

4.13

4.131

4.132

4.133

4.134

4.135

0.5

1.5

2.5

3.5

Isource - mA

t
p

t
V

Slow

Fast

VDD = 5V, V

REF

= 2V, Input Code = 4095

Figure 5 Source Current VDD = 3V

Figure 6 Source Current VDD = 5V

WM2636

Production Data

WOLFSON MICROELECTRONICS LTD

PD Rev 1.0 July 1999

DEVICE DESCRIPTION

GENERAL FUNCTION

The device uses a resistor string network buffered with an op amp to convert 12-bit digital data
to analogue voltage levels (see Block Diagram). The output voltage is determined by the
reference input voltage and the input code according to the following relationship:

Output voltage =

( )

4096

CODE

REF

INPUT

OUTPUT

1111

( )

4096

4095

REF

1000

0000

0001

( )

4096

2049

REF

1000

0000

( )

REF

4096

2048

0111

1111

( )

4096

2047

REF

0000

0001

( )

4096

REF

0000

Table 1 Binary Code Table (0V to 2V

REF

Output), Gain = 2

POWER ON RESET

An internal power-on-reset circuit resets the DAC register to all 0s on power-up.

BUFFER AMPLIFIER

The output buffer has a near rail-to-rail output with short circuit protection and can reliably drive
a 2k

load with a 100pF load capacitance.

SERIAL INTERFACE

Explanation of data transfer:

First, the device has to be enabled with NCS set to low. Then, a falling edge of FS starts
shifting the data bit-per-bit (starting with the MSB) to the internal register on the falling edges of
SCLK. After 16 bits have been transferred or FS rises, the content of the shift register is moved
to the DAC latch which updates the voltage output to the new level.

The serial interface of the device can be used in two basic modes:

four wire (with chip select)

three wire (without chip select)

Using chip select (four wire mode), it is possible to have more than one device connected to
the serial port of the data source (DSP or microcontroller). If there is no need to have more
than one device on the serial bus, then NCS can be tied low.

SERIAL CLOCK AND UPDATE RATE

Figure 1 shows the device timing. The maximum serial rate is:

SCLK

max =

MHz

min

WCL

min

WCH

The digital update rate is limited to an 800ns period, or 1.25MHz frequency. However, the DAC
settling time to 12 bits limits the update rate for large input step transitions.

WM2636

Production Data

WOLFSON MICROELECTRONICS LTD

PD Rev 1.0 July 1999

SOFTWARE CONFIGURATION OPTIONS

The 16 bits of data can be transferred with the sequence shown in Table 2. D11-D0 contains
the 12-bit data word. D15-D12 hold the programmable options.

D15

D14

D13

D12

D11

D10

SPD PWR

New DAC or control register value (12 bits)

Table 2 Serial Word Format

PROGRAMMABLE SETTLING TIME

Settling time is a software selectable 3.5

s or 1

s, typical to within

0.5LSB of final value. This

is controlled by the value of D14. A ONE defines a settling time of 1

s, a ZERO defines a

settling time of 3.5

PROGRAMMABLE POWER DOWN

The power down function is controlled by D13. A ZERO configures the device as active, or fully
powered up, a ONE configures the device into power down mode. When the power down
function is released the device reverts to the DAC code set prior to power down.

REGISTER ADDRESSING

A separate internal control register is available. This is accessed from the register access bits
R1 (Bit D15) and R0 (Bit D12).

(BIT D15)

(BIT D12)

REGISTER

Write data to DAC

Reserved

Write data to control register

Table 3 Register Access Control

The contents of the control register, shown below in Table 4, are used to program the internal
reference function.

D11

D10

REF1 REF0

Table 4 Control Register Contents

PROGRAMMABLE INTERNAL REFERENCE

The reference can be sourced internally or externally under software control. If an external
reference voltage is applied to the REF pin, the device must be configured to accept this.

If an external reference is selected, the reference voltage input is buffered which makes the
DAC input resistance independent of code. The REF pin has an input resistance of 10M

and

an input capacitance of typically 55pF. The reference voltage determines the DAC full-scale
output.

If an internal reference is selected, a voltage of 1.024V or 2.048 is available. The internal
reference can source up to 1mA and can therefore be used as an external system reference.

REF1

REF0)

REGISTER

External

1.024V

2.048V

External

Table 5 Programmable Internal Reference

WM2636

Production Data

WOLFSON MICROELECTRONICS LTD

PD Rev 1.0 July 1999

PACKAGE DIMENSIONS

DM009.B

D: 8 PIN SOIC 3.9mm Wide Body

Symbols

Dimensions

(mm)

Dimensions

(Inches)

MIN

MAX

MIN

MAX

1.35

1.75

0.0532

0.0688

0.10

0.25

0.0040

0.0098

0.33

0.51

0.0130

0.0200

0.19

0.25

0.0075

0.0098

4.80

5.00

0.1890

0.1968

1.27 BSC

0.050 BSC

3.80

4.00

0.1497

0.1574

0.25

0.50

0.0099

0.0196

5.80

6.20

0.2284

0.2440

0.40

1.27

0.0160

0.0500

REF:

JEDEC.95, MS-012

NOTES:
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS (INCHES).
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM (0.010IN).
D. MEETS JEDEC.95 MS-012, VARIATION = AA. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.

h x 45

SEATING PLANE

-C-

0.10 (0.004)

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: WM2636ID

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: WM2636ID