W83194BR-648

- II -

Table of Contents-

GENERAL DESCRIPTION ..........................................................................................................1

FEATURES ..................................................................................................................................1

PIN CONFIGURATION ................................................................................................................2

BLOCK DIAGRAM .......................................................................................................................2

PIN DESCRIPTION......................................................................................................................3

5.1

Crystal I/O.................................................................................................................................3

5.2

CPU, ZCLK, SDRAM, PCI Clock Outputs...............................................................................3

5.3

I2C Control Interface ................................................................................................................4

5.4

Fixed Frequency Outputs ........................................................................................................4

5.5

Power Management Pins.........................................................................................................4

5.6

Power Pins................................................................................................................................5

5.7

Hardware MULTSEL0 Selects Function .................................................................................5

FREQUENCY SELECTION BY HARDWARE OR SOFTWARE .................................................6

C CONTROL AND STATUS REGISTERS ................................................................................7

7.1

7.2

7.3

7.4

7.5

7.6

7.7

7.8

7.9

7.10

7.11

7.12

7.13

7.14

7.15

7.16

7.17

Ratio Selection Table.............................................................................................................13

ACCESS INTERFACE ...............................................................................................................14

8.1

Block Write Protocol...............................................................................................................14

8.2

Block Read Protocol...............................................................................................................14

W83194BR-648

Publication Release Date: April 13, 2005

- III -

Revision 1.1

8.3

Byte Write Protocol.................................................................................................................14

8.4

Byte Read Protocol ................................................................................................................14

SPECIFICATIONS .....................................................................................................................15

9.1

Absolute Maximum Ratings...................................................................................................15

9.2

General Operating Characteristics........................................................................................15

9.3

Skew Group Timing Clock .....................................................................................................16

9.4

CPU 0.7V Electrical Characteristics ......................................................................................16

9.5

CPU 1.0V Electrical Characteristics ......................................................................................16

9.6

AGP Electrical Characteristics...............................................................................................17

9.7

PCI Electrical Characteristics.................................................................................................17

9.8

ZCLK Electrical Characteristics .............................................................................................17

9.9

SDRAM Electrical Characteristics .........................................................................................18

9.10

24M, 48M Electrical Characteristics ......................................................................................18

9.11

REF Electrical Characteristics ...............................................................................................18

10.

POWER MANAGEMENT TIMING .............................................................................................19

10.1

CPU_STOP# Timing Diagram...............................................................................................19

10.2

PCI_STOP# Timing Diagram ................................................................................................19

11.

ORDERING INFORMATION......................................................................................................20

12.

HOW TO READ THE TOP MARKING.......................................................................................20

13.

PACKAGE DRAWING AND DIMENSIONS...............................................................................21

14.

REVISION HISTORY .................................................................................................................22

W83194BR-648

Publication Release Date: April 13, 2005

- 1 -

Revision 1.1

1. GENERAL DESCRIPTION

The W83194BR-648 is a Clock Synthesizer for SIS P4 series chipset. W83194BR-648 provides all
clocks required for high-speed Intel Pentium 4, and also provides 32 different frequencies of CPU
clocks frequency setting. All clocks are externally selectable with smooth transitions. The W83194BR-
648 makes SDRAM in synchronous or asynchronous frequency with CPU clocks.

The W83194BR-648 provides step-less frequency programming by controlling the VCO freq. and the
programmable AGP, PCI clock output divisor ratio. AGP and PCI frequency can be fixed to be four
kinds of different frequency outputs. A watchdog timer is quipped and when time out, register9 bit5 will
be set to 1 for warning. Spread spectrum built in at �0.5% or �0.25% to reduce EMI. Programmable
stopping individual clock outputs and frequency selection through I

C interface.

The W83194BR-648 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.
High drive PCI CLOCK outputs typically provide greater than 1V /nS slew rate into 30 pF loads. The
fixed frequency outputs as REF, 24 MHz, and 48 MHz provide better than 0.5V /nS slew rate.

2. FEATURES

�

Supports Intel Pentium 4 CPU with I

�

2 pairs of differential CPU clocks

�

2 ZCLK for SIS chipsets

�

2 AGP clocks

�

1 SDRAM output clock for chipset

�

8 PCI synchronous clocks

�

1 24/48 MHz, 1 48 MHz

�

REF

clocks

�

Skew --- CPU to SDRAM < 1 ns, PCI to PCI < 500ps, AGP to AGP < 175ps

�

Smooth frequency switch with selections from 66 to 200 MHz

�

C 2-Wire serial interface and I

C read back

�

Flexible spread spectrum to reduce EMI

�

Programmable registers to enable/stop each output

�

Packaged in 48-pin SSOP

W83194BR-648

- 2 -

3. PIN CONFIGURATION

V D D R 1

4 8 V D D S D

F S 0 & / R E F 0 2

4 7 S D R A M

F S 1 & / R E F 1 3

4 6 G N D

F S 2 & / R E F 2 4

4 5 C P U _ S T O P # *

G N D 5

4 4 C P U C L K T _ 1

X I N 6

4 3 C P U C L K C _ 1

X O U T 7

4 2 V D D C

G N D 8

4 1 G N D

Z C L K 0 9

4 0 C P U C L K T _ 0

Z C L K 1 1 0

3 9 C P U C L K C _ 0

V D D Z 1 1

3 8 I R E F

P C I _ S T O P # * 1 2

3 7 G N D

V D D P C I 1 3

3 6 V D D A

F S 3 & / P C I C L K _ F 0 1 4

3 5 S D C L K *

F S 4 & / P C I C L K _ F 1 1 5

3 4 S D A T A *

P C I C L K 0 1 6

3 3 P D # * / V T T _ P W G D

P C I C L K 1 1 7

3 2 G N D

G N D 1 8

3 1 A G P C L K 0

V D D P C I 1 9

3 0 A G P C L K 1

P C I C L K 2 2 0

2 9 V D D A G P

P C I C L K 3 2 1

2 8 V D D 4 8

P C I C L K 4 2 2

2 7 4 8 M H z

P C I C L K 5 2 3

2 6 2 4 _ 4 8 M H z / M U L T I S E L 0 *

G N D 2 4

2 5 G N D

#: Active low
*: Internal pull up resistor 120K to VDD
&: Internal Pull-down resistor 120K to GND

4. BLOCK DIAGRAM

PLL2

Mux

Control

Logic

Config

Register

Divider

1/2

Stop

XTAL

OSC

PLL1

Spread

Spectrum

Stop

M/N/Ratio

S.S.P

ROM

Driver

VCOCLK

48MHz

24_48MHz

REF0:2

CPUCLK_T 0:1

CPUCLK_C 0:1

AGPCLK 0:1

PCICLK_F0:1

PCICLK_0:5

Rref

XIN

XOUT

SDATA*

SDCLK*

FS<0:4>

PD#*

CPU_STOP#*

PCI_STOP#*

MULTISEL0*

VTT_PWGD

Latch

POR

I2C

interface

ZCLK 0:1

SDRAM

W83194BR-648

Publication Release Date: April 13, 2005

- 3 -

Revision 1.1

5. PIN DESCRIPTION

BUFFER TYPE SYMBOL

DESCRIPTION

IN Input

tp120k

Latched input at power up, internal 120K pull up.

td120k

Latched input at power up, internal 120K pull down.

OUT Output

OD Open

Drain

I/O Bi-directional

I/OD Bi-directional

Pin,

Open

Drain.

# Active

Low

Internal 120k

pull-up

Internal 120 k

pull-down

5.1 Crystal I/O

PIN

PIN NAME

TYPE

DESCRIPTION

6 XIN

Crystal input with internal loading capacitors (18pF) and
feedback resistors.

7 XOUT

OUT

Crystal output at 14.318 MHz nominally with internal loading
capacitors (18pF).

5.2 CPU, ZCLK, SDRAM, PCI Clock Outputs

PIN

PIN NAME

TYPE

DESCRIPTION

40, 39,

44, 43

CPUCLKT_0

CPUCLKC_0,

CPUCLKT_1

CPUCLKC_1,

OUT

True CPU clock output and Complementary CPU clock
output. These pins will be stopped by CPU_STOP#

SDRAM

OUT

SDRAM clock output, which have syn. or asyn. Frequencies
as CPU clocks. The clock phase is the same as CPUCLKT_0
and CPUCLKT_1.

PCICLK_F0

OUT

PCI free running clock during normal operation.

FS3

td120k

Latched input for FS3 at initial power up for H/W selecting the
output frequency. Internal 120K

pull-down

PCICLK_F1

OUT

PCI free running clock during normal operation.

FS4

td120k

Latched input for FS4 at initial power up for H/W selecting the
output frequency. Internal 120K

pull-down

16, 17, 20,

21, 22, 23

PCICLK [0:5]

OUT Low skew (< 500 pS) PCI clock outputs.

31, 30

AGPCLK [0:1]

OUT AGP clock outputs for AGP.

9, 10

ZCLK [0:1]

OUT Z clock outputs for chipset.

W83194BR-648

- 4 -

5.3 I2C Control Interface

PIN

PIN NAME

TYPE

DESCRIPTION

34 SDATA* I/O

Serial data of I

C 2-wire control interface, Internal 120K

pull-up.

35 SDCLK* IN

Serial clock of I

C 2-wire control interface, Internal 120K

pull-up.

5.4 Fixed Frequency Outputs

PIN

PIN NAME

TYPE

DESCRIPTION

38 IREF IN

Deciding the reference current for the CPUCLK pairs. The pin
was connected to the precision resistor tied to ground to decide
the appropriate current. There are two modes to select different
current via power on trapping the Pin 26 (MULTISEL0). The table
is show as follows.

REF0

OUT

3.3V, 14.318 MHz reference clock output.

FS0

td120k

Latched input for FS0 at initial power up for H/W selecting the
output frequency. Internal 120 K

pull- down.

REF1

OUT

3.3V, 14.318 MHz reference clock output.

FS1

td120k

Latched input for FS1 at initial power up for H/W selecting the
output frequency, Internal 120 K

pull- down.

REF2

OUT

3.3V, 14.318 MHz reference clock output.

FS2

td120k

Latched input for FS2 at initial power up for H/W selecting the
output frequency. Internal 120 K

pull- down.

24_48 MHz

OUT

24 MHz or 48 MHz clock output selected by Register.

MULTISEL0*

tp120k

MULTISEL0* at initial power up for H/W selecting the current
multiplier for CPU outputs. Internal 120 K

pull-up.

48 MHz

OUT

48 MHz output for USB.

5.5 Power Management Pins

PIN

PIN NAME

TYPE

DESCRIPTION

PD#* IN

Power Down pin, low active all clocks are stopped, internal
120K pull up.

VTT_PWGD

Power good input signal comes from ACPI with high active. This
3.3V input is level sensitive strobe used to determine FS [4:0] and
MULTISEL0 input are valid and is ready to sample. This pin is
high active.

45 CPU_STOP#*

IN CPU clock stop control pin, This pin is low active. Internal 120K

pull-up.

12 PCI_STOP#*

IN PCI clock stop control pin, This pin is low active. Internal 120K

pull-up.

W83194BR-648

Publication Release Date: April 13, 2005

- 5 -

Revision 1.1

5.6 Power Pins

PIN

PIN NAME

DESCRIPTION

VDDR

Power supply for REF0: 2 3.3V.

VDDZ

Power supply for ZCLK 3.3V.

VDDA

Power supply for core logic. 3.3V

VDDC

Power supply for CPUCLK 3.3V.

VDDAGP

Power supply for AGP outputs.

13,19

VDDPCI

Power supply for PCI outputs.

VDDSD

Power supply for SDRAM 3.3V.

VDD48

Power supply for 48/24 MHz outputs.

5, 8, 18, 24, 25,

32, 37, 41, 46

GND Circuit

Ground.

5.7 Hardware MULTSEL0 Selects Function

MULTSEL0

PIN 26

BOARD TARGET

TRACE/TERM Z

REFERENCE R, IREF =

VDD/(3*RR)

OUTPUT

CURRENT

VOH @ Z

0 50

Rr = 221 1%

IREF = 5.00 mA

Ioh = 4*IREF

1.0V @ 50

0 60

Rr =221 1%

IREF = 5.00 mA

Ioh = 4*IREF

1.2V @ 60

1 50

Rr = 221 1%

IREF = 5.00 mA

Ioh = 6*IREF

1.5V @ 50

1 60

Rr = 221 1%

IREF = 5.00 mA

Ioh = 6*IREF

1.8V @ 60

0 50

Rr = 475 1%

IREF = 2.32 mA

Ioh = 4*IREF

0.47V @ 50

0 60

Rr = 475 1%

IREF = 2.32 mA

Ioh = 4*IREF

0.56V @ 60

1 50

Rr = 475 1%

IREF = 2.32 mA

Ioh = 6*IREF

0.7V @ 50

1 60

Rr = 475 1%

IREF = 2.32 mA

Ioh = 6*IREF

0.84V @ 60

W83194BR-648

- 6 -

6. FREQUENCY SELECTION BY HARDWARE OR SOFTWARE

This frequency table is used at power on latched FS [4:0] value or software programming at SSEL
[4:0] (Register 4 bit 4 ~ 7, 2)

FS4 FS3 FS2 FS1 FS0 CPU (MHz) SDRAM (MHz) ZCLK (MHz) AGP (MHz)

PCI (MHz)

0 0 0 0 0 100.2

100.2

80.2

66.8

33.4

0 0 0 0 1 100.2

133.6

80.2

66.8

33.4

0 0 0 1 0 100.2

200.5

80.2

66.8

33.4

0 0 0 1 1 100.2

167.0

83.5

62.6

31.3

0 0 1 0 0 133.6

100.2

80.2

66.8

33.4

0 0 1 0 1 133.6

133.6

80.2

66.8

33.4

0 0 1 1 0 133.6

200.5

80.2

66.8

33.4

0 0 1 1 1 133.7

167.2

83.6

66.9

33.4

0 1 0 0 0 166.6

99.9

83.3

62.5

31.2

0 1 0 0 1 166.8

133.4

83.4

66.7

33.4

0 1 0 1 0 166.8

222.4

83.4

66.7

33.4

0 1 0 1 1 166.8

166.8

83.4

66.7

33.4

0 1 1 0 0 199.7

99.9

79.9

66.6

33.3

0 1 1 0 1 199.7

133.2

79.9

66.6

33.3

0 1 1 1 0 199.7

199.7

79.9

66.6

33.3

0 1 1 1 1 200.0

150.0

75.0

66.7

33.3

1 0 0 0 0 100.2

100.2

133.6

66.8

33.4

1 0 0 0 1 100.2

133.6

66.8

33.4

1 0 0 1 0 100.2

200.5

133.6

66.8

33.4

1 0 0 1 1 100.2

167.0

125.3

62.6

31.3

1 0 1 0 0 133.6

100.2

133.6

66.8

33.4

1 0 1 0 1 133.6

133.6

66.8

33.4

1 0 1 1 0 133.6

200.5

133.6

66.8

33.4

1 0 1 1 1 133.7

167.2

133.7

66.9

33.4

1 1 0 0 0 166.6

99.9

124.9

62.5

31.2

1 1 0 0 1 166.8

133.4

66.7

33.4

1 1 0 1 0 166.8

222.4

133.4

66.7

33.4

1 1 0 1 1 166.8

166.8

133.4

66.7

33.4

1 1 1 0 0 199.7

99.9

133.2

66.6

33.3

1 1 1 0 1 199.7

133.2

66.6

33.3

1 1 1 1 0 199.7

199.7

133.2

66.6

33.3

1 1 1 1 1 200.0

150.0

120.0

66.7

33.3

W83194BR-648

Publication Release Date: April 13, 2005

- 7 -

Revision 1.1

7. I

C CONTROL AND STATUS REGISTERS

The Register 0~3 are reserved for external clock buffer

(The register No. Is increased by 1 if use byte data read/write protocol)

7.1 Register 4: Frequency Select (Default = 00H)

BIT

NAME

PWD

DESCRIPTION

7 SSEL

[3] 0

6 SSEL

[2] 0

5 SSEL

[1] 0

4 SSEL

[0] 0

Frequency selection by software via I

3 EN_SSEL 0

Enable software program FS [4:0].
0 = Select frequency by hardware.
1 = Select frequency by software I

C - Bit 4:7, 2.

SSEL [4]

Frequency selection bit 4

1 EN_SPSP

Enable Spread Spectrum in the frequency table.
0 = Normal
1 = Spread Spectrum enabled

0 EN_SAFE_FREQ

Enable reload safe frequency when the watchdog is timeout.
0 = reload the FS [4:0] latched pins when watchdog time out.
1 = reload the safe frequency bit defined at Register 9 bit 4~0.

7.2 Register 5: CPU, SDRAM Clock (1 = Enable, 0 = Stopped) (Default = FFH)

BIT

PIN NO

PWD

DESCRIPTION

7 47 1

SDRAM

output

control

6 44,

43 1

CPUCLKT/C1

output

control

5 40,

39 1

CPUCLKT/C0

output

control

Invert Power on latched value of FS4 pin,

Default 1 (Read only)

Invert Power on latched value of FS3 pin. Default 1 (Read only)

Invert Power on latched value of FS2 pin. Default 1 (Read only)

Invert Power on latched value of FS1 pin. Default 1 (Read only)

Invert Power on latched value of FS0 pin. Default 1 (Read only)

W83194BR-648

- 8 -

7.3 Register 6 PCI Clock (1 = Enable, 0 = Stopped) (Default = FFH)

BIT

PIN NO

PWD

DESCRIPTION

7 15 1

PCICLK_F1

output

control

6 14 1

PCICLK_F0

output

control

PCICLK 5 output control

PCICLK 4 output control

PCICLK 3 output control

PCICLK 2 output control

PCICLK 1 output control

PCICLK 0 output control

7.4 Register 7 48 MHz, ZCLK, REF Clock (1 = Enable, 0 = Stopped) (Default = FFH)

BIT

PIN NO

PWD

DESCRIPTION

48 MHZ output control

24_48 MHz output control

5 SEL_24 1

24/48 MHz frequency control
1: 24 MHz.
0: 48 MHz.

ZCLK1 output control

ZCLK0 output control

2 4 1

REF2

output

control

1 3 1

REF1

output

control

0 2 1

REF0

output

control

7.5 Register 8: AGP Control (1 = Enable, 0 = Stopped) (Default = CEH)

BIT

Pin NO

PWD

DESCRIPTION

7 1

CPUCLKT/C0 Stop control: 0: CPUCLK0 free run
1: CPUCLK0 can stopped by CPU_STOP#

6 1

CPUCLKT/C1 Stop control: 0: CPUCLK1 free run
1: CPUCLK1 can stopped by CPU_STOP#

5 0

PCI_F0 Stop control: 0: PCI_F0 free run
1: PCI_F0 can stopped by PCI_STOP#

4 0

PCI_F1 Stop control: 0: PCI_F1 free run
1: PCI_F1 can stopped by PCI_STOP#

3 30 1

AGP_1

output

control

2 31 1

AGP_0

output

control

MULTISEL0

MULTISEL0 trapping pin data read back, Default 1.

0 Reserved 0

Reserved

W83194BR-648

Publication Release Date: April 13, 2005

- 9 -

Revision 1.1

7.6 Register 9: Watchdog Control (Default = 00H)

BIT

NAME

PWD

DESCRIPTION

7 Reserved 0

Reserved

6 EN_WD 0

Enable Watchdog Timer if set to 1. Set to 0, disable watchdog timer.
Read this bit will return a counting state. If timer continues down count,
this bit will return 1. Otherwise, this bit will return 0.

5 WD_TIMEOUT

Watchdog Timeout Status. If the watchdog is started and timer down
counts to zero, this bit will be set to 1. Clear this bit to logic 0, If set to
1, when the watchdog is restart in the next time. This bit is Read Only.

4 SAF_FREQ

[4]

3 SAF_FREQ

[3]

2 SAF_FREQ

[2]

1 SAF_FREQ

[1]

0 SAF_FREQ

[0]

Watchdog safe frequency bits. These bits will be reloaded into FS
[4:0], if the watchdog is timeout and enable reload safe frequency bits.

7.7 Register 10: Watchdog Timer (Default = 08H)

BIT

NAME

PWD

DESCRIPTION

7 WD_TIME

[7] 0

6 WD_TIME

[6] 0

5 WD_TIME

[5] 0

4 WD_TIME

[4] 0

3 WD_TIME

[3] 1

2 WD_TIME

[2] 0

1 WD_TIME

[1] 0

0 WD_TIME

[0] 0

Watchdog timeout time. The bit resolution is 250 mS. The default time
is 8*250 mS = 2.0 seconds. If the watchdog timer is start, this register
will be down count. Read this register will return a down count value.

7.8 Register 11: M/N Program (Default = ABH)

BIT

NAME

PWD

DESCRIPTION

N_DIV [8]

Programmable N divisor value. Bit 7 ~0 are defined in the Register 12.

TEST2

Test bit 2. WINBOND test bit, do not change them.

TEST1

Test bit 1. WINBOND test bit, do not change them.

4 M_DIV

[4] 0

3 M_DIV

[3] 1

2 M_DIV

[2] 0

1 M_DIV

[1] 1

0 M_DIV

[0] 1

Programmable M divisor value.

W83194BR-648

- 10 -

7.9 Register 12: M/N Program (Default = 2FH)

BIT

NAME

PWD

DESCRIPTION

7 N_DIV

[7]

6 N_DIV

[6] 0

5 N_DIV

[5] 1

4 N_DIV

[4] 0

3 N_DIV

[3] 1

2 N_DIV

[2] 1

1 N_DIV

[1] 1

0 N_DIV

[0] 1

Programmable N divisor value bit 7 ~0. The bit 8 is defined in
Register 11.

7.10 Register 13: Spread Spectrum Programming (Default = 1FH)

BIT

NAME

PWD

DESCRIPTION

SP_UP [3]

Spread Spectrum Up Counter bit 3.

SP_UP [2]

Spread Spectrum Up Counter bit 2.

SP_UP [1]

Spread Spectrum Up Counter bit 1.

SP_UP [0]

Spread Spectrum Up Counter bit 0

SP_DOWN [3]

Spread Spectrum Down Counter bit 3

SP_DOWN [2]

Spread Spectrum Down Counter bit 2

SP_DOWN [1]

Spread Spectrum Down Counter bit 1

SP_DOWN [0]

Spread Spectrum Down Counter bit 0

7.11 Register 14: Divisor and Step-less Enable Control (Default = 4CH)

BIT

NAME

PWD

DESCRIPTION

7 EN_MN_PROG 0

0: use frequency table
1: use M/N register to program frequency
The equation is VCO freq. = 14.318 MHz * (N+4)/ M. When the
watchdog timer is timeout, this will be clear. In this time, the
frequency is set to hardware default latched or safe frequency set
by EN_SFAE_FREQ (Register 4 bit 0).

6 RATIO_SEL

[4] 1

5 RATIO_SEL

[3] 0

4 RATIO_SEL

[2] 0

3 RATIO_SEL

[1] 1

2 RATIO_SEL

[0] 1

CPU, PCI, AGP, SDRAM, and ZCLK ratio selection. The ratio is
shown as following table.

1 TEST0 0
0 Reserved 0

Test bit 0. WINBOND test bit, do not change them.

W83194BR-648

Publication Release Date: April 13, 2005

- 11 -

Revision 1.1

7.12 Register 15: CPU_ZCLK Skew Control (Default = A7H)

BIT

NAME

PWD

DESCRIPTION

CPU_ZCLK_SKEW [2]

CPU to ZCLK SKEW control

6 Reserved 0

Reserved

5 Reserved 1
4 Reserved 0
3 Reserved 0
2 Reserved 1
1 Reserved 1
0 Reserved 1

Reserved

7.13 Register 16: CPU_AGP_SKEW (Default = 1CH)

BIT

NAME

PWD

DESCRIPTION

7 SEL

[1] 0

6 SEL

[0] 0

AGP & PCI FIX frequency (PCI = AGP/2)
SEL [1:0] for AGP 00: 72 MHZ 01: 64 MHZ
10: 77NHZ 11: 67MHZ

FIX_AGP_PCI

0:normal mode, 1: fix mode

CPU_STOP

CPU_STOP pin read back

PCI_STOP

CPU_STOP pin read back

2 CPU_AGP_SKEW

[2] 1

1 CPU_AGP_SKEW

[1] 0

0 CPU_AGP_SKEW

[0] 0

CPU to AGP skew.

7.14 Register 17: Skew Control (Default = 24H)

BIT

NAME

PWD

DESCRIPTION

7 CPU_ZCLK_SKEW

[1] 0

6 CPU_ZCLK_SKEW

[0] 0

CPU to AGP skew

5 CPU_SDRAM_SKEW

[2] 1

4 CPU_SDRAM_SKEW

[1] 0

3 CPU_SDRAM_SKEW

[0] 0

CPU to SDRAM skew

2 CPU_PCI_SKEW

[2] 1

1 CPU_PCI_SKEW

[1] 0

0 CPU_PCI_SKEW

[0] 0

CPU to PCI skew

W83194BR-648

- 12 -

7.15 Register 18: Winbond Chip ID (Read Only) (Default = 77H)

BIT

NAME

PWD

DESCRIPTION

7 CHPI_ID

[7]

WINBOND Chip ID. W83194BR-648 is 0x77.

CHPI_ID [6]

WINBOND Chip ID.

CHPI_ID [5]

WINBOND Chip ID.

CHPI_ID [4]

WINBOND Chip ID.

CHPI_ID [3]

WINBOND Chip ID.

CHPI_ID [2]

WINBOND Chip ID.

CHPI_ID [1]

WINBOND Chip ID.

CHPI_ID [0]

WINBOND Chip ID.

7.16 Register 19: Winbond Chip ID (Read Only) (Default = 11H)

BIT

NAME

PWD

DESCRIPTION

7 SUB_ID

[3] 0

WINBOND Sub-Chip ID. The sub-chip ID of W83194BR-648 is
defined as 0001b.

SUB_ID [2]

WINBOND Sub-Chip ID.

SUB_ID [1]

WINBOND Sub-Chip ID.

SUB_ID [0]

WINBOND Sub-Chip ID.

VER_ID [3]

WINBOND Version ID. The Version ID of W83194BR-648 is 0001b.

VER_ID [2]

WINBOND Version ID.

VER_ID [1]

WINBOND Version ID.

VER_ID [0]

WINBOND Version ID.

W83194BR-648

Publication Release Date: April 13, 2005

- 13 -

Revision 1.1

7.17 Ratio Selection Table

Table of CPU, PCI, AGP, SDRAM, and ZCLK clock selection.

Reg14 Reg14 Reg14 Reg14

Reg14

Bit6 Bit5 Bit4 Bit3 Bit2

CPU

SDRAM

ZCLK

AGP

PCI

SSEL4 SSEL3 SSEL2 SSEL1

SSEL0

Ratio

Ratio Ratio Ratio Ratio

0 0 0 0 0 4

4 5 6

0 0 0 0 1 4

3 5 6

0 0 0 1 0 4

2 5 6

0 0 0 1 1 5

3 6 8

0 0 1 0 0 3

4 5 6

0 0 1 0 1 3

3 5 6

0 0 1 1 0 3

2 5 6

0 0 1 1 1 5

4 8

0 1 0 0 0 3

5 6 8

0 1 0 0 1 4

5 8

0 1 0 1 0 4

3 8

0 1 0 1 1 4

4 8

0 1 1 0 0 2

4 5 6

0 1 1 0 1 2

3 5 6

0 1 1 1 0 2

2 5 6

0 1 1 1 1 3

4 8 9

1 0 0 0 0 4

4 3 6

1 0 0 0 1 4

3 3 6

1 0 0 1 0 4

2 3 6

1 0 0 1 1 5

3 4 8

1 0 1 0 0 3

4 3 6

1 0 1 0 1 3

3 3 6

1 0 1 1 0 3

2 3 6

1 0 1 1 1 5

4 5

1 1 0 0 0 3

5 4 8

1 1 0 0 1 4

5 5

1 1 0 1 0 4

3 5

1 1 0 1 1 4

4 5

1 1 1 0 0 2

4 3 6

1 1 1 0 1 2

3 3 6

1 1 1 1 0 2

2 3 6

1 1 1 1 1 3

4 5 9

W83194BR-648

Publication Release Date: April 13, 2005

- 15 -

Revision 1.1

9. SPECIFICATIONS

9.1 Absolute Maximum Ratings

Stresses greater than those listed in this table may cause permanent damage to the device.
Precautions should be taken to avoid application of any voltage higher than the maximum rated
voltages to this circuit. Subjection to maximum conditions for extended periods may affect reliability.
Unused inputs must always be tied to an appropriate logic voltage level (Ground or VDD).

PARAMETER RATING

Absolute 3.3V Core Supply Voltage

-0.5V to +4.6V

Absolute 3.3V I/O Supple Voltage

-0.5 V to +4.6 V

Operating 3.3V Core Supply Voltage

3.135V to 3.465V

Operating 3.3V I/O Supple Voltage

3.135V to 3.465V

Storage Temperature

-65

�

C to +150

�

Ambient Temperature

-55

�

C to +125

�

Operating Temperature

�

C to +70

�

Input ESD Protection (Human body model)

2000V

9.2 General Operating Characteristics

VDDR = VDDZ = VDDA = VDDC = VDDAGP = VDDPCI = VDDSD = VDD48 = 3.3V

�

5 %, TA = 0

�

C to +70

�

C, Cl = 10pF

PARAMETER SYM.

MIN.

MAX.

UNITS

TEST

CONDITIONS

Input Low Voltage

0.8 V

Input High Voltage

2.0 V

Output Low Voltage

0.4 V

All outputs using 3.3V power

Output High Voltage

2.4 V

All outputs using 3.3V power

Dynamic Supply Current

350

CPU = 100 to 200 MHz
PCI = 33.3 MHz with load

Input Pin Capacitance

Cin

Output Pin Capacitance

Cout

Input Pin Inductance

Lin

W83194BR-648

- 16 -

9.3 Skew Group Timing Clock

VDDR = VDDZ = VDDA = VDDC = VDDAGP = VDDPCI = VDDSD = VDD48 = 3.3V

�

5 %, TA = 0

�

C to +70

�

C, Cl = 10pF

PARAMETER MIN.

TYP.

MAX.

UNITS

TEST

CONDITIONS

CPU to SDRAM Skew

-2 0 2 nS

CPU Crossing point to SDRAM at
1.5V

CPU (early) to AGP Skew

CPU Crossing point to AGP at 1.5V

CPU (early) to ZCLK Skew

CPU Crossing point to ZCLK at 1.5V

CPU (early) to PCI Skew

CPU Crossing point to PCI at 1.5V

CPU to CPU Skew

150

Crossing

point

AGP to AGP Skew

175

Measured at 1.5V

ZCLK to ZCLK Skew

175

Measured at 1.5V

PCI to PCI Skew

500

Measured at 1.5V

48 MHz to 48 MHz Skew

1000

Measured at 1.5V

REF to REF Skew

500

Measured at 1.5V

9.4 CPU 0.7V Electrical Characteristics

VDDA = VDDC= 3.3V

�

5 %, TA = 0

�

C to +70

�

C, Test load Rs = 33, Rp = 49.9 Cl = 10pF, Vol = 0.14V, Voh = 0.56V, Vr = 475,

IRE = 2.32mA, Ioh = 6*IREF

PARAMETER MIN.

MAX.

UNITS

TEST

CONDITIONS

Rise Time

175

700

100 to 200 MHz

Fall Time

175 700 pS 100

200

MHz

Absolute Crossing Point Voltages

250 550 mV 100

200

MHz

Cycle to Cycle jitter

125

100 to 200 MHz

Duty Cycle

45 55 % 100

200

MHz

9.5 CPU 1.0V Electrical Characteristics

VDDA = VDDC= 3.3V

�

5 %, TA = 0

�

C to +70

�

C, Test load Rs = 33, Rp = 49.9 Cl = 10pF, Vol = 0.2V, Voh = 0.8V, Vr = 221,

IREF = 5.0 mA, Ioh = 4*IREF

PARAMETER MIN.

MAX.

UNITS

TEST

CONDITIONS

Rise Time

300

600

100 to 200 MHz

Fall Time

300 600 pS 100

200

MHz

Absolute Crossing Point Voltages

510 760 mV 100

200

MHz

Cycle to Cycle Jitter

200

100 to 200 MHz

Duty Cycle

45 55 % 100

200

MHz

W83194BR-648

Publication Release Date: April 13, 2005

- 17 -

Revision 1.1

9.6 AGP Electrical Characteristics

VDDAGP= 3.3V

�

5 %, TA = 0

�

C to +70

�

C, Test load, C = 10pF,

PARAMETER MIN.

MAX.

UNITS

TEST

CONDITIONS

Rise Time

500

1600

Measure from 0.4V to 2.4V

Fall Time

500

1600

Measure from 2.4V to 0.4V

Cycle to Cycle Jitter

250

Measure 1.5V point

Duty Cycle

45 55 %

Pull-Up Current Min.

-33

Vout = 1.0V

Pull-Up Current Max.

-33

Vout = 3.135V

Pull-Down Current Min.

Vout = 1.95V

Pull-Down Current Max.

Vout = 0.4V

9.7 PCI Electrical Characteristics

VDDPCI = 3.3V

�

5 %, TA = 0

�

C to +70

�

C, Test load, Cl = 10pF

PARAMETER MIN.

MAX.

UNITS

TEST

CONDITIONS

Rise Time

500

2000

Measure from 0.4V to 2.4V

Fall Time

500

2000

Measure from 2.4V to 0.4V

Cycle to Cycle Jitter

500

Measure 1.5V point

Duty Cycle

45 55 %

Pull-Up Current Min.

-33

Vout = 1.0V

Pull-Up Current Max.

-33

Vout = 3.135V

Pull-Down Current Min.

Vout = 1.95V

Pull-Down Current Max.

Vout = 0.4V

9.8 ZCLK Electrical Characteristics

VDDZ = 3.3V

�

5 %, TA = 0

�

C to +70

�

C, Test load, Cl = 10pF

PARAMETER MIN.

MAX.

UNITS

TEST

CONDITIONS

Rise Time

500

1600

Measure from 0.4V to 2.4V

Fall Time

500

1600

Measure from 2.4V to 0.4V

Cycle to Cycle Jitter

250

Measure 1.5V point

Duty Cycle

45 55 %

Pull-Up Current Min.

-33

Vout = 1.0V

Pull-Up Current Max.

-33

Vout = 3.135V

Pull-Down Current Min.

Vout = 1.95V

Pull-Down Current Max.

Vout = 0.4V

W83194BR-648

- 18 -

9.9 SDRAM Electrical Characteristics

VDDSD= 3.3V

�

5 %, TA = 0

�

C to +70

�

C, Test load, Cl = 10pF

PARAMETER MIN.

MAX.

UNITS

TEST

CONDITIONS

Rise Time

500

1600

Measure from 0.4V to 2.4V

Fall Time

500

1600

Measure from 2.4V to 0.4V

Cycle to Cycle Jitter

250

Measure 1.5V point

Duty Cycle

45 55 %

Pull-Up Current Min.

-33

Vout = 1.0V

Pull-Up Current Max.

-33

Vout = 3.135V

Pull-Down Current Min.

Vout = 1.95V

Pull-Down Current Max.

Vout = 0.4V

9.10 24M, 48M Electrical Characteristics

VDD48 = 3.3V

�

5 %, TA = 0

�

C to +70

�

C, Test load, Cl = 10pF

PARAMETER MIN.

MAX.

UNITS

TEST

CONDITIONS

Rise Time

1000

4000

Measure from 0.4V to 2.4V

Fall Time

1000

4000

Measure from 2.4V to 0.4V

Long Term Jitter

500

Measure 1.5V point

Duty Cycle

45 55 %

Pull-Up Current Min.

-29

Vout = 1.0V

Pull-Up Current Max.

-23

Vout = 3.135V

Pull-Down Current Min.

Vout = 1.95V

Pull-Down Current Max.

Vout = 0.4V

9.11 REF Electrical Characteristics

VDD48 = 3.3V

�

5 %, TA = 0

�

C to +70

�

C, Test load, Cl = 10pF

PARAMETER MIN.

MAX.

UNITS

TEST

CONDITIONS

Rise Time

1000

4000

Measure from 0.4V to 2.4V

Fall Time

1000

4000

Measure from 2.4V to 0.4V

Cycle to Cycle Jitter

1000

Measure 1.5V point

Duty Cycle

45 55 %

Pull-Up Current Min.

-33

Vout=1.0V

Pull-Up Current Max.

-33

Vout=3.135V

Pull-Down Current Min.

Vout=1.95V

Pull-Down Current Max.

Vout=0.4V

W83194BR-648

Publication Release Date: April 13, 2005

- 19 -

Revision 1.1

10. POWER MANAGEMENT TIMING

10.1 CPU_STOP# Timing Diagram

CPUCLK

(Internal)

PCICLK

(Internal)

PCICLK_F

CPU_STOP#

CPUCLK[0:3]

SDRAM

For synchronous Chipset, CPU_STOP# pin is an asynchronous " active low " input pin used to stop
the CPU clocks for low power operation. This pin is asserted synchronously by the external control
logic at the rising edge of free running PCI clock (PCICLK_F). All other clocks will continue to run
while the CPU clocks are stopped. The CPU clocks will always be stopped in a low state and resume
output with full pulse width. In this case, CPU locks on latency" is less than 4 CPU clocks and

locks off latency" is less then 4 CPU clocks.

10.2 PCI_STOP# Timing Diagram

CPUCLK

(Internal)

PCICLK

(Internal)

PCICLK_F

PCI_STOP#

PCICLK[0:5]

For synchronous Chipset, PCI_STOP# pin is an asynchronous Active low" input pin used to stop the
PCICLK [0:4] for low power operation. This pin is asserted synchronously by the external control logic
at the rising edge of free running PCI clock (PCICLK_F). All other clocks will continue to run while the
PCI clocks are stopped. The PCI clocks will always be stopped in a low state and resume output with
full pulse width. In this case, PCI locks on latency" is less than 2 PCI clocks and locks off latency" is
less then 2 PCI clocks.

W83194BR-648

- 22 -

14. REVISION HISTORY

VERSION DATE

PAGE

DESCRIPTION

n.a.

All of the versions before 0.50 are for internal
use.

0.5 02/7/03 17~22

Add AC/DC Specifications and Power
management

0.6 2/21/03

All

Update

new

form

0.7 12/18/03 7~11,

Correction IC version, add register default
value and correction some description and
default value

1.0

05/06/04

Update on web

1.1 04/13/2005

22 Add

disclaimer

Important Notice

Winbond products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal
instruments, combustion control instruments, or for other applications intended to support or
sustain life. Further more, Winbond products are not intended for applications wherein failure
of Winbond products could result or lead to a situation wherein personal injury, death or
severe property or environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sales.

Headquarters

No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5665577
http://www.winbond.com.tw/

Taipei Office

TEL: 886-2-8177-7168
FAX: 886-2-8751-3579

Winbond Electronics Corporation America

2727 North First Street, San Jose,
CA 95134, U.S.A.
TEL: 1-408-9436666
FAX: 1-408-5441798

Winbond Electronics (H.K.) Ltd.

No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong

FAX: 852-27552064

Unit 9-15, 22F, Millennium City,

TEL: 852-27513100

Please note that all data and specifications are subject to change without notice.

All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.

Winbond Electronics (Shanghai) Ltd.

200336 China

FAX: 86-21-62365998

27F, 2299 Yan An W. Rd. Shanghai,

TEL: 86-21-62365999

Winbond Electronics Corporation Japan

Shinyokohama Kohoku-ku,
Yokohama, 222-0033

FAX: 81-45-4781800

7F Daini-ueno BLDG, 3-7-18

TEL: 81-45-4781881

9F, No.480, Rueiguang Rd.,

Neihu District, Taipei, 114,

Taiwan, R.O.C.

Электронный компонент: W83194BR-648