W78ERD2 Data Sheet

8-BIT MICROCONTROLLER

Publication Release Date: April 20, 2005

- 1 -

Revision A4

Table of Contents-

GENERAL DESCRIPTION ......................................................................................................... 3

FEATURES ................................................................................................................................. 3

PIN CONFIGURATIONS............................................................................................................. 4

PIN DESCRIPTION..................................................................................................................... 5

BLOCK DIAGRAM ...................................................................................................................... 6

FUNCTIONAL DESCRIPTION.................................................................................................... 7

6.1

RAM ................................................................................................................................... 7

6.2

Timers 0, 1 and 2............................................................................................................... 7

6.3

Clock .................................................................................................................................. 8

6.4

Crystal Oscillator................................................................................................................ 8

6.5

External Clock.................................................................................................................... 8

6.6

Power Management........................................................................................................... 8

6.7

Reduce EMI Emission ....................................................................................................... 8

6.8

Reset.................................................................................................................................. 8

SPECIAL FUNCTION REGISTER .............................................................................................. 9

PORT 4 AND BASE ADDRESS REGISTERS.......................................................................... 33

INTERRUPT.............................................................................................................................. 35

10.

ENHANCED FULL DUPLEX SERIAL PORT............................................................................ 36

10.1

MODE 0 ....................................................................................................................... 36

10.2

MODE 1 ....................................................................................................................... 37

10.3

MODE 2 ....................................................................................................................... 38

10.4

MODE 3 ....................................................................................................................... 39

10.5

Framing Error Detection............................................................................................... 41

10.6

Multiprocessor Communications.................................................................................. 41

11.

PROGRAMMABLE COUNTER ARRAY (PCA) ........................................................................ 43

11.1

PCA Capture Mode ...................................................................................................... 46

11.2

16-bit Software Timer Comparator Mode .................................................................... 46

11.3

High Speed Output Mode ............................................................................................ 47

11.4

Pulse Width Modulator Mode....................................................................................... 47

11.5

Watchdog Timer........................................................................................................... 48

W78ERD2

- 2 -

12.

HARDWARE WATCHDOG TIMER (ONE-TIME ENABLED WITH RESET-OUT) ................... 48

12.1

Using the WDT............................................................................................................. 48

13.

DUAL DPTR .............................................................................................................................. 49

14.

IN-SYSTEM PROGRAMMING (ISP) MODE ............................................................................ 49

15.

H/W REBOOT MODE (BOOT FROM LDROM)........................................................................ 51

16.

OPTION BITS ........................................................................................................................... 56

17.

ELECTRICAL CHARACTERISTICS ......................................................................................... 57

17.1

Absolute Maximum Ratings ......................................................................................... 57

17.2

D.C. Characteristics ..................................................................................................... 57

17.3

A.C. Characteristics ..................................................................................................... 59

18.

TIMING WAVEFORMS ............................................................................................................. 61

19.

TYPICAL APPLICATION CIRCUITS ........................................................................................ 63

19.1

External Program Memory and Crystal........................................................................ 63

19.2

Expanded External Data Memory and Oscillator......................................................... 64

20.

PACKAGE DIMENSIONS ......................................................................................................... 65

21.

APPLICATION NOTE ............................................................................................................... 67

21.1

In-system Programming Software Examples............................................................... 67

21.2

How to Use Programmable Counter Array .................................................................. 71

22.

VERSION HISTORY ................................................................................................................. 72

W78ERD2

Publication Release Date: April 20, 2005

- 3 -

Revision A4

1. GENERAL DESCRIPTION

The W78ERD2 is an 8-bit microcontroller which has an in-system programmable Flash EPROM for
firmware updating. The instruction set of the W78ERD2 is fully compatible with the standard 8052. The
W78ERD2 contains a 64K bytes of main Flash EPROM and a 4K bytes of auxiliary Flash EPROM
which allows the contents of the 64KB main Flash EPROM to be updated by the loader program
located at the 4KB auxiliary Flash EPROM ROM; 256 bytes of on-chip RAM, 1K AUX-RAM; four 8-bit
bi-directional and bit-addressable I/O ports; an additional 4-bit port P4; three 16-bit timer/counters; a
serial port. These peripherals are supported by a nine sources four level interrupt capability. To
facilitate programming and verification, the Flash EPROM inside the W78ERD2 allows the program
memory to be programmed and read electronically. Once the code is confirmed, the user can protect
the code for security.
The W78ERD2 microcontroller has two power reduction modes, idle mode and power-down mode,
both of which are software selectable. The idle mode turns off the processor clock but allows for
continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
processor.

2. FEATURES

�

8-bit CMOS microcontroller

�

Pin compatible with standard 80C52

�

Instruction-set compatible with MCS-51

�

Four 8-bit I/O Ports

�

One extra 4-bit I/O port, interrupt, chip select function

�

Three 16-bit Timers

�

Programmable clock out

�

Programmable Counter Array (PCA): PWM, Capture, Compare, Watchdog

�

9 interrupt sources with 4 levels of priority

�

One enhanced full duplex serial port with framing error detection and automatic address

recognition

�

64KB In-system Programmable Flash EPROM (AP Flash EPRAOM)

�

4KB Auxiliary Flash EPROM for loader program (LD Flash EPROM)

�

256+1K bytes of on-chip RAM. (Including 1K bytes of AUX-RAM, software selectable)

�

Software Reset

�

12 clocks per machine cycle operation (default). Speed up to 40 MHz.

�

6 clocks per machine cycle operation which is set by the writer. Speed up to 20 MHz.

�

2 DPTR registers

�

Low EMI (inhibit ALE)

�

Built-in power management with idle mode and power down mode

�

Code protection

�

Packages:

DIP 40: W78ERD2A40DN

PLCC 44: W78ERD2A40PN

QFP 44: W78ERD2A40FN

W78ERD2

- 4 -

3. PIN CONFIGURATIONS

VDD

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

P0.0, AD0
P0.1, AD1
P0.2, AD2
P0.3, AD3
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7

EA
ALE

PSEN

P2.5, A13

P2.6, A14

P2.7, A15

P2.0, A8

P2.1, A9

P2.2, A10

P2.3, A11

P2.4, A12

T2, P1.0

40-Pin DIP

P1.2
P1.3
P1.4
P1.5
P1.6

RXD, P3.0
TXD, P3.1

P1.7
RST

INT0, P3.2
INT1, P3.3

T0, P3.4

T1, P3.5

WR, P3.6

RD, P3.7

XTAL1

XTAL2

VSS

T2EX, P1.1

44-Pin PLCC

1 44 43 42 41

39
38
37
36
35
34
33
32
31
30
29

P1.5
P1.6
P1.7

RST

RXD, P3.0

TXD, P3.1

INT0, P3.2
INT1, P3.3

T0, P3.4

T1, P3.5

P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA

ALE

PSEN
P2.7, A15
P2.6, A14
P2.5, A13

P4.1

INT2, P4.3

44-Pin QFP

40 39 38 37 36 35

44 43 42 41

33
32
31
30
29
28
27
26
25
24
23

P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA

ALE

PSEN
P2.7, A15
P2.6, A14
P2.5, A13

P1.5
P1.6
P1.7

RST

RXD, P3.0

TXD, P3.1

INT0, P3.2
INT1, P3.3

T0, P3.4

T1, P3.5

P4.1

INT2, P4.3

W78ERD2

Publication Release Date: April 20, 2005

- 5 -

Revision A4

4. PIN DESCRIPTION

SYMBOL TYPE

DESCRIPTIONS

EXTERNAL ACCESS ENABLE: This pin forces the processor to execute the
external ROM. The ROM address and data will not be presented on the bus if
the EA pin is high.

PSEN

O H PROGRAM STORE ENABLE: PSEN enables the external ROM data in the

Port 0 address/data bus. When internal ROM access is performed, no PSEN
strobe signal outputs originate from this pin.

ALE

O H ADDRESS LATCH ENABLE: ALE is used to enable the address latch that

separates the address from the data on Port 0. ALE runs at 1/6th of the
oscillator frequency.

RST

I L RESET: A high on this pin for two machine cycles while the oscillator is

running resets the device.

XTAL1

CRYSTAL 1: This is the crystal oscillator input. This pin may be driven by an
external clock.

XTAL2

CRYSTAL 2: This is the crystal oscillator output. It is the inversion of XTAL1.

GROUND:

ground

potential.

POWER SUPPLY: Supply voltage for operation.

P0.0

P0.7 I/O D PORT 0: Function is the same as that of standard 8052.

P1.0

P1.7 I/O H PORT 1: Function is the same as that of standard 8052.

P2.0

P2.7 I/O H PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also

provides the upper address bits for accesses to external memory.

P3.0

P3.7 I/O H PORT 3: Function is the same as that of the standard 8052.

P4.0

P4.3 I/O H PORT 4: A bi-directional I/O. See details below.

* Note: TYPE I: input, O: output, I/O: bi-directional, H: pull-high, L: pull-low, D: open drain

PORT4

Another bit-addressable port P4 is also available and only 4 bits (P4<3:0>) can be used. This port
address is located at 0D8H with the same function as that of port P1.
Example:

P4 REG 0D8H

MOV P4, #0AH ; Output data "A" through P4.0

P4.3.

MOV A, P4 ; Read P4 status to Accumulator.
ORL P4,

#00000001B

ANL P4,

#11111110B

W78ERD2

- 6 -

5. BLOCK DIAGRAM

S S

P 3 .0

P 3 .7

P 1 .0

P 1 .7

A L U

P o rt 0

L a tc h

P o rt 1

L a tc h

T im e r

P o rt

U A R T

X T A L 1

P S E N

A L E

V s s

V C C

R S T

X T A L 2

O s c illa to r

In te rru p t

P S W

In s tru c tio n

D e c o d e r

S e q u e n c e r

R e s e t B lo c k

B u s & C lo c k

C o n tro lle r

S F R R A M

A d d re s s

P o w e r c o n tro l

2 5 6 b y te s

R A M & S F R

S ta c k

P o in te r

A d d r. R e g .

In c r e m e n to r

P C

D P T R

T e m p R e g .

T 2

T 1

A C C

P o rt 3

L a tc h

P o rt 4

L a tc h

P o rt

P o rt 2

L a tc h

P 4 .0

P 4 .3

P o rt

P 2 .0

P 2 .7

P 0 .0

P 0 .7

6 4 K B

A P F la s h

4 K B

L D F la s h

1 K b y te s
A U X -R A M

E P R O M

W78ERD2

Publication Release Date: April 20, 2005

- 7 -

Revision A4

6. FUNCTIONAL DESCRIPTION

The W78ERD2 architecture consists of a core controller surrounded by various registers, four general
purpose I/O ports, one special purpose programmable 4-bits I/O port, 256 bytes of RAM, 1K AUX-
RAM, three timer/counters, a serial port and an internal 74373 latch and 74244 buffer which can be
switched to port2. The processor supports 111 different opcodes and references both a 64K program
address space and a 64K data storage space.

6.1 RAM

The internal data RAM in the W78ERD2 is 256 + 1K bytes. It is divided into two banks: 256 bytes of
scratchpad RAM and 1K bytes of AUX-RAM. These RAMs are addressed by different ways.

�

RAM 0H

7FH can be addressed directly and indirectly as the same as in 8051. Address pointers

are

R0 and R1 of the selected register bank.

�

RAM 80H

FFH can only be addressed indirectly as the same as in 8051. Address pointers are R0,

R1 of the selected registers bank.

�

AUX-RAM 0H

3FFH is addressed indirectly as the same way to access external data memory with

the MOVX instruction. Address pointer are R0 and R1 of the selected register bank and DPTR
register. An access to external data memory locations higher than 3FFH will be performed with the
MOVX instruction in the same way as in the 8051. The AUX-RAM will be enabled after a reset.
Clearing the bit 1 in AUXR register will enable the access to AUX-RAM. When AUX-RAM is enabled
the instructions of "MOVX @Ri" will always access to on-chip AUX-RAM. When executing from
internal program memory, an access to AUX-RAM will not affect the Ports P0, P2, WR and RD .
Example,

ANL AUXR,

#11111101B

;

Enable

AUX-RAM

MOV

DPTR,

#1234H

MOV A, #56H
MOVX @DPTR,

;

Write

56h

data to external memory at address 1234H

MOV XRAMAH, #02H ; Only 2 LSB effective
MOV R0, #34H
MOV

@R0 ;

Read

AUX-RAM

data

address

0234H

6.2 Timers 0, 1 and 2

Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0,
TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide
control functions for timers 0, 1. The T2CON register provides control functions for Timer 2. RCAP2H
and RCAP2L are used as reload/capture registers for Timer 2. The operations of Timer 0 and Timer 1
are the same as in the W78C51. Timer 2 is a 16-bit timer/counter that is configured and controlled by
the T2CON register. Like Timers 0 and 1, Timer 2 can operate as either an external event counter or
as an internal timer, depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating
modes: capture, auto-reload, and baud rate generator. The clock speed at capture or auto-reload
mode is the same as that of Timers 0 and 1.

W78ERD2

- 8 -

6.3 Clock

The W78ERD2 is designed with either a crystal oscillator or an external clock.

6.4 Crystal Oscillator

The W78ERD2 incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be
connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each
pin to ground, and a resistor must also be connected from XTAL1 to XTAL2 to provide a DC bias
when the crystal frequency is above 24 MHz.

6.5 External Clock

An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The
XTAL1 input is a CMOS-type input, as required by the crystal oscillator. As a result, the external clock
signal should have an input one level of greater than 3.5 volts.

6.6 Power Management

6.6.1 Idle Mode

Setting the IDL bit in the PCON register enters the idle mode. In the idle mode, the internal clock to the
processor is stopped. The peripherals and the interrupt logic continue to be clocked. The processor
will exit idle mode when either an interrupt or a reset occurs.

6.6.2 Power-down

Mode

When the PD bit in the PCON register is set, the processor enters the power-down mode. In this mode
all of the clocks are stopped, including the oscillator. To exit from power-down mode is by a hardware
reset or external interrupts INT0 to INT1 when enabled and set to level triggered.

6.7 Reduce EMI Emission

If the crystal frequency is under 25 MHz, please option.b7 is set to 0 by the writer. Please refer option
bits description to operate this bit.

6.8 Reset

The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two
machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to
deglitch the reset line when the W78ERD2 is used with an external RC network. The reset logic also
has a special glitch removal circuit that ignores glitches on the reset line. During reset, the ports are
initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit 4) to 00H, and all of the
other SFR registers except SBUF to 00H. SBUF is not reset.

W78ERD2

Publication Release Date: April 20, 2005

- 9 -

Revision A4

7. SPECIAL FUNCTION REGISTER

W78E51RD2 Special Function Registers (SFRs) and Reset Values

00000000

CCAP0H

00000000

CCAP1H

00000000

CCAP2H

00000000

CCAP3H

00000000

CCAP4H

00000000

CHPENR

00000000

+P4

xxxx1111

00000000

CCAP0L

00000000

CCAP1L

00000000

CCAP2L

00000000

CCAP3L

00000000

CCAP4L

00000000

+ACC

00000000

CCON

x0000000

CMOD

00xxx000

CCAPM0

x0000000

CCAPM1

x0000000

CCAPM2

x0000000

CCAPM3

x0000000

CCAPM4

x0000000

CKCON

xx000xx1

+PSW

00000000

+T2CON

00000000

T2MOD

xxxxxx00

RCAP2L

00000000

RCAP2H

00000000

TL2

00000000

TH2

00000000

XICON

00000000

XICONH

0xxx0xxx

P4CONA

00000000

P4CONB

00000000

SFRAL

00000000

SFRAH

00000000

SFRFD

00000000

SFRCN

00000000

+IP

x0000000

SADEN

00000000

CHPCON

000xx000

+P3

00000000

P43AL

00000000

P43AH

00000000

IPH

x0000000

+IE

00000000

SADDR

00000000

P42AL

00000000

P42AH

00000000

P4CSIN

00000000

+P2

11111111

XRAMAH

00000000

AUXR1

xxxxx0x0

WDTRST

00000000

+SCON

00000000

SBUF

xxxxxxxx

P2EAL

00000000

P2EAH

00000000

+P1

11111111

P41AL

00000000

P41AH

00000000

+TCON

00000000

TMOD

00000000

TL0

00000000

TL1

00000000

TH0

00000000

TH1

00000000

AUXR

00000000

+P0

11111111

00000111

DPL

00000000

DPH

00000000

P40AL

00000000

P40AH

00000000

PORT

00000000

PCON

00110000

Notes:

1. The SFRs marked with a plus sign(+) are both byte- and bit-addressable.

2. The text of SFR with bold type characters are extension function registers.

W78ERD2

- 10 -

Port 0

Bit: 7 6 5 4 3 2 1 0

P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0

Mnemonic:

Address:

80h

Port 0 is an open-drain bi-directional I/O port. This port also provides a multiplexed low order
address/data bus during accesses to external memory.

Stack Pointer

Bit: 7 6 5 4 3 2 1 0

SP.7 SP.6 SP.5 SP.4 SP.3 SP.2 SP.1 SP.0

Mnemonic:

SP Address:

81h

The Stack Pointer stores the Scratchpad RAM address where the stack begins. In other words, it
always points to the top of the stack.

Data Pointer Low

Bit: 7 6 5 4 3 2 1 0

DPL.7

DPL.6

DPL.5

DPL.4

DPL.3

DPL.2

DPL.1

DPL.0

Mnemonic:

DPL

Address:

82h

This is the low byte of the standard 8052 16-bit data pointer.

Data Pointer High

Bit: 7 6 5 4 3 2 1 0

DPH.7

DPH.6

DPH.5

DPH.4

DPH.3

DPH.2

DPH.1

DPH.0

Mnemonic:

DPH Address:

83h

This is the high byte of the standard 8052 16-bit data pointer.

Port 4.0 Low Address Comparator

Bit: 7 6 5 4 3 2 1 0

P40AL.7

P40AL.6

P40AL.5 P40AL.4 P40AL.3 P40AL.2 P40AL.1

P40AL.0

Mnemonic:

P40AL Address:

84h

W78ERD2

Publication Release Date: April 20, 2005

- 11 -

Revision A4

Port 4.0 High Address Comparator

Bit: 7 6 5 4 3 2 1 0

P40AH.7

P40AH.6

P40AH.5 P40AH.4 P40AH.3 P40AH.2 P40AH.1

P40AH.0

Mnemonic:

P40AH Address:

85h

Port Option Register

Bit: 7 6 5 4 3 2 1 0

- -

- - - -

P0PH

Mnemonic:

POPT

Address:

86h

BIT NAME

FUNCTION

7 -

Reserve

6 -

Reserve

5 -

Reserve

4 -

Reserve

3 -

Reserve

2 -

Reserve

1 -

Reserve

0 P0PH

0: Disable Port 0 weak up.
1: Enable Port 0 weak up. The pins of Port 0 can be configured with either the

open drain or standard port with internal pull-up. By the default, Port 0 is an
open drain bi-directional I/O port. When the P0UP bit in the POPT register is
set, the pins of port 0 will perform a bi-directional I/O port with internal pull-up
that is structurally the same Port2.

Power Control

Bit: 7 6 5 4 3 2 1 0

SMOD

SMOD0

POR GF1 GF0 PD IDL

Mnemonic:

PCON

Address:

87h

BIT NAME

FUNCTION

SMOD 1: This bit doubles the serial port baud rate in mode 1, 2, and 3.

6 SMOD0

0: Framing Error Detection Disable. SCON.7 acts as per the standard 8052

function.

1: Framing Error Detection Enable, then and SCON.7 indicates a Frame Error and

acts as the FE (FE_1) flag.

W78ERD2

- 12 -

Continued

BIT NAME

FUNCTION

5 - Reserve

4 POF

0: Cleared by software.
1: Set automatically when a power-on reset has occurred.

GF1

These two bits are general purpose user flags.

GF0

These two bits are general purpose user flags.

1 PD

1: Setting this bit causes the Chip to go into the POWER DOWN mode. In this

mode all the clocks are stopped and program execution is frozen.

0 IDL

1: Setting this bit causes the Chip to go into the IDLE mode. In this mode the clocks

to the CPU are stopped, so program execution is frozen. But the clock to the
serial, timer and interrupt blocks is not stopped, and these blocks continue
operating.

Timer Control

Bit: 7 6 5 4 3 2 1 0

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

Mnemonic:

TCON

Address:

88h

BIT NAME

FUNCTION

7 TF1

Timer 1 overflow flag: This bit is set when Timer 1 overflows. It is cleared
automatically when the program does a timer 1 interrupt service routine. Software
can also set or clear this bit.

6 TR1

Timer 1 run control: This bit is set or cleared by software to turn timer/counter on or
off.

5 TF0

Timer 0 overflow flag: This bit is set when Timer 0 overflows. It is cleared
automatically when the program does a timer 0 interrupt service routine. Software
can also set or clear this bit.

4 TR0

Timer 0 run control: This bit is set or cleared by software to turn timer/counter on or
off.

3 IE1

Interrupt 1 Edge Detect: Set by hardware when an edge/level is detected on INT1 .
This bit is cleared by hardware when the service routine is vectored to only if the
interrupt was edge triggered. Otherwise it follows the pin.

2 IT1

Interrupt 1 type control: Set/cleared by software to specify falling edge/ low level
triggered external inputs.

1 IE0

Interrupt 0 Edge Detect: Set by hardware when an edge/level is detected on INT0 .
This bit is cleared by hardware when the service routine is vectored to only if the
interrupt was edge triggered. Otherwise it follows the pin.

0 IT0

Interrupt 0 type control: Set/cleared by software to specify falling edge/ low level
triggered external inputs.

W78ERD2

Publication Release Date: April 20, 2005

- 13 -

Revision A4

Timer Mode Control

Bit: 7 6 5 4 3 2 1 0

GATE T

M1 M0

GATE

M1 M0

Mnemonic: TMOD Address:

89h

BIT NAME

FUNCTION

7 GATE

Gating control: When this bit is set, Timer/counter x is enabled only while INTx pin
is high and TRx control bit is set. When cleared, Timer x is enabled whenever TRx
control bit is set.

Timer or Counter Select: When cleared, the timer is incremented by internal clocks.
When set, the timer counts high-to-low edges of the Tx pin.

Mode Select bits:

3 GATE

Gating control: When this bit is set, Timer/counter x is enabled only while INTx pin
is high and TRx control bit is set. When cleared, Timer x is enabled whenever TRx
control bit is set.

Timer or Counter Select: When cleared, the timer is incremented by internal clocks.
When set, the timer counts high-to-low edges of the Tx pin.

Mode Select bits:

M1, M0: Mode Select bits:

M1 M0 Mode

Mode 0: 8-bits with 5-bit prescale.

Mode 1: 18-bits, no prescale.

Mode 2: 8-bits with auto-reload from THx

Mode 3: (Timer 0) TL0 is an 8-bit timer/counter controlled by the standard Timer 0
control bits. TH0 is a 8-bit timer only controlled by Timer 1 control bits. (Timer 1)
Timer/counter is stopped.

Timer 0 LSB

Bit: 7 6 5 4 3 2 1 0

TL0.7 TL0.6 TL0.5

TL0.4

TL0.3

TL0.2

TL0.1 TL0.0

Mnemonic:

TL0 Address:

8Ah

TL0.7-0: Timer 0 Low byte

W78ERD2

Publication Release Date: April 20, 2005

- 15 -

Revision A4

Port 1

Bit: 7 6 5 4 3 2 1 0

P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0

Mnemonic:

Address:

90h

P1.7-0: General purpose Input/Output port. Most instructions will read the port pins in case of a port
read access, however in case of read-modify-write instructions, the port latch is read. These alternate
functions are described below:

Port 4.1 Low Address Comparator

Bit: 7 6 5 4 3 2 1 0

P41AL.7 P41AL.6 P41AL.5 P41AL.4 P41AL.3 P41AL.2 P41AL.1 P41AL.0

Mnemonic:

P41AL Address:

94h

Port 4.1 High Address Comparator

Bit: 7 6 5 4 3 2 1 0

P41AH.7

P41AH.6

P41AH.5 P41AH.4 P41AH.3 P41AH.2 P41AH.1 P41AH.0

Mnemonic:

P41AH Address:

95h

Serial Port Control

Bit: 7 6 5 4 3 2 1 0

SM0/FE

SM1 SM2 REN TB8 RB8 TI RI

Mnemonic:

SCON

Address:

98h

BIT NAME

FUNCTION

7 SM0/FE

Serial port 0, Mode 0 bit or Framing Error Flag: The SMOD0 bit in PCON SFR
determines whether this bit acts as SM0 or as FE. The operation of SM0 is
described below. When used as FE, this bit will be set to indicate an invalid stop bit.
This bit must be manually cleared in software to clear the FE condition.

6 SM1

Serial port Mode bit 1:
Mode: SM0 SM1 Description Length Baud rate
0 0 0 Synchronous 8 4/12 Tclk
1 0 1 Asynchronous 10 Variable
2 1 0 Asynchronous 11 64/32 Tclk
3 1 1 Asynchronous 11 Variable

W78ERD2

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Continued

BIT NAME

FUNCTION

5 SM2

Multiple processors communication. Setting this bit to 1 enables the multiprocessor
communication feature in mode 2 and 3. In mode 2 or 3, if SM2 is set to 1, then RI
will not be activated if the received 9th data bit (RB8) is 0. In mode 1, if SM2 = 1,
then RI will not be activated if a valid stop bit was not received. In mode 0, the SM2
bit controls the serial port clock. If set to 0, then the serial port runs at a divide by
12 clock of the oscillator. This gives compatibility with the standard 8052.

4 REN

Receive enable: When set to 1 serial reception is enabled, otherwise reception is
disabled.

3 TB8

This is the 9th bit to be transmitted in modes 2 and 3. This bit is set and cleared by
software as desired.

2 RB8

In modes 2 and 3 this is the received 9th data bit. In mode 1, if SM2 = 0, RB8 is the
stop bit that was received. In mode 0 it has no function.

1 TI

Transmit interrupt flag: This flag is set by hardware at the end of the 8th bit time in
mode 0, or at the beginning of the stop bit in all other modes during serial
transmission. This bit must be cleared by software.

0 RI

Receive interrupt flag: This flag is set by hardware at the end of the 8th bit time in
mode 0, or halfway through the stop bits time in the other modes during serial
reception. However the restrictions of SM2 apply to this bit. This bit can be cleared
only by software.

Serial Data Buffer

Bit: 7 6 5 4 3 2 1 0

SBUF.7 SBUF.6 SBUF.5 SBUF.4 SBUF.3 SBUF.2 SBUF.1 SBUF.0

Mnemonic:

SBUF Address:

99h

BIT NAME

FUNCTION

7~0 SBUF

Serial data on the serial port 1 is read from or written to this location. It actually
consists of two separate internal 8-bit registers. One is the receive resister, and the
other is the transmit buffer. Any read access gets data from the receive data buffer,
while write access is to the transmit data buffer.

W78ERD2

- 18 -

Watchdog Timer Reset Register

Bit: 7 6 5 4 3 2 1 0

WDTRS

T.7

WDTRS

T.6

WDTRS

T.5

WDTRS

T.4

WDTRS

T.3

WDTRS

T.2

WDTRS

T.1

WDTRS

T.0

Mnemonic: WDTRST Address: A6h

Interrupt Enable

Bit: 7 6 5 4 3 2 1 0

ET2

ET1

EX1

ET0

EX0

Mnemonic:

IE Address:

A8h

BIT NAME

FUNCTION

Global enable. Enable/disable all interrupts except for PFI.

6 EC Enable

PCA

interrupt.

ET2

Enable Timer 2 interrupt.

Enable Serial Port 0 interrupt.

ET1

Enable Timer 1 interrupt.

EX1

Enable external interrupt 1.

ET0

Enable Timer 0 interrupt.

EX0

Enable external interrupt 0.

SLAVE ADDRESS

Bit: 7 6 5 4 3 2 1 0

Mnemonic:

SADDR Address:

A9h

BIT NAME

FUNCTION

7 SADDR

The SADDR should be programmed to the given or broadcast address for serial
port 0 to which the slave processor is designated.

Port 4.2 Low Address Comparator

Bit: 7 6 5 4 3 2 1 0

P42AL.7 P42AL.6 P42AL.5 P42AL.4 P42AL.3 P42AL.2 P42AL.1 P42AL.0

Mnemonic:

P42AL Address:

ACh

W78ERD2

- 20 -

Interrupt Priority High

Bit: 7 6 5 4 3 2 1 0

PPCH

PT2H

PSH

PT1H

PX1H

PT0H

PX0H

Mnemonic:

IPH Address:

B8h

BIT NAME

FUNCTION

This bit is un-implemented and will read high.

PPCH

1: To set interrupt priority of PCA is highest priority level.

PT2H

1: To set interrupt priority of Timer 2 is highest priority level.

PSH

1: To set interrupt priority of Serial port 0 is highest priority level.

PT1H

1: To set interrupt priority of Serial port 0 is highest priority level.

PX1H

1: To set interrupt priority of External interrupt 1 is highest priority level.

PT0H

1: To set interrupt priority of Timer 0 is highest priority level.

PX0H

1: To set interrupt priority of External interrupt 0 is highest priority level.

Interrupt Priority

Bit: 7 6 5 4 3 2 1 0

PPC

PT2

PT1

PX1

PT0

PX0

Mnemonic:

Address:

B8h

BIT NAME

FUNCTION

This bit is un-implemented and will read high.

PPC

1: To set interrupt priority of PCA is higher priority level.

PT2

1: To set interrupt priority of Timer 2 is higher priority level.

1: To set interrupt priority of Serial port 0 is higher priority level.

PT1

1: To set interrupt priority of Serial port 0 is higher priority level.

PX1

1: To set interrupt priority of External interrupt 1 is higher priority level.

PT0

1: To set interrupt priority of Timer 0 is higher priority level.

PX0

1: To set interrupt priority of External interrupt 0 is higher priority level.

Slave Address Mask Enable

Bit: 7 6 5 4 3 2 1 0

Mnemonic:

SADEN Address:

B9h

W78ERD2

Publication Release Date: April 20, 2005

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Revision A4

BIT NAME

FUNCTION

7~0 SADEN

This register enables the Automatic Address Recognition feature of the Serial
port 0. When a bit in the SADEN is set to 1, the same bit location in SADDR will
be compared with the incoming serial data. When SADEN.n is 0, then the bit
becomes a "don't care" in the comparison. This register enables the Automatic
Address Recognition feature of the Serial port 0. When all the bits of SADEN
are 0, interrupt will occur for any incoming address.

On-Chip Programming Control

Bit: 7 6 5 4 3 2 1 0

SWRST/R

EBOOT

- - - - 0

FBOOTSL

FPROGEN

Mnemonic:

CHPCON Address:

BFh

BIT NAME

FUNCTION

7 SWRESET/

REBOOT

(F04KMODE)

When this bit is set to 1, and both FBOOTSL and FPROGEN are set to 1. It
will enforce microcontroller reset to initial condition just like power on reset.
This action will re-boot the microcontroller and start to normal operation. To
read this bit in logic-1 can determine that the H/W REBOOT mode is running.

6 -

Reserve.

5 -

Reserve.

Reserve

3 -

Reserve

2 -

Reserve

FBOOTSL The Program Location Select.

0: The Loader Program locates at the 64 KB AP Flash EPROM. 4KB LD

Flash EPROM is destination for re-programming.

1: The Loader Program locates at the 4 KB memory bank. 64KB AP Flash

EPROM is destination for re-programming.

FPROGEN FLASH EPROM Programming Enable.

= 1: enable. The microcontroller enter the in-system programming mode after

entering the idle mode and wake-up from interrupt. During in-system
programming mode, the operation of erase, program and read are
achieve when device enters idle mode.

= 0: disable. The on-chip flash memory is read-only. In-system

programmability is disabled.

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External Interrupt Control

Bit: 7 6 5 4 3 2 1 0

PX3 EX3 IE3 IT3 PX2 EX2 IE2 IT2

Mnemonic: XICON Address: C0h

BIT NAME

FUNCTION

PX3

External interrupt 3 priority high if set

EX3

External interrupt 3 enable if set

IE3

1: IE3 is set/cleared automatically by hardware when interrupt is detected /

serviced

IT3

1: External interrupt 3 is falling-edge/low-level triggered when this bit is set /

cleared by software

PX2

External interrupt 2 priority high if set

EX2

External interrupt 2 enable if set

IE2

1: IE2 is set/cleared automatically by hardware when interrupt is detected /

serviced

IT2

1: External interrupt 2 is falling-edge/low-level triggered when this bit is set /

cleared by software

External Interrupt High Control

Bit: 7 6 5 4 3 2 1 0

PXH3

- - -

PXH2

- - -

Mnemonic: XICON Address: C0h

BIT NAME

FUNCTION

PXH3

External interrupt 3 priority highest if set

6 -

Reserve

5 -

Reserve

4 -

Reserve

PXH2

External interrupt 2 priority highest if set

2 -

Reserve

1 -

Reserve

0 -

Reserve

W78ERD2

Publication Release Date: April 20, 2005

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Revision A4

Port 4 Control Register A

Bit: 7 6 5 4 3 2 1 0

P41FUN1

P41FUN0

P41CMP1 P41CMP0 P40FUN1 P40FUN0 P40CMP1

P40CMP0

Mnemonic:

P4CONA Address:

C2h

BIT NAME

FUNCTION

7, 6

P41FUN1
P41FUN0

The P4.1 function control bits which are the similar definition as P43FUN1,
P43FUN0.

5, 4

P41CMP1
P41CMP0

The P4.1 address comparator length control bits which are the similar
definition as P43CMP1, P43CMP0.

3, 2

P40FUN1
P40FUN0

The P4.0 function control bits which are the similar definition as P43FUN1,
P43FUN0.

1, 0

P40CMP1
P40CMP0

The P4.0 address comparator length control bits which are the similar
definition as P43CMP1, P43CMP0.

Port 4 Control Register B

Bit: 7 6 5 4 3 2 1 0

P43FUN1

P43FUN0

P43CMP1 P43CMP0 P42FUN1 P42FUN0 P42CMP1

P42CMP0

Mnemonic:

P4CONB Address:

C3h

BIT NAME

FUNCTION

7, 6

P43FUN1
P43FUN0

00: Mode 0. P4.3 is a general purpose I/O port which is the same as Port1.
01: Mode 1. P4.3 is a Read Strobe signal for chip select purpose. The

address range depends on the SFR P43AH, P43AL, P43CMP1 and
P43CMP0.

10: Mode 2. P4.3 is a Write Strobe signal for chip select purpose. The

address range depends on the SFR P43AH, P43AL, P43CMP1 and
P43CMP0.

11: Mode 3. P4.3 is a Read/Write Strobe signal for chip select purpose. The

address range depends on the SFR P43AH, P43AL, P43CMP1, and
P43CMP0.

W78ERD2

- 24 -

BIT NAME

FUNCTION

5, 4

P43CMP1
P43CMP0

Chip-select signals address comparison:
00: Compare the full address (16 bits length) with the base address register

P43AH, P43AL.

01: Compare the 15 high bits (A15

A1) of address bus with the base

address register P43AH, P43AL.

10: Compare the 14 high bits (A15

A2) of address bus with the base

address register P43AH, P43AL.

11: Compare the 8 high bits (A15

A8) of address bus with the base

address register P43AH, P43AL.

3, 2

P42FUN1
P42FUN0

The P4.2 function control bits which are the similar definition as P43FUN1,
P43FUN0.

1, 0

P42CMP1
P42CMP0

The P4.2 address comparator length control bits which are the similar
definition as P43CMP1, P43CMP0.

F/W Flash Low Address

Bit: 7 6 5 4 3 2 1 0

Mnemonic: SFRAL Address: C4h

F/W flash low byte address

F/W Flash High Address

Bit: 7 6 5 4 3 2 1 0

Mnemonic: SFRAH Address: C5h

F/W flash high byte address

F/W Flash Data

Bit: 7 6 5 4 3 2 1 0

Mnemonic: SFRFD Address: C6h

F/W flash data

W78ERD2

Publication Release Date: April 20, 2005

- 25 -

Revision A4

F/W Flash Control

Bit: 7 6 5 4 3 2 1 0

WFWIN

NOE

NCE

CTRL3 CTRL2 CTRL1

CTRL0

Mnemonic: SFRCN Address: C7h

BIT NAME

FUNCTION

7 -

Reserve

WFWIN

On-chip Flash EPROM bank select for in-system programming.
0: 64K bytes Flash EPROM bank is selected as destination for re-

programming.

1: 4K bytes Flash EPROM bank is selected as destination for re-

programming.

OEN

Flash EPROM output enable.

CEN

Flash EPROM chip enable.

3~0

CTRL[3:0] The flash control signals

Timer 2 Control

Bit: 7 6 5 4 3 2 1 0

TF2

EXF2

RCLK

TCLK

EXEN2

TR2

C/T2

CP/RL2

Mnemonic: T2CON Address: C8h

BIT NAME

FUNCTION

TF2

Timer 2 overflow flag: This bit is set when Timer 2 overflows. It is also set when
the count is equal to the capture register in down count mode. It can be set only
if RCLK and TCLK are both 0. It is cleared only by software. Software can also
set or clear this bit.

EXF2

Timer 2 External Flag: A negative transition on the T2EX pin (P1.1) or timer 2
underflow/overflow will cause this flag to set based on the CP/RL2, EXEN2 and
DCEN bits. If set by a negative transition, this flag must be cleared by software.
Setting this bit in software or detection of a negative transition on T2EX pin will
force a timer interrupt if enabled.

RCLK

Receive clock Flag: This bit determines the serial port time-base when receiving
data in serial modes 1 or 3. If it is 0, then timer 1 overflow is used for baud rate
generation, else timer 2 overflow is used. Setting this bit forces timer 2 in baud
rate generator mode.

TCLK

Transmit clock Flag: This bit determines the serial port time-base when
transmitting data in mode 1 and 3. If it is set to 0, the timer 1 overflow is used to
generate the baud rate clock, else timer 2 overflow is used. Setting this bit
forces timer 2 in baud rate generator mode.

W78ERD2

- 26 -

Continued

BIT NAME

FUNCTION

EXEN2 Timer 2 External Enable: This bit enables the capture/reload function on the

T2EX pin if Timer 2 is not generating baud clocks for the serial port. If this bit is
0, then the T2EX pin will be ignored, else a negative transition detected on the
T2EX pin will result in capture or reload.

TR2

Timer 2 Run Control: This bit enables/disables the operation of timer 2.halting
this will preserve the current count in TH2, TL2.

C/T2

Counter/Timer select: This bit determines whether timer 2 will function as a timer
or a counter. Independent of this bit, the timer will run at 2 clocks per tick when
used in baud rate generator mode. If it is set to 0, then timer 2 operates as a
timer at a speed depending on T2M bit (CKCON.5), else, it will count negative
edges on T2 pin.

CP/RL2 Capture/Reload Select: This bit determines whether the capture or reload

function will be used for timer 2. If either RCLK or TCLK is set, this bit will not
function and the timer will function in an auto-reload mode following each
overflow. If the bit is 0 then auto-reload will occur when timer 2 overflows or a
falling edge is detected on T2EX if EXEN2 = 1. If this bit is 1, then timer 2
captures will occur when a falling edge is detected on T2EX if EXEN2 = 1.

Timer 2 Mode

Bit: 7 6 5 4 3 2 1 0

- - - - - -

T2OE

DCEN

Mnemonic: T2MOD Address: C9h

BIT NAME

FUNCTION

7~2 - Reserve

T2OE

Timer 2 Output Enable. This bit enables/disables the Timer 2 clock out function.

DCEN

Down Count Enable: This bit, in conjunction with the T2EX pin, controls the
direction that timer 2 counts in 16-bit auto-reload mode.

Timer 2 Capture Low

Bit: 7 6 5 4 3 2 1 0

RCAP2L.7

RCAP2L.6

RCAP2L.5 RCAP2L.4 RCAP2L.3 RCAP2L.2 RCAP2L.1 RCAP2L.0

Mnemonic:

RCAP2L Address:

CAh

RCAP2L Timer 2 Capture LSB: This register is used to capture the TL2 value when a timer 2 is
configured in capture mode. RCAP2L is also used as the LSB of a 16-bit reload value when timer 2 is
configured in auto-reload mode.

W78ERD2

Publication Release Date: April 20, 2005

- 27 -

Revision A4

Timer 2 Capture High

Bit: 7 6 5 4 3 2 1 0

RCAP2H.7 RCAP2H.6 RCAP2H.5 RCAP2H.4 RCAP2H.3 RCAP2H.2 RCAP2H.1 RCAP2H.0

Mnemonic:

RCAP2H Address:

CBh

RCAP2H Timer 2 Capture HSB: This register is used to capture the TH2 value when a timer 2 is
configured in capture mode. RCAP2H is also used as the HSB of a 16-bit reload value when timer 2 is
configured in auto-reload mode.

Timer 2 Register Low

Bit: 7 6 5 4 3 2 1 0

TL2.7 TL2.6 TLH2.5

TL2.4 TL2.3 TL2.2 TL2.1 TL2.0

Mnemonic:

TL2

Address:

CCh

TL2 Timer 2 LSB

Timer 2 Register High

Bit: 7 6 5 4 3 2 1 0

TH2.7

TH2.6

TH2.5

TH2.4

TH2.3

TH2.2

TH2.1

TH2.0

Mnemonic:

TH2

Address:

CDh

TL2 Timer 2 MSB

Program Status Word

Bit: 7 6 5 4 3 2 1 0

RS1

RS0

F1 P

Mnemonic:

PSW Address:

D0h

BIT NAME

FUNCTION

7 CY

Carry flag: Set for an arithmetic operation which results in a carry being generated
from the ALU. It is also used as the accumulator for the bit operations.

6 AC

Auxiliary carry: Set when the previous operation resulted in a carry from the high
order nibble.

User flag 0: The General purpose flag that can be set or cleared by the user.

RS1

RS0

2 OV

Overflow flag: Set when a carry was generated from the seventh bit but not from
the 8th bit as a result of the previous operation, or vice-versa.

1 F1

User Flag 1: The General purpose flag that can be set or cleared by the user by
software.

0 P

Parity flag: Set/cleared by hardware to indicate odd/even number of 1's in the
accumulator.

W78ERD2

Publication Release Date: April 20, 2005

- 29 -

Revision A4

PCA Module 3 Register

Bit: 7 6 5 4 3 2 1 0

ECOM3

CAPP3 CAPN3

MAT3

TOG3

PWM3

ECCF3

Mnemonic:

CCAPM3 Address:

DDh

PCA Module 4 Register

Bit: 7 6 5 4 3 2 1 0

ECOM4

CAPP4 CAPN4

MAT4

TOG4

PWM4

ECCF4

Mnemonic:

CCAPM4 Address:

DEh

Clock Control Register

Bit: 7 6 5 4 3 2 1 0

- -

T2M

T1M

T0M

- -

Mnemonic: CKCON Address: DFh

BIT NAME

FUNCTION

7 - Reserve
6 - Reserve

5 T2M

Timer 2 clock select: When T2M is set to 1, timer 2 uses a divide by 6 clock, and
when set to 0 uses a divide by 12 clock. (This bit has no effect if bit 3 of Option-bits
is set to 1 to select 12 clocks/machine cycle)

4 T1M

Timer 1 clock select: When T1M is set to 1, timer 1 uses a divide by 6 clock, and
when set to 0 uses a divide by 12 clock. (This bit has no effect if bit 3 of Option-
bits is set to 1 to select 12 clocks/machine cycle)

3 T0M

Timer 0 clock select: When T0M is set to 1, timer 0 uses a divide by 6 clock, and
when set to 0 uses a divide by 12 clock. (This bit has no effect if bit 3 of Option-
bits is set to 1 to select 12 clocks/machine cycle)

2 - Reserve
1 - Reserve

0 MD

Stretch MOVX select bits: This bit is used to select the stretch value for the MOVX
instruction. Using a variable MOVX length. Enables the user to access slower
memory devices or peripherals without the need for external circuits. The RD or
WR strobe will be stretched by the selected interval. All internal timing s are also
stretched by the same amount. This operation is transparent to the user. By
default, the stretch has value 1 cycle. If the user needs faster accessing, then
stretch value of 0 should be selected

Accumulator

Bit: 7 6 5 4 3 2 1 0

ACC.7

ACC.6

ACC.5

ACC.4

ACC.3

ACC.2

ACC.1

ACC.0

W78ERD2

- 30 -

Mnemonic:

ACC Address:

E0h

ACC.7-0: The A (or ACC) register is the standard 8052 accumulator.

Port 4

Bit: 7 6 5 4 3 2 1 0

- - - -

P4.3/INT2 P4.2/INT3

P4.1

P4.0

Mnemonic:

ACC Address:

E8h

P4.3-0: Port 4 is a bi-directional I/O port with internal pull-ups.

BIT NAME

FUNCTION

7 -

Reserve

6 -

Reserve

5 -

Reserve

4 -

Reserve

P4.3

Port 4 Data bit which outputs to pin P4.3 at mode 0, or external Interrupt 2.

P4.2

Port 4 Data bit which outputs to pin P4.2 at mode 0, or external Interrupt 3.

P4.1

Port 4 Data bit which outputs to pin P4.1 at mode 0.

P4.0

Port 4 Data bit which outputs to pin P4.0 at mode 0.

PCA Counter Low Register

Bit: 7 6 5 4 3 2 1 0

CL.7 CL.6 CL.6 CL.4 CL.3 CL.2 CL.1 CL.0

Mnemonic:

CL Address:

E9h

PCA Module 0 Compare/Capture Low Register

Bit: 7 6 5 4 3 2 1 0

CCAP0L.7 CCAP0L.6 CCAP0L.5 CCAP0L.4 CCAP0L.3 CCAP0L.2 CCAP0L.1 CCAP0L.0

Mnemonic: CCAP0L Address: EAh

PCA Module 1 Compare/Capture Low Register

Bit: 7 6 5 4 3 2 1 0

CCAP1L.7

CCAP1L.6

CCAP1L.5 CCAP1L.4 CCAP1L.3 CCAP1L.2 CCAP1L.1 CCAP1L.0

Mnemonic: CCAP1L Address: EBh

W78ERD2

Publication Release Date: April 20, 2005

- 31 -

Revision A4

PCA Module 2 Compare/Capture Low Register

Bit: 7 6 5 4 3 2 1 0

CCAP2L.7

CCAP2L.6

CCAP2L.5 CCAP2L.4 CCAP2L.3 CCAP2L.2 CCAP2L.1 CCAP2L.0

Mnemonic: CCAP2L Address: ECh

PCA Module 3 Compare/Capture Low Register

Bit: 7 6 5 4 3 2 1 0

CCAP3L.7

CCAP3L.6

CCAP3L.5 CCAP3L.4 CCAP3L.3 CCAP3L.2 CCAP3L.1 CCAP3L.0

Mnemonic: CCAP3L Address: EDh

PCA Module 4 Compare/Capture Low Register

Bit: 7 6 5 4 3 2 1 0

CCAP4L.7

CCAP4L.6

CCAP4L.5 CCAP4L.4 CCAP4L.3 CCAP4L.2 CCAP4L.1 CCAP4L.0

Mnemonic: CCAP4L Address: EEh

B Register

Bit: 7 6 5 4 3 2 1 0

B.7 B.6 B.5 B.4 B.3 B.2 B.1 B.0

Mnemonic:

B Address:

F0h

B.7-0: The B register is the standard 8052 register that serves as a second accumulator.

Chip Enable Register

Bit: 7 6 5 4 3 2 1 0

Mnemonic: CHPENR Address: F6h

W78ERD2

- 32 -

PCA Counter High Register

Bit: 7 6 5 4 3 2 1 0

CH.7 CH.6 CH.6 CH.4 CH.3 CH.2 CH.1 CH.0

Mnemonic:

CH Address:

F9h

PCA Module 0 Compare/Capture High Register

Bit: 7 6 5 4 3 2 1 0

CCAP0H.7CCAP0H.6

CCAP0H.5CCAP0H.4CCAP0H.3CCAP0H.2CCAP0H.1 CCAP0H.0

Mnemonic: CCAP0H Address: FAh

PCA Module 1 Compare/Capture High Register

Bit: 7 6 5 4 3 2 1 0

CCAP1H.7CCAP1H.6

CCAP1H.5CCAP1H.4CCAP1H.3CCAP1H.2CCAP1H.1 CCAP1H.0

Mnemonic: CCAP1H Address: FBh

PCA Module 2 Compare/Capture High Register

Bit: 7 6 5 4 3 2 1 0

CCAP2H.7CCAP2H.6

CCAP2H.5CCAP2H.4CCAP2H.3CCAP2H.2CCAP2H.1 CCAP2H.0

Mnemonic: CCAP2H Address: FCh

PCA Module 3 Compare/Capture High Register

Bit: 7 6 5 4 3 2 1 0

CCAP3H.7CCAP3H.6

CCAP3H.5CCAP3H.4CCAP3H.3CCAP3H.2CCAP3H.1 CCAP3H.0

Mnemonic: CCAP3H Address: FDh

PCA Module 4 Compare/Capture High Register

Bit: 7 6 5 4 3 2 1 0

CCAP4H.7 CCAP4H.6 CCAP4H.5 CCAP4H.4 CCAP4H.3 CCAP4H.2 CCAP4H.1 CCAP4H.0

Mnemonic: CCAP4H Address: FEh

W78ERD2

Publication Release Date: April 20, 2005

- 33 -

Revision A4

8. PORT 4 AND BASE ADDRESS REGISTERS

Port 4, address E8H, is a 4-bit multipurpose programmable I/O port. Each bit can be configured
individually by software. The Port 4 has four different operation modes.

Mode 0: P4.0

P4.3 is a bi-directional I/O port which is same as port 1. P4.2 and P4.3 also serve as

external interrupt INT3 and INT2 if enabled.

Mode 1: P4.0

P4.3 are read strobe signals that are synchronized with RD signal at specified

addresses. These signals can be used as chip-select signals for external peripherals.

Mode 2: P4.0

P4.3 are write strobe signals that are synchronized with

WR signal at specified

addresses. These signals can be used as chip-select signals for external peripherals.

Mode 3: P4.0

P4.3 are read/write strobe signals that are synchronized with RD or WR signal at

specified addresses. These signals can be used as chip-select signals for external
peripherals.

When Port 4 is configured with the feature of chip-select signals, the chip-select signal address range
depends on the contents of the SFR P4xAH, P4xAL, P4CONA and P4CONB. The registers P4xAH
and P4xAL contain the 16-bit base address of P4.x. The registers P4CONA and P4CONB contain the
control bits to configure the Port 4 operation mode.

P40AH, P40AL:

The Base address register for comparator of P4.0. P40AH contains the high-order byte of address,
P40AL contains the low-order byte of address.

P41AH, P41AL:

The Base address register for comparator of P4.1. P41AH contains the high-order byte of address,
P41AL contains the low-order byte of address.

P42AH, P42AL:

The Base address register for comparator of P4.2. P42AH contains the high-order byte of address,
P42AL contains the low-order byte of address.

P43AH, P43AL:

The Base address register for comparator of P4.3. P43AH contains the high-order byte of address,
P43AL contains the low-order byte of address.

W78ERD2

- 34 -

P4 (E8H)

BIT NAME

FUNCTION

7 -

Reserve

6 -

Reserve

5 -

Reserve

4 -

Reserve

P43

Port 4 Data bit which outputs to pin P4.3 at mode 0.

P42

Port 4 Data bit which outputs to pin P4.2 at mode 0.

P41

Port 4 Data bit which outputs to pin P4.1at mode 0.

P40

Port 4 Data bit which outputs to pin P4.0 at mode 0.

Here is an example to program the P4.0 as a write strobe signal at the I/O port address 1234H

1237H and positive polarity, and P4.1

P4.3 are used as general I/O ports.

MOV P40AH, #12H
MOV P40AL, #34H

; Base I/O address 1234H for P4.0

MOV P4CONA, #00001010B

; P4.0 a write strobe signal and address line A0 and A1 are masked.

MOV P4CONB, #00H

; P4.1

P4.3 as general I/O port which are the same as PORT1

MOV P2ECON, #10H

; Write the P40SINV = 1 to inverse the P4.0 write strobe polarity

; default is negative.

Then any instruction MOVX @DPTR, A (with DPTR = 1234H

1237H) will generate the positive

polarity write strobe signal at pin P4.0. And the instruction MOV P4, #XX will output the bit3 to bit1 of
data #XX to pin P4.3

P4.1.

ADDRESS BUS

Bit Length

Selectable

comparator

P4xAL

P4xAH

EQUAL

P4.x

MUX 4->1

P4 REGISTER

P4.x

READ
WRITE

DATA I/O

RD_CS

WR_CS

RD/WR_CS

P4xCMP0

P4xCMP1

P4xFUN0

P4xFUN1

P4xCSINV

P4.x INPUT DATA BUS

W78ERD2

Publication Release Date: April 20, 2005

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Revision A4

9. INTERRUPT

INT2 / INT3

Two additional external interrupts, INT2 and INT3 , whose functions are similar to those of external
interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are
determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register is
bit-addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To
set/clear bits in the XICON register, one can use the "SETB ( CLR ) bit" instruction. For example,
"SETB 0C2H" sets the EX2 bit of XICON.

Nine-source interrupt information

INTERRUPT SOURCE

VECTOR

ADDRESS

POLLING SEQUENCE

WITHIN PRIORITY

LEVEL

ENABLE

REQUIRED

SETTINGS

INTERRUPT TYPE

EDGE/LEVEL

External Interrupt 0

03H

0 (highest)

IE.0

TCON.0

Timer/Counter 0

0BH

IE.1

External Interrupt 1

13H

IE.2

TCON.2

Timer/Counter 1

1BH

IE.3

Programmable
Counter Array

33H 4 IE.6 -

Serial Port

23H

IE.4

Timer/Counter 2

2BH

IE.5

External Interrupt 2

33H

XICON.2

XICON.0

External Interrupt 3

3BH

8 (lowest)

XICON.6

XICON.3

Four-level interrupt priority

PRIORITY BITS

IPH.X IP.X

INTERRUPT PRIORITY LEVEL

Level 0(lowest priority)

0 1

Level

1 0

Level

Level 3(highest priority)

W78ERD2

- 36 -

10. ENHANCED FULL DUPLEX SERIAL PORT

Serial port in the W78ERD2 is a full duplex port. The W78ERD2 provides the user with additional
features such as the Frame Error Detection and the Automatic Address Recognition. The serial ports
are capable of synchronous as well as asynchronous communication. In Synchronous mode the
W78ERD2 generates the clock and operates in a half duplex mode. In the asynchronous mode, full
duplex operation is available. This means that it can simultaneously transmit and receive data. The
transmit register and the receive buffer are both addressed as SBUF Special Function Register.
However any write to SBUF will be to the transmit register, while a read from SBUF will be from the
receive buffer register. The serial port can operate in four different modes as described below.

10.1 MODE 0

This mode provides synchronous communication with external devices. In this mode serial data is
transmitted and received on the RXD line. TXD is used to transmit the shift clock. The TxD clock is
provided by the W78ERD2 whether the device is transmitting or receiving. This mode is therefore a
half duplex mode of serial communication. In this mode, 8 bits are transmitted or received per frame.
The LSB is transmitted/received first. The baud rate is fixed at 1/12 of the oscillator frequency.
The functional block diagram is shown below. Data enters and leaves the Serial port on the RxD line.
The TxD line is used to output the shift clock. The shift clock is used to shift data into and out of the
W78ERD2 and the device at the other end of the line. Any instruction that causes a write to SBUF will
start the transmission. The shift clock will be activated and data will be shifted out on the RxD pin till all
8 bits are transmitted. If SM2 = 1, then the data on RxD will appear 1 clock period before the falling
edge of shift clock on TxD. The clock on TxD then remains low for 2 clock periods, and then goes high
again. If SM2 = 0, the data on RxD will appear 3 clock periods before the falling edge of shift clock on
TxD. The clock on TxD then remains low for 6 clock periods, and then goes high again. This ensures
that at the receiving end the data on RxD line can either be clocked on the rising edge of the shift
clock on TxD or latched when the TxD clock is low.

SBUF

Transmit Shift Register

Receive Shift Register

SHIFT

PAROUT

Internal

Data Bus

Internal

Data Bus

RXD
P3.0 Alternate
Output Function

TXD
P3.1 Alternate
Output function

RXD

P3.0 Alternate

Iutput function

Serial Port Interrupt

Write to

SBUF

START

SOUT

REN

PARIN

LOAD

CLOCK

Read SBUF

SBUF

TX CLOCK

SERIAL

CONTROLLE

SHIFT

CLOCK

RX
CLOCK

LOAD SBUF

RX
START

RX SHIFT

CLOCK

SIN

osc

Serial Port Mode 0

W78ERD2

Publication Release Date: April 20, 2005

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Revision A4

The TI flag is set high in C1 following the end of transmission of the last bit. The serial port will receive
data when REN is 1 and RI is zero. The shift clock (TxD) will be activated and the serial port will latch
data on the rising edge of shift clock. The external device should therefore present data on the falling
edge on the shift clock. This process continues till all the 8 bits have been received. The RI flag is set
in C1 following the last rising edge of the shift clock on TxD. This will stop reception, till the RI is
cleared by software.

10.2 MODE 1

In Mode 1, the full duplex asynchronous mode is used. Serial communication frames are made up of
10 bits transmitted on TXD and received on RXD. The 10 bits consist of a start bit (0), 8 data bits (LSB
first), and a stop bit (1). On receive, the stop bit goes into RB8 in the SFR SCON. The baud rate in this
mode is variable. The serial baud can be programmed to be 1/16 or 1/32 of the Timer 1 overflow.
Since the Timer 1 can be set to different reload values, a wide variation in baud rates is possible.
Transmission begins with a write to SBUF. The serial data is brought out on to TxD pin at C1 following
the first roll-over of divide by 16 counter. The next bit is placed on TxD pin at C1 following the next
rollover of the divide by 16 counter. Thus the transmission is synchronized to the divide by 16 counter
and not directly to the write to SBUF signal. After all 8 bits of data are transmitted, the stop bit is
transmitted. The TI flag is set in the C1 state after the stop bit has been put out on TxD pin. This will
be at the 10th rollover of the divide by 16 counter after a write to SBUF.
Reception is enabled only if REN is high. The serial port actually starts the receiving of serial data,
with the detection of a falling edge on the RxD pin. The 1-to-0 detector continuously monitors the RxD
line, sampling it at the rate of 16 times the selected baud rate. When a falling edge is detected, the
divide by 16 counter is immediately reset. This helps to align the bit boundaries with the rollovers of
the divide by 16 counter.
The 16 states of the counter effectively divide the bit time into 16 slices. The bit detection is done on a
best of three basis. The bit detector samples the RxD pin, at the 8th, 9th and 10th counter states. By
using a majority 2 of 3 voting system, the bit value is selected. This is done to improve the noise
rejection feature of the serial port. If the first bit detected after the falling edge of RxD pin is not 0, then
this indicates an invalid start bit, and the reception is immediately aborted. The serial port again looks
for a falling edge in the RxD line. If a valid start bit is detected, then the rest of the bits are also
detected and shifted into the SBUF.
After shifting in 8 data bits, there is one more shift to do, after which the SBUF and RB8 are loaded
and RI is set. However certain conditions must be met before the loading and setting of RI can be
done.
1. RI must be 0 and
2. Either SM2 = 0, or the received stop bit = 1.

If these conditions are met, then the stop bit goes to RB8, the 8 data bits go into SBUF and RI is set.
Otherwise the received frame may be lost. After the middle of the stop bit, the receiver goes back to
looking for a 1-to-0 transition on the RxD pin.

W78ERD2

- 38 -

SBUF

RB8

Transmit Shift Register

Receive Shift

TX SHIFT

PAROUT

Internal

Data Bus

Internal

Data

Bus

TXD

RXD

Serial Port

Interrupt

SMOD =

TCLK

RCLK

SAMPLE

Write to

SBUF

TX START

SOUT

PARIN

STOP

START
LOAD

CLOCK

Read

SBUF

Timer 2

Overflow

Timer 1

Overflow

TX CLOCK

SERIAL

CONTROLLER

RX CLOCK

LOAD

SBUF

START

RX SHIFT

1-TO-0

DETECTOR

BIT

DETECTOR

CLOCK

SIN

Serial Port Mode 1

10.3 MODE 2

This mode uses a total of 11 bits in asynchronous full-duplex communication. The functional
description is shown in the figure below. The frame consists of one start bit (0), 8 data bits (LSB first),
a programmable 9th bit (TB8) and a stop bit (0). The 9th bit received is put into RB8. The baud rate is
programmable to 1/32 or 1/64 of the oscillator frequency, which is determined by the SMOD bit in
PCON SFR. Transmission begins with a write to SBUF. The serial data is brought out on to TxD pin at
C1 following the first roll-over of the divide by 16 counter. The next bit is placed on TxD pin at C1
following the next rollover of the divide by 16 counter. Thus the transmission is synchronized to the
divide by 16 counter, and not directly to the write to SBUF signal. After all 9 bits of data are
transmitted, the stop bit is transmitted. The TI flag is set in the C1 state after the stop bit has been put
out on TxD pin. This will be at the 11th rollover of the divide by 16 counter after a write to SBUF.
Reception is enabled only if REN is high. The serial port actually starts the receiving of serial data,
with the detection of a falling edge on the RxD pin. The 1-to-0 detector continuously monitors the RxD
line, sampling it at the rate of 16 times the selected baud rate. When a falling edge is detected, the
divide by 16 counter is immediately reset. This helps to align the bit boundaries with the rollovers of
the divide by 16 counter. The 16 states of the counter effectively divide the bit time into 16 slices. The
bit detection is done on a best of three basis. The bit detector samples the RxD pin, at the 8th, 9th and
10th counter states. By using a majority 2 of 3 voting system, the bit value is selected. This is done to
improve the noise rejection feature of the serial port.

W78ERD2

Publication Release Date: April 20, 2005

- 39 -

Revision A4

SBUF

RB8

Transmit Shift Register

Receive Shift Register

SHIFT

PAROUT

Internal

Data Bus

Internal

Data

Bus

TXD

RXD

Serial Port

Interrupt

SMOD =

SAMPLE

Write to

SBUF

START

SOUT

PARIN

STOP

START
LOAD

CLOCK

Read
SBUF

CLOCK

SERIAL

CONTROLLER

RX CLOCK

LOAD

SBUF

RX START

RX SHIFT

1-TO-0

DETECTOR

BIT

DETECTOR

CLOCK

SIN

TB8

osc

Serial Port Mode 2

If the first bit detected after the falling edge of RxD pin, is not 0, then this indicates an invalid start bit,
and the reception is immediately aborted. The serial port again looks for a falling edge in the RxD line.
If a valid start bit is detected, then the rest of the bits are also detected and shifted into the SBUF.
After shifting in 9 data bits, there is one more shift to do, after which the SBUF and RB8 are loaded
and RI is set. However certain conditions must be met before the loading and setting of RI can be
done.
1. RI must be 0 and
2. Either SM2 = 0, or the received stop bit = 1.
If these conditions are met, then the stop bit goes to RB8, the 8 data bits go into SBUF and RI is set.
Otherwise the received frame may be lost. After the middle of the stop bit, the receiver goes back to
looking for a 1-to-0 transition on the RxD pin.

10.4 MODE 3

This mode is similar to Mode 2 in all respects, except that the baud rate is programmable. The user
must first initialize the Serial related SFR SCON before any communication can take place. This
involves selection of the Mode and baud rate. The Timer 1 should also be initialized if modes 1 and 3
are used. In all four modes, transmission is started by any instruction that uses SBUF as a destination
register. Reception is initiated in Mode 0 by the condition RI = 0 and REN = 1. This will generate a
clock on the TxD pin and shift in 8 bits on the RxD pin. Reception is initiated in the other modes by the
incoming start bit if REN = 1. The external device will start the communication by transmitting the start
bit.

W78ERD2

- 40 -

SBUF

RB8

Transmit Shift Register

Receive Shift

TX SHIFT

PAROUT

Internal

Data Bus

Internal

Data

Bus

TXD

RXD

Serial Port

Interrupt

SMOD =

TCLK

RCLK

SAMPLE

Write to

SBUF

TX START

SOUT

PARIN

STOP

START
LOAD

CLOCK

Read

SBUF

Timer 2

Overflow

Timer 1

Overflow

TX CLOCK

SERIAL

CONTROLLER

RX CLOCK

LOAD

SBUF

START

RX SHIFT

1-TO-0

DETECTOR

BIT

DETECTOR

CLOCK

SIN

TB8

Serial Port Mode 3

Serial Ports Modes

SM1 SM0 Mode

Type

Baud

Clock

Frame

Size

Start

Bit

Stop

Bit

9th bit

Function

Synch.

12 TCLKS

8 bits

None

Asynch.

Timer 1 or 2

10 bits

None

Asynch.

32 or 64 TCLKS

11 bits

0, 1

Asynch.

Timer 1 or 2

11 bits

0, 1

W78ERD2

Publication Release Date: April 20, 2005

- 41 -

Revision A4

10.5 Framing Error Detection

A Frame Error occurs when a valid stop bit is not detected. This could indicate incorrect serial data
communication. Typically the frame error is due to noise and contention on the serial communication
line. The W78ERD2 has the facility to detect such framing errors and set a flag which can be checked
by software.

The Frame Error FE bit is located in SCON.7. This bit is normally used as SM0 in the standard 8051
family. However, in the W78ERD2 it serves a dual function and is called SM0/FE. There are actually
two separate flags, one for SM0 and the other for FE. The flag that is actually accessed as SCON.7 is
determined by SMOD0 (PCON.6) bit. When SMOD0 is set to 1, then the FE flag is indicated in
SM0/FE. When SMOD0 is set to 0, then the SM0 flag is indicated in SM0/FE.

The FE bit is set to 1 by hardware but must be cleared by software. Note that SMOD0 must be 1 while
reading or writing to FE. If FE is set, then any following frames received without any error will not clear
the FE flag. The clearing has to be done by software.

10.6 Multiprocessor Communications

Multiprocessor communications makes use of the 9th data bit in modes 2 and 3. In the W78ERD2, the
RI flag is set only if the received byte corresponds to the Given or Broadcast address. This hardware
feature eliminates the software overhead required in checking every received address, and greatly
simplifies the software programmer task.

In the multiprocessor communication mode, the address bytes are distinguished from the data bytes
by transmitting the address with the 9th bit set high. When the master processor wants to transmit a
block of data to one of the slaves, it first sends out the address of the targeted slave (or slaves). All the
slave processors should have their SM2 bit set high when waiting for an address byte. This ensures
that they will be interrupted only by the reception of a address byte. The Automatic address
recognition feature ensures that only the addressed slave will be interrupted. The address comparison
is done in hardware not software.

The addressed slave clears the SM2 bit, thereby clearing the way to receive data bytes. With SM2 = 0,
the slave will be interrupted on the reception of every single complete frame of data. The unaddressed
slaves will be unaffected, as they will be still waiting for their address. In Mode 1, the 9th bit is the stop
bit, which is 1 in case of a valid frame. If SM2 is 1, then RI is set only if a valid frame is received and
the received byte matches the Given or Broadcast address.

The Master processor can selectively communicate with groups of slaves by using the Given Address.
All the slaves can be addressed together using the Broadcast Address. The addresses for each slave
are defined by the SADDR and SADEN SFRs. The slave address is an 8-bit value specified in the
SADDR SFR. The SADEN SFR is actually a mask for the byte value in SADDR. If a bit position in
SADEN is 0, then the corresponding bit position in SADDR is don't care. Only those bit positions in
SADDR whose corresponding bits in SADEN are 1 are used to obtain the Given Address. This gives
the user flexibility to address multiple slaves without changing the slave address in SADDR.

W78ERD2

- 42 -

The following example shows how the user can define the Given Address to address different slaves.
Slave 1:
SADDR 1010

0100

SADEN 1111

1010

Given 1010

0x0x

Slave 2:
SADDR 1010

0111

SADEN 1111

1001

Given 1010

0xx1

The Given address for slave 1 and 2 differ in the LSB. For slave 1, it is a don't care, while for slave 2 it
is 1. Thus to communicate only with slave 1, the master must send an address with LSB = 0 (1010
0000). Similarly the bit 1 position is 0 for slave 1 and don't care for slave 2. Hence to communicate
only with slave 2 the master has to transmit an address with bit 1 = 1 (1010 0011). If the master
wishes to communicate with both slaves simultaneously, then the address must have bit 0 = 1 and bit
1 = 0. The bit 3 position is don't care for both the slaves. This allows two different addresses to select
both slaves (1010 0001 and 1010 0101).

The master can communicate with all the slaves simultaneously with the Broadcast Address. This
address is formed from the logical ORing of the SADDR and SADEN SFRs. The zeros in the result are
defined as don't cares In most cases the Broadcast Address is FFh. In the previous case, the
Broadcast Address is (1111111X) for slave 1 and (11111111) for slave 2.

The SADDR and SADEN SFRs are located at address A9h and B9h respectively. On reset, these two
SFRs are initialized to 00h. This results in Given Address and Broadcast Address being set as XXXX
XXXX(i.e. all bits don't care). This effectively removes the multiprocessor communications feature,
since any selectivity is disabled.

W78ERD2

Publication Release Date: April 20, 2005

- 43 -

Revision A4

11. PROGRAMMABLE COUNTER ARRAY (PCA)

The PCA is a special 16-bit Timer that has five 16-bit capture/compare modules associated with it.
Each of the modules can be programmed to operate in one of four modes: rising and/or falling edge
capture, software timer, high-speed output, or pulse width modulator. Each module has a pin
associate with it in port 1. module0 is connected to p1.3(CEX0), module1 is connected to p1.4(CEX1),
etc.

PCA Timer/Counter

Module0

Module1

Module2

Module3

Module4

P1.3/CEX0

P1.4/CEX1

P1.5/CEX2

P1.6/CEX3

P1.7/CEX4

time base for PCA modules

Module Functions:
16-bit Capture
16-bit Timer/Compare
16-bit High Speed Output
8-bit PWM
Watchdog Timer (Module 4 Only)

16-bit Up-Counter

Programmable Counter Array (PCA)

Each module in the PCA has a special function register associated with it. These register are:
CCAPM0 for module0, CCAPM1 for module1, etc. The registers contain the bits that control the mode
that each module will operate in. The ECCF bit enables the CCF flag in the CCON SFR to generate an
interrupt when a match or compare occurs in the associated module. PWM enables the pulse width
modulation mode. The TOG bit when set causes the CEX output associated with the module to toggle
when there is a match between the PCA counter and the module's compare/capture register. The
match bit MAT when set will cause the CCF bit in the CCON register to be set when there is a match
between the PCA counter and the module's compare/capture register. The bits CAPP and CAPN
determine the edge that a capture input will be active on. The CAPP bit enables the positive edge, and
the CAPN bit enables the negative edge. If both bits are set both edges will be enabled and a capture
will occur for either transition. The bit ECOM enables the comparator function.
The PCA Timer is a common time base for all five modules and can be programmed to select the
different timer source. The default value is 12 clocks (T) per machine cycle. 12T / 6T can be set by
the option bit. The option bits only are set by the writer. The timer count source is determined from the
CPS1 and CPS2 bits in the CMOD SFR as follows:

CPS1 CPS0

PCA TIMER COUNT SOURCE FOR 12T

PCA TIMER COUNT SOURCE FOR 6T

Oscillator frequency / 12

Oscillator frequency / 6

Oscillator frequency / 4

Oscillator frequency / 2

Timer0 overflow

External input at ECI pin

CMOD(D8H)

W78ERD2

- 44 -

BIT NAME

FUNCTION

7 CILD

Counter idle control: CILD = 0 programs the PCA Counter to continue functioning
during idle mode CILD = 1 programs it to be gated off during idle.

6 WDTE

Watchdog Timer Enable: WDTE = 0 disables Watchdog Timer function on PCA
module 4. WDTE = 1 enables it.

5 -

Reserved

3 -

Reserved

CPS1

PCA Count Pulse Select bit 1

CPS0

PCA Count Pulse Select bit 0

0 ECF

PCA Enable Counter Overflow interrupt: ECF = 1 enables CF bit in CCON to
generate an interrupt. ECF = 0 disables that function of CF.

There are three additional bits associated with the PCA in the CMOD SFR. They are CILD which
allows the PCA to stop during idle mode, WDTE which enables or disables the watchdog function on
module4 (the watchdog timer is executed in module4), and ECF which when set causes an interrupt
and the PCA overflow flag CF to be set when the PCA timer overflows.

CCON(D8H)

BIT NAME

FUNCTION

7 CF

PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF
flags an interrupt if bit ECF in CMOD is set. CF may be set by either hardware or
software but can only be cleared by software.

6 CR

PCA Counter Run control bit. Set by software to turn the PCA counter on. Must
be cleared by software to turn the PCA counter off

5 -

Reserved

4 CCF4

PCA Module4 interrupt flag. Set by hardware when a match or capture occurs.
Must be cleared by software.

3 CCF3

PCA Module3 interrupt flag. Set by hardware when a match or capture occurs.
Must be cleared by software.

2 CCF2

PCA Module2 interrupt flag. Set by hardware when a match or capture occurs.
Must be cleared by software.

1 CCF1

PCA Module1 interrupt flag. Set by hardware when a match or capture occurs.
Must be cleared by software.

0 CCF0

PCA Module0 interrupt flag. Set by hardware when a match or capture occurs.
Must be cleared by software.

W78ERD2

Publication Release Date: April 20, 2005

- 45 -

Revision A4

The CCON SFR contains the run control bit for the PCA and the flags for the PCA timer (CF) and each
module to run the PCA the CR bit (CCON.6) must be set by software. The PCA is turned off by
clearing this bit. The CF bit (CCON.7) is set when the PCA Counter overflows and an interrupt will be
generated if the ECF bit in the CMOD register is set. The CF bit can only be cleared by software.
CCON.0~CCON.4 are the flags for the modules and are set by hardware when either a match or a
capture occurs. These flags also can only be cleared by software.

CCAPMn

CCAPM0(DAH) , CCAPM1(DBH) , CCAPM2(DCH) , CCAPM3(DDH), CCAPM4(DEH)

BIT NAME

FUNCTION

7 -

Reserved

ECOMn

Enable Comparator. ECOMn = 1 enables the comparator function

CAPPn

Capture Positive. CAPPn = 1 enables positive edge capture.

CAPNn

Capture Negative. CAPNn = 1 enables negative edge capture.

3 MATn

Match. When MATn = 1 a match of the PCA counter with this module's
compare/capture register causes the CCFn bit in CCON to be set, flagging
an interrupt.

2 TOGn

Toggle. When TOGn = 1 a match of the PCA counter with this module's
compare/capture register causes the CEXn bit to toggle.

1 PWMn

Pulse Width Modulation Mode. PWMn = 1 enables the CEXn bit to be used
as a pulse width modulated output.

0 ECCFn

Enable CCF interrupt. Enables compare/capture flag CCFn in the CCON
register to generate an interrupt.

MODULE FUNCTION

ECOMN CAPPN CAPNN MATN

TOGN PWMN ECCFN

operation

0 0 0 0 0 0 0

16-bit capture by a positive edge
trigger on CEXn

X 1 0 0 0 0 X

16-bit capture by a negative trigger
on CEXn

X 0 1 0 0 0 X

16-bit capture by a transition on
CEXn

X 1 1 0 0 0 X

16-bit

Software

Timer

1 0 0 1 0 0 X

16-bit

High

Speed

Output

1 0 0 1 1 0 X

8-bit

PWM

1 0 0 0 0 1 0

Watchdog Timer (only in module4)

PCA Module Modes (CCAPMn Register)

W78ERD2

- 46 -

11.1 PCA Capture Mode

To use one of the PCA modules in the capture mode either one or both of the CCAPM bits CAPN and
CAPP for that module must be set. The external CEX input for the module (on port1) is sampled for a
transition. When a valid transition occurs the PCA hardware loads the value of the PCA counter
registers (CH and CL) into the module's capture registers (CCAPnH and CCAPnL). If the
CCFn(CCON) bit for the module and the ECCFn(CCAPMn) bit are set then an interrupt will be
generated.

CCF0

CCF1

CCF2

CCF3

CCF4

CCON(D8H)

CEXn

CCAPnH CCAPnL

ECCFn

PWMn

TOGn

MATn

CAPNn

CAPPn

ECOMn

CCAPMn, n=0~4
(DAH~DEH)

PCA Timer/Counter

PCA INTERRUPT

Capture

To CCFn

PCA Capture Mode

11.2 16-bit Software Timer Comparator Mode

The PCA modules can be used as software timers by setting both the ECOM and MAT bits in the
modules CCAPMn register The PCA timer will be compared to the module's capture registers and
when a match occurs an interrupt will occur if the CCFn(CCON) and the ECCFn(CCAPMn) bits for the
module are both set.

CCF0

CCF1

CCF2

CCF3

CCF4

CCON(D8H)

ECCFn

PWMn

TOGn

MATn

CAPNn

CAPPn

ECOMn

CCAPMn, n=0~4
(DAH~DEH)

Write To
CCAPnL

Write To
CCAPnH

CCAPnH CCAPnL

PCA Timer/Counter

16-bit Comparator

Enable

PCA INTERRUPT

To CCFn

Match

PCA 16-bit Timer Comparator Mode

W78ERD2

Publication Release Date: April 20, 2005

- 47 -

Revision A4

11.3 High Speed Output Mode

In this mode the CEX output (on port1) associated with the PCA module will toggle each time a match
occurs between the PCA counter and the module's capture registers. To activate this mode the TOG,
MAT, and ECOM(CCAPMn) bits must be set.

CCF0

CCF1

CCF2

CCF3

CCF4

CCON(D8H)

ECCFn

PWMn

TOGn

MATn

CAPNn

CAPPn

ECOMn

CCAPMn, n=0~4
(DAH~DEH)

Write To
CCAPnL

Write To
CCAPnH

CCAPnH CCAPnL

PCA Timer/Counter

16-bit Comparator

Enable

PCA INTERRUPT

To CCFn

Match

CEXn

PCA High Speed Output Mode

11.4 Pulse Width Modulator Mode

All of the PCA modules can be use as PWM outputs. The frequency of the output depends on the
source for the PCA timer. All of the modules will have the same frequency of output because they all
share the PCA timer. The duty cycle of each module is independently variable using the module's
capture register CCAPLn When the value of the PCA CL SFR is less than the value in the module's
CCAPLn SFR the output will be low, when it is equal to or greater than the output will be high. When
CL overflows from FF to 00, CCAPLn is reloaded with the value in CCApHn. This allows updating the
PWM with out glitches. The PWM and ECOM(CCAPM) bits must be set to enable the PWM mode.

Enable

CEXn

ECCFn

PWMn

TOGn

MATn

CAPNn

CAPPn

ECOMn

CCAPMn, n=0~4
(DAH~DEH)

PCA Timer/Counter

CCAPnH

CCAPnL

8-BIT

COMPARATOR

Overflow

CL < CCAPnL

CL >= CCAPnL

PAC PWM Mode

W78ERD2

- 48 -

11.5 Watchdog Timer

The Watchdog timer is a free-running timer which can be programmed by the user to serve as a
system monitor. The watchdog timer function is only implemented in module4. However, module4 can
still be used for other modes if the watchdog is not needed. The user pre-loads a 16-bit value in the
compare registers. Just like the other compare modes, this 16-bit value is compared to the PCA timer
value. If a match is allowed to occur, an internal reset will be generated. This will not cause the RST
pin to be high.

ECCF4

PWM4

TOG4

MAT4

CAPN4

CAPP4

ECOM4

CCAPM4(DEH)

Write To
CCAP4H

Write To
CCAP4L

CCAP4H CCAP4L

PCA Timer/Counter

16-bit Comparator

Enable

Match

CIDL

ECF

CPS0

CPS1

WDTE

CMOD(D9H)

Module4

RESET

PCA Watchdog Timer Mode

12. HARDWARE WATCHDOG TIMER (ONE-TIME ENABLED WITH RESET-OUT)

The WDT is intended as a recovery method in situations where the CPU may be subjected to software
upset. The WDT consists of a 14-bit counter and the Watchdog Timer reset (WDTRST) SFR. The
WDT is disabled at reset. To enable the WDT, user must write 01EH and 0E1H in sequence to the
WDTRST, SFR location 0A6H. When WDT is enabled, it will increment every machine cycle while the
oscillator is running and there is no way to disable the WDT except through reset (either hardware
reset or WDT overflow reset). When WDT overflows, it will drive an output reset HIGH pulse at the
RST-pin. It does not need the external pull-down resistor and pull-up CAP on the reset pin.

12.1 Using the WDT

To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location
0A6H. When WDT is enabled, the user needs to service it by writing to 01EH and 0E1H to WDTRST
to avoid WDT overflow. The 14-bit counter overflows when it reaches 3FFFH and this will reset the
device. When WDT is enabled, it will increment every machine cycle while the oscillator is running.
This means the user must reset the WDT at least every 3FFFH machine cycles. To reset the WDT,
the user must write 01EH and 0E1H to WDTRST. WDTRST is a write only register. The WDT counter
cannot be read or written. When WDT overflows, it will generate an output RESET pulse at the reset
pin. To make the best use of the WDT, it should be serviced in those sections of code that will
periodically be executed within the time required to prevent a WDT reset. The RESET high pulse width
is 98 source clock at 12-clock mode, or 49 source clock at 6-clock mode.

W78ERD2

Publication Release Date: April 20, 2005

- 49 -

Revision A4

13. DUAL DPTR

The dual DPTR structure is a way by which the chip will specify the address of an external data
memory location. There are two 16-bit DPTR registers that address the external memory, and a single
bit called DPS = AUXR1/bit0 that allows the program code to switch between them. The DPS bit status
should be saved by software when switching between DPTR0 and DPTR1. Note that bit 2 can't be
written and is always read as a zero. This allows the DPS bit to be quickly toggled simply by executing
an INC DPTR instruction without affecting the GF2 bits.

14. IN-SYSTEM PROGRAMMING (ISP) MODE

The W78ERD2 equips one 64K byte of main Flash EPROM bank for application program (called AP
Flash EPROM) and one 4K byte of auxiliary Flash EPROM bank for loader program (called LD Flash
EPROM). In the normal operation, the microcontroller executes the code in the AP Flash EPROM. If
the content of AP Flash EPROM needs to be modified, the W78ERD2 allows user to activate the In-
System Programming (ISP) mode by setting the CHPCON register. The CHPCON is read-only by
default,

software must write two specific values 87H, then 59H sequentially to the CHPENR

register to enable the CHPCON write attribute. Writing CHPENR register with the values except
87H and 59H will close CHPCON register write attribute.

The W78ERD2 achieves all in-system

programming operations including enter/exit ISP Mode, program, erase, read ... etc, during device in
the idle mode. Setting the bit CHPCON.0 the device will enter in-system programming mode after a
wake-up from idle mode. Because device needs proper time to complete the ISP operations before
awaken from idle mode, software may use timer interrupt to control the duration for device wake-up
from idle mode. To perform ISP operation for revising contents of AP Flash EPROM, software located
at AP Flash EPROM setting the CHPCON register then enter idle mode, after awaken from idle mode
the device executes the corresponding interrupt service routine in LD Flash EPROM. Because the
device will clear the program counter while switching from AP Flash EPROM to LD Flash EPROM, the
first execution of RETI instruction in interrupt service routine will jump to 00H at LD Flash EPROM
area. The device offers software reset for switching back to AP Flash EPROM while the content of AP
Flash EPROM has been updated completely. Setting CHPCON register bit 0, 1 and 7 to logic-1 will
result a software reset to reset the CPU

. The software reset serves as an external reset. This in-

system programming feature makes the job easy and efficient in which the application needs to
update firmware frequently. In some applications, the in-system programming feature make it possible
to easily update the system firmware without opening the chassis.

SFRAH, SFRAL:

The objective address of on-chip Flash EPROM in the in-system programming
mode. SFRFAH contains the high-order byte of address, SFRFAL contains the
low-order byte of address.

SFRFD:

The programming data for on-chip Flash EPROM in programming mode.

SFRCN:

The control byte of on-chip Flash EPROM programming mode.

W78ERD2

- 50 -

SFRCN (C7)

BIT NAME

FUNCTION

7 -

Reserve.

6 WFWIN

On-chip Flash EPROM bank select for in-system programming.
= 0: 64K bytes Flash EPROM bank is selected as destination for re-

programming.

= 1: 4K bytes Flash EPROM bank is selected as destination for re-

programming.

OEN

Flash EPROM output enable.

CEN

Flash EPROM chip enable.

3, 2, 1, 0

CTRL[3:0]

The flash control signals

MODE WFWIN

CTRL<3:0>

OEN

CEN

SFRAH,

SFRAL

SFRFD

Erase 64KB AP Flash
EPROM

0 0010

0 X

Program 64KB AP Flash
EPROM

0001

Address in

Data in

Read 64KB AP Flash
EPROM

0000

Address in

Data out

Erase 4KB LD Flash
EPROM

1 0010

0 X

Program 4KB LD Flash
EPROM

0001

Address in

Data in

Read 4KB LD Flash
EPROM

0000

Address in

Data out

W78ERD2

Publication Release Date: April 20, 2005

- 51 -

Revision A4

15. H/W REBOOT MODE (BOOT FROM LDROM)

By default, the W78ERD2 boots from AP Flash EPROM program after a power on reset. On some
occasions, user can force the W78ERD2 to boot from the LD Flash EPROM program via following
settings. The possible situation that you need to enter H/W REBOOT mode when the AP Flash
EPROM program can not run properly and device can not jump back to LD Flash EPROM to execute
in-system programming function. Then you can use this H/W REBOOT mode to force the W78ERD2
jumps to LD Flash EPROM and executes in-system programming procedure. When you design your
system, you may reserve the pins P2.6, P2.7 to switches or jumpers. For example in a CD-ROM
system, you can connect the P2.6 and P2.7 to PLAY and EJECT buttons on the panel. When the AP
Flash EPROM program fails to execute the normal application program. User can press both two
buttons at the same time and then turn on the power of the personal computer to force the W78ERD2
to enter the H/W REBOOT mode. After power on of personal computer, you can release both buttons
and finish the in-system programming procedure to update the AP Flash EPROM code. In application
system design, user must take care of the P2, P3, ALE, EA and PSEN pin value at reset to prevent
from accidentally activating the programming mode or H/W REBOOT mode.

H/W REBOOT MODE

P4.3 P2.7 P2.6

OPTION

BIT

MODE

Bit4 = L

H/W REBOOT

Bit5 = L

H/W REBOOT

W78ERD2

Publication Release Date: April 20, 2005

- 55 -

Revision A4

Part 2: 4KB LDROM

Procedure of Updating

the 64KB APROM

Timer Interrupt Service Routine:

Stop Timer & disable interrupt

Is F04KBOOT Mode?

(CHPCON.7=1)

Reset the CHPCON Register:

MOV CHPENR,#87H

MOV CHPENR,#59H
MOV CHPCON,#03H

Yes

Setting Timer and enable Timer

interrupt for wake-up .

(15 ms for erasing operation)

Setting erase operation mode:

MOV SFRCN,#22H

(Erase 64KB APROM)

Start Timer and enter IDLE

Mode.

(Erasing...)

End of erase

operation. CPU will

be wakened by Timer

interrupt.

PGM

Setting Timer and enable Timer

interrupt for wake-up .

(50us for program operation)

End of Programming ?

Get the parameters of new code

(Address and data bytes)

through I/O ports, UART or

other interfaces.

Is currently in the

F04KBOOT Mode ?

Setting control registers for

programming:

MOV SFRAH,#ADDRESS_H
MOV SFRAL,#ADDRESS_L
MOV SFRFD,#DATA
MOV SFRCN,#21H

Software reset CPU and
re-boot from the 64KB
APROM.

MOV CHPENR,#87H
MOV CHPENR,#59H
MOV CHPCON,#83H

END

Executing new code

from address

00H in the 64KB APROM.

Hardware Reset

to re-boot from

new 64 KB APROM.

(S/W reset is

invalid in H/W reboot

Mode)

Yes

W78ERD2

- 56 -

16. OPTION BITS

During the on-chip Flash EPROM programming mode, the Flash EPROM can be programmed and
verified repeatedly. Until the code inside the Flash EPROM is confirmed OK, the code can be
protected. The protection of Flash EPROM and those operations on it are described below.

64KB Flash EPROM

Program Memory

AP Flash EPROM

4KB Flash EPROM

Program Memory

LD Flash EPROM

0000H

FFFFH

0FFFH

Reserved

Security Register

Option Bits

B0: Lock bit, Logic 0 is active

B1: MOVC Inhibit, Logic 0 is active

B2: Encryption bit, Logic 0 is active

B3: logic 1 is 12 clock per machine cycle

logic 0 is 6 clock per machine cycle

B4: Enable P2.7 and P2.6 as H/W Reboot Function

logic 1: P2.7 and P2.6 are as I/O Function

logic 0: P2.7 and P2.6 are as H/W Reboot Function

B5: Enable P4.3 as H/W Reboot Function

logic 1: P4.3 is as I/O Function

logic 0: P4.3 is as H/W Reboot Function

B6: Reserved (0)

B7: Logic 1: The Crystal Frequency is above 25MHz

Logic 0: The Crystal Frequency is under 25MHz

Default 1 is for all Security Bits.
The Reserved bit must be kept in logic 1.

Special Setting Register

Lock bit

This bit is used to protect the customer's program code in the W78ERD2. It may be set after the
programmer finishes the programming and verifies sequence. Once this bit is set to logic 0, both the
Flash EPROM data and Special Setting Registers can not be accessed again.

MOVC Inhibit

This bit is used to restrict the accessible region of the MOVC instruction. It can prevent the MOVC
instruction in external program memory from reading the internal program code. When this bit is set to
logic 0, a MOVC instruction in external program memory space will be able to access code only in the
external memory, not in the internal memory. A MOVC instruction in internal program memory space
will always be able to access the ROM data in both internal and external memory. If this bit is logic 1,
there are no restrictions on the MOVC instruction.

Encryption

This bit is used to enable/disable the encryption logic for code protection. Once encryption feature is
enabled, the data presented on port 0 will be encoded via encryption logic. Only whole chip erase will
reset this bit.

Oscillator Control

W78ERD2

Publication Release Date: April 20, 2005

- 57 -

Revision A4

W78ERD2 allow user to diminish the gain of on-chip oscillator amplifier by using programmer to set
the bit B7 of option bits register. Once B7 is set to 0, a half of gain will be decreased. Care must be
taken if user attempts to diminish the gain of oscillator amplifier, reducing a half of gain may
improperly affect the external crystal operation at high frequency above 24 MHz. The value of R and
C1, C2 may need some adjustment while running at lower gain.

17. ELECTRICAL CHARACTERISTICS

17.1 Absolute Maximum Ratings

PARAMETER SYMBOL

MIN.

MAX.

UNIT

DC Power Supply

-0.3 +6.0

Input Voltage

-0.3

+0.3

Operating Temperature

0 70

�

Storage Temperature

-55

+150

�

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability

of the device.

17.2 D.C. Characteristics

= 5V

�

10%, T

= 25

�

C, Fosc = 20 MHz, unless otherwise specified.)

SPECIFICATION

PARAMETER SYM.

MIN. MAX.

UNIT

TEST CONDITIONS

Operating Voltage

4.5 5.5 V

Operating Current

- 20

No load
V

= 5.5V

Idle Current

IDLE

- 10

Idle mode
V

= 5.5V

Power Down Current

PWDN

- 10

�

Power-down mode
V

= 5.5V

Input Current
P1, P2, P3, P4

IN1

-50 +10

�

= 5.5V

= 0V or V

Input Current
RST

IN2

0 +300

�

= 5.5V

0< V

Input Leakage Current
P0, EA

-10 +10

�

= 5.5V

0V< V

< V

Logic 1 to 0 Transition Current
P1, P2, P3, P4

[*4]

-500 -

�

= 5.5V

= 2.0V

Input Low Voltage
P0, P1, P2, P3, P4, EA

IL1

0 0.8

= 4.5V

W78ERD2

- 58 -

D.C. Electrical Characteristics, continued

SPECIFICATION

PARAMETER SYM.

MIN. MAX.

UNIT

TEST CONDITIONS

Input Low Voltage
RST

IL2

0 0.8 V

= 4.5V

Input Low Voltage
XTAL1

[*4]

IL3

0 0.8 V

= 4.5V

Input High Voltage

P0, P1, P2,

P3, P4, EA

IH1

2.4 V

+0.2

= 5.5V

Input High Voltage
RST

IH2

3.5 V

+0.2

= 5.5V

Input High Voltage
XTAL1

[*4]

IH3

3.5 V

+0.2

= 5.5V

Output Low Voltage
P1, P2, P3, P4

OL1

- 0.45

= 4.5V

= +2 mA

Output Low Voltage

P0, ALE, PSEN

[*3]

OL2

- 0.45

= 4.5V

= +4 mA

Sink Current
P1, P3, P4

Isk1 4 8 mA

= 4.5V

= 0.45V

Sink Current

P0, P2, ALE, PSEN

Isk2 10 15 mA

= 4.5V

= 0.45V

Output High Voltage
P1, P2, P3, P4

OH1

2.4 - V

= 4.5V

= -100

�

Output High Voltage

P0, ALE, PSEN

[*3]

OH2

2.4 - V

= 4.5V

= -400

�

Source Current
P1, P2, P3, P4

Isr1 -180 -300

�

= 4.5V

= 2.4V

Source Current

P0, P2, ALE, PSEN

Isr2 -8 -12

= 4.5V

= 2.4V

Notes:

*1. RST pin is a Schmitt trigger input.

*3. P0, ALE and PSEN are tested in the external access mode.
*4. XTAL1 is a CMOS input.

*5. Pins of P1, P2, P3, P4 can source a transition current when they are being externally driven from 1 to 0.

The transition current reaches its maximum value when V

approximates to 2V.

W78ERD2

Publication Release Date: April 20, 2005

- 59 -

Revision A4

17.3 A.C. Characteristics

The AC specifications are a function of the particular process used to manufacture the part, the ratings
of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the specifications
can be expressed in terms of multiple input clock periods (T

), and actual parts will usually

experience less than a

�

20 nS variation. The numbers below represent the performance expected

from a 0.6 micron CMOS process when using 2 and 4 mA output buffers.

Clock Input Waveform

XTAL1

OP,

PARAMETER SYMBOL

MIN.

TYP.

MAX.

UNIT

NOTES

Operating Speed

Fop

MHz

Clock Period

TCP

Clock High

Tch

Clock Low

Tcl

Notes:

1. The clock may be stopped indefinitely in either state.

2. The T

specification is used as a reference in other specifications.

3. There are no duty cycle requirements on the XTAL1 input.

Program Fetch Cycle

PARAMETER SYMBOL

MIN.

TYP.

MAX.

UNIT

NOTES

Address Valid to ALE Low

AAS

1 T

- - nS 4

Address Hold from ALE Low

AAH

1 T

- - nS 1,

ALE Low to

PSEN

Low

APL

1 T

- - nS 4

PSEN

Low to Data Valid

PDA

- -

nS 2

Data Hold after PSEN High

PDH

1 T

nS 3

Data Float after PSEN High

PDZ

1 T

ALE Pulse Width

ALW

2 T

PSEN Pulse Width

PSW

3 T

Notes

P0.0

P0.7, P2.0

P2.7 remain stable throughout entire memory cycle.

2. Memory access time is 3 T

3. Data have been latched internally prior to PSEN going high.

" (due to buffer driving delay and wire loading) is 20 nS.

W78ERD2

- 60 -

Data Read Cycle

PARAMETER SYMBOL

MIN.

TYP.

MAX.

UNIT

NOTES

ALE Low to RD Low

DAR

3 T

CP+

nS 1,

RD Low to Data Valid

DDA

- -

nS 1

Data Hold from RD High

DDH

2 T

Data Float from RD High

DDZ

0 -

RD Pulse Width

DRD

6 T

Notes:

1. Data memory access time is 8 T

" (due to buffer driving delay and wire loading) is 20 nS.

Data Write Cycle

PARAMETER SYMBOL

MIN.

TYP.

MAX.

UNIT

ALE Low to WR Low

DAW

3 T

Data Valid to WR Low

DAD

1 T

- - nS

Data Hold from WR High

DWD

1 T

- - nS

WR Pulse Width

DWR

6 T

Note: "

" (due to buffer driving delay and wire loading) is 20 nS.

Port Access Cycle

PARAMETER SYMBOL

MIN.

TYP.

MAX.

UNIT

Port Input Setup to ALE Low

PDS

1 TCP

Port Input Hold from ALE Low

PDH

0 - - nS

Port Output to ALE

PDA

1 TCP

Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to

ALE, since it provides a convenient reference.

W78ERD2

Publication Release Date: April 20, 2005

- 63 -

Revision A4

19. TYPICAL APPLICATION CIRCUITS

19.1 External Program Memory and Crystal

AD0

A10

A11

A12

A13

A14

A15

27512

AD0

74LS373

AD0

XTAL1

XTAL2

RST

INT0

INT1

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

39
38

21
22

P0.0

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

PSEN

ALE

TXD

RXD

10 u

8.2 K

CRYSTAL

AD1

AD2

AD3

AD4

AD5

AD6

AD7

AD1

AD2

AD3

AD4

AD5

AD6

AD7

GND

A6
A7

AD1

AD2

AD3

AD4

AD5

AD6

AD7

A10

A11

A12

A13

A14

A15

GND

A10

A11

A12

A13

A14

A15

Figure A

CRYSTAL C1 C2 R

6 MHz

47P

16 MHz

30P

24 MHz

15P

32 MHz

10P

6.8K

40 MHz

3 K

Above table shows the reference values for crystal applications.

Notes:

1. C1, C2, R components refer to Figure A

2. Crystal layout must get close to XTAL1 and XTAL2 pins on user's application board.

W78ERD2

- 64 -

Typical Application Circuits, continued

19.2 Expanded External Data Memory and Oscillator

10 u

8.2 K

OSCILLATOR

XTAL1

XTAL2

RST

INT0

INT1

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

P0.0

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

PSEN

ALE

TXD

RXD

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

AD0
AD1

AD2

AD3
AD4

AD5

AD6

AD7

A2
A3

74LS373

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

A10
A11

A12

A13

A14

A10

A11

A12

A13

A14

GND

A8
A9
A10

A11

A12
A13

A14

GND

20256

Figure B

W78ERD2

Publication Release Date: April 20, 2005

- 65 -

Revision A4

20. PACKAGE DIMENSIONS

40-pin DIP

Seating Plane

1. Dimension D Max. & S include mold flash or

tie bar burrs.

2. Dimension E1 does not include interlead flash.
3. Dimension D & E1 include mold mismatch and

are determined at the mold parting line.

6. General appearance spec. should be based on

final visual inspection spec.

1.372

1.219

0.054

0.048

Notes:

Symbol

Min. Nom. Max.

Max.

Nom.

Min.

Dimension in inch

Dimension in mm

0.050

1.27

0.210

5.334

0.010

0.150

0.016

0.155

0.018

0.160

0.022

3.81

0.406

0.254

3.937

0.457

4.064

0.559

0.008

0.120

0.670

0.010

0.130

0.014

0.140

0.203

3.048

0.254

3.302

0.356

3.556

0.540

0.550

0.545

13.72

13.97

13.84

17.01

15.24

14.986

15.494

0.600

0.590

0.610

2.286

2.54

2.794

0.090

0.100

0.110

2.055

2.070

52.20

52.58

0.090

2.286

0.650

0.630

16.00

16.51

protrusion/intrusion.

4. Dimension B1 does not include dambar

5. Controlling dimension: Inches.

Base Plane

44-pin PLCC

Seating Plane

Symbol

Min. Nom. Max.

Max.

Nom.

Min.

Dimension in inch

Dimension in mm

b
c
D

Notes:

on final visual inspection spec.

4. General appearance spec. should be based

3. Controlling dimension: Inches

protrusion/intrusion.

2. Dimension b1 does not include dambar

flash.

1. Dimension D & E do not include interlead

0.020

0.145

0.026

0.016

0.008

0.648

0.590

0.680

0.090

0.150

0.028

0.018

0.010

0.653

0.610

0.690

0.100

0.050

BSC

0.185

0.155

0.032

0.022

0.014

0.658

0.630

0.700

0.110

0.004

0.508

3.683

0.66

0.406

0.203

16.46

14.99

17.27

2.296

3.81

0.711

0.457

0.254

16.59

15.49

17.53

2.54

1.27

4.699

3.937

0.813

0.559

0.356

16.71

16.00

17.78

2.794

0.10

BSC

16.71

16.59

16.46

0.658

0.653

0.648

16.00

15.49

14.99

0.630

0.610

0.590

17.78

17.53

17.27

0.700

0.690

0.680

W78ERD2

- 66 -

Package Dimensions, continued.

44-pin PQFP

Seating Plane

See Detail F

Detail F

1. Dimension D & E do not include interlead

flash.

2. Dimension b does not include dambar

protrusion/intrusion.

3. Controlling dimension: Millimeter
4. General appearance spec. should be based

on final visual inspection spec.

0.254

0.101

0.010

0.004

Notes:

Symbol

Min. Nom. Max.

Max.

Nom.

Min.

Dimension in inch

Dimension in mm

b
c
D

A
A

0.006

0.152

---

0.002

0.075

0.01

0.081

0.014

0.087

0.018

1.90

0.25

0.05

2.05

0.35

2.20

0.45

0.390

0.025

0.063

0.003

0.394

0.031

0.398

0.037

9.9

0.80

0.65

1.6

10.00

0.8

10.1

0.95

0.398

0.394

0.390

0.530

0.520

0.510

13.45

13.2

12.95

10.1

10.00

9.9

0.08

0.031

0.01

0.02

0.25

0.5

---

0.025

0.036

0.635

0.952

0.530

0.520

0.510

13.45

13.2

12.95

0.051

0.075

1.295

1.905

W78ERD2

Publication Release Date: April 20, 2005

- 67 -

Revision A4

21. APPLICATION NOTE

21.1 In-system Programming Software Examples

This application note illustrates the in-system programmability of the Winbond W78ERD2 Flash
EPROM microcontroller. In this example, microcontroller will boot from 64 KB AP Flash EPROM bank
and waiting for a key to enter in-system programming mode for re-programming the contents of 64 KB
AP Flash EPROM. While entering in-system programming mode, microcontroller executes the loader
program in 4KB LD Flash EPROM bank. The loader program erases the 64 KB AP Flash EPROM
then reads the new code data from external SRAM buffer (or through other interfaces) to update the
64KB AP Flash EPROM.

EXAMPLE 1:

;*******************************************************************************************************************
;* Example of 64K AP Flash EPROM program: Program will scan the P1.0. if P1.0 = 0, enters
;* in-system Programming mode for updating the content of AP Flash EPROM code else executes the
;* current ROM code.
;* XTAL = 40 MHz
;*******************************************************************************************************************

.chip 8052
.RAMCHK OFF
.symbols

CHPCON EQU BFH
CHPENR EQU F6H
SFRAL EQU C4H
SFRAH EQU C5H
SFRFD EQU C6H
SFRCN

EQU C7H

ORG

LJMP 100H ; JUMP TO MAIN PROGRAM
;************************************************************************
;* TIMER0 SERVICE VECTOR ORG = 000BH
;************************************************************************
ORG 00BH
CLR TR0 ; TR0 = 0, STOP TIMER0
MOV TL0, R6
MOV TH0, R7
RETI
;************************************************************************
;* 64K AP Flash EPROM MAIN PROGRAM
;************************************************************************
ORG 100H

MAIN_64K:

MOV

P1 ;

SCAN

P1.0

ANL A, #01H
CJNE A, #01H, PROGRAM_64K ; IF P1.0 = 0, ENTER IN-SYSTEM PROGRAMMING MODE
JMP NORMAL_MODE

PROGRAM_64K:
MOV CHPENR, #87H ; CHPENR = 87H, CHPCON REGISTER WRTE ENABLE
MOV CHPENR, #59H ; CHPENR = 59H, CHPCON REGISTER WRITE ENABLE
MOV CHPCON, #03H ; CHPCON = 03H, ENTER IN-SYSTEM PROGRAMMING MODE

W78ERD2

- 68 -

MOV TCON, #00H ; TR = 0 TIMER0 STOP
MOV IP, #00H ; IP = 00H
MOV IE, #82H ; TIMER0 INTERRUPT ENABLE FOR WAKE-UP FROM IDLE MODE
MOV R6, #F0H ; TL0 = F0H
MOV R7, #FFH ; TH0 = FFH
MOV TL0, R6
MOV TH0, R7
MOV TMOD, #01H ; TMOD = 01H, SET TIMER0 A 16-BIT TIMER
MOV TCON, #10H ; TCON = 10H, TR0 = 1, GO
MOV PCON, #01H ; ENTER IDLE MODE FOR LAUNCHING THE IN-SYSTEM
; PROGRAMMABILITY

;********************************************************************************

;* Normal mode 64KB AP Flash EPROM program: depending user's application

;********************************************************************************

NORMAL_MODE:

. ; User's application program

.
.
.

EXAMPLE 2:

;*****************************************************************************************************************************
;* Example of 4KB LD Flash EPROM program: This lorder program will erase the 64KB AP Flash EPROM
;* first,then reads the new ;* code from external SRAM and program them into 64KB AP Flash EPROM bank.
;* XTAL = 40MHz
;*****************************************************************************************************************************

.chip 8052
.RAMCHK OFF
.symbols

CHPCON EQU BFH
CHPENR EQU F6H
SFRAL EQU C4H
SFRAH EQU

C5H

SFRFD EQU C6H
SFRCN EQU C7H

ORG 000H
LJMP 100H ; JUMP TO MAIN PROGRAM

;************************************************************************
;* 1. TIMER0 SERVICE VECTOR ORG = 0BH
;************************************************************************
ORG 000BH
CLR TR0 ; TR0 = 0, STOP TIMER0
MOV TL0, R6
MOV TH0, R7
RETI

;************************************************************************
;* 4KB LD Flash EPROM MAIN PROGRAM
;************************************************************************
ORG 100H

W78ERD2

Publication Release Date: April 20, 2005

- 69 -

Revision A4

MAIN_4K:
MOV SP, #C0H ; BE INITIAL SP REGISTER
MOV CHPENR, #87H ; CHPENR = 87H, CHPCON WRITE ENABLE.
MOV CHPENR, #59H ; CHPENR = 59H, CHPCON WRITE ENABLE.
MOV A, CHPCON
ANL A, #80H
CJNE A, #80H, UPDATE_64K; CHECK H/W REBOOT MODE ?

MOV CHPCON, #03H ; CHPCON = 03H, ENABLE IN-SYSTEM PROGRAMMING.
MOV CHPENR, #00H ; DISABLE CHPCON WRITE ATTRIBUTE

MOV TCON, #00H ; TCON = 00H, TR = 0 TIMER0 STOP
MOV TMOD, #01H ; TMOD = 01H, SET TIMER0 A 16BIT TIMER
MOV IP, #00H ; IP = 00H
MOV IE, #82H ; IE = 82H, TIMER0 INTERRUPT ENABLED
MOV R6, #F0H
MOV R7, #FFH
MOV TL0, R6
MOV TH0, R7
MOV TCON, #10H ; TCON = 10H, TR0 = 1, GO
MOV PCON, #01H ; ENTER IDLE MODE

UPDATE_64K:
MOV CHPENR, #00H ; DISABLE CHPCON WRITE-ATTRIBUTE
MOV TCON, #00H ; TCON = 00H, TR = 0 TIM0 STOP
MOV IP, #00H ; IP = 00H
MOV IE, #82H ; IE = 82H, TIMER0 INTERRUPT ENABLED
MOV TMOD, #01H ; TMOD = 01H, MODE1
MOV R6, #3CH ; SET WAKE-UP TIME FOR ERASE OPERATION, ABOUT 15 mS. DEPENDING
; ON USER'S SYSTEM CLOCK RATE.
MOV R7, #B0H
MOV TL0, R6
MOV TH0, R7

ERASE_P_4K:
MOV SFRCN, #22H ; SFRCN(C7H) = 22H ERASE 64K
MOV TCON, #10H ; TCON = 10H, TR0 = 1, GO
MOV PCON, #01H ; ENTER IDLE MODE (FOR ERASE OPERATION)

;*********************************************************************
;* BLANK CHECK
;*********************************************************************
MOV SFRCN, #0H ; READ 64KB AP Flash EPROM MODE
MOV SFRAH, #0H ; START ADDRESS = 0H
MOV SFRAL, #0H
MOV R6, #FBH ; SET TIMER FOR READ OPERATION, ABOUT 1.5

�

MOV R7, #FFH
MOV TL0, R6
MOV TH0, R7

BLANK_CHECK_LOOP:
SETB

TR0 ;

ENABLE

TIMER

MOV

PCON,

#01H

;

ENTER

IDLE

MODE

MOV A, SFRFD ; READ ONE BYTE

W78ERD2

- 70 -

CJNE A, #FFH, BLANK_CHECK_ERROR
INC

SFRAL ;

ADDRESS

MOV A, SFRAL
JNZ

BLANK_CHECK_LOOP

INC SFRAH
MOV A, SFRAH
CJNE A, #0H, BLANK_CHECK_LOOP ; END ADDRESS = FFFFH
JMP PROGRAM_64KROM

BLANK_CHECK_ERROR:
MOV P1, #F0H
MOV P3, #F0H
JMP $

;*******************************************************************************
;* RE-PROGRAMMING 64KB AP Flash EPROM BANK
;*******************************************************************************
PROGRAM_64KROM:
MOV DPTR, #0H ; THE ADDRESS OF NEW ROM CODE
MOV R2, #00H ; TARGET LOW BYTE ADDRESS
MOV R1, #00H ; TARGET HIGH BYTE ADDRESS
MOV DPTR, #0H ; EXTERNAL SRAM BUFFER ADDRESS
MOV SFRAH, R1 ; SFRAH, TARGET HIGH ADDRESS
MOV SFRCN, #21H ; SFRCN(C7H) = 21 (PROGRAM 64K)
MOV R6, #5AH ; SET TIMER FOR PROGRAMMING, ABOUT 50

�

MOV R7, #FFH
MOV TL0, R6
MOV TH0, R7

PROG_D_64K:

MOV SFRAL, R2 ; SFRAL(C4H) = LOW BYTE ADDRESS
MOVX A, @DPTR ; READ DATA FROM EXTERNAL SRAM BUFFER
MOV SFRFD, A ; SFRFD(C6H) = DATA IN
MOV TCON, #10H ; TCON = 10H, TR0 = 1, GO
MOV PCON, #01H ; ENTER IDLE MODE (PRORGAMMING)
INC DPTR
INC R2
CJNE R2, #0H, PROG_D_64K
INC R1
MOV

SFRAH,

CJNE R1, #0H, PROG_D_64K

;*****************************************************************************
; * VERIFY 64KB AP Flash EPROM BANK
;*****************************************************************************
MOV R4, #03H ; ERROR COUNTER
MOV R6, #FBH ; SET TIMER FOR READ VERIFY, ABOUT 1.5

�

MOV R7, #FFH
MOV TL0, R6
MOV TH0, R7
MOV DPTR, #0H ; The start address of sample code
MOV R2, #0H ; Target low byte address
MOV R1, #0H ; Target high byte address
MOV SFRAH, R1 ; SFRAH, Target high address
MOV SFRCN, #00H ; SFRCN = 00 (Read ROM CODE)

W78ERD2

Publication Release Date: April 20, 2005

- 71 -

Revision A4

READ_VERIFY_64K:
MOV SFRAL, R2 ; SFRAL(C4H) = LOW ADDRESS
MOV TCON, #10H ; TCON = 10H, TR0 = 1, GO
MOV PCON, #01H
INC R2
MOVX A, @DPTR
INC DPTR
CJNE A, SFRFD, ERROR_64K
CJNE R2, #0H, READ_VERIFY_64K
INC R1
MOV

SFRAH,

CJNE R1, #0H, READ_VERIFY_64K

;******************************************************************************
;* PROGRAMMING COMPLETLY, SOFTWARE RESET CPU
;******************************************************************************
MOV CHPENR, #87H ; CHPENR = 87H
MOV CHPENR, #59H ; CHPENR = 59H
MOV CHPCON, #83H ; CHPCON = 83H, SOFTWARE RESET.

ERROR_64K:
DJNZ R4, UPDATE_64K ; IF ERROR OCCURS, REPEAT 3 TIMES.
. ; IN-SYSTEM PROGRAMMING FAIL, USER'S PROCESS TO DEAL WITH IT.
.
.
.

21.2 How to Use Programmable Counter Array

Please refer to Winbond website

http://www.winbond.com.tw

to get the application note.

W78ERD2

- 72 -

22. VERSION HISTORY

VERSION DATE PAGE

DESCRIPTION

June 2004

Initial Issued

August 2004

Modify the content of PCA

Add the application of PCA

A3 Sep.

30,

2004 38

Add Enhanced full duplex serial port with framing error
detection and automatic address recognition

April 20, 2005

Add Important Notice

Important Notice

Winbond products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal
instruments, combustion control instruments, or for other applications intended to support or
sustain life. Further more, Winbond products are not intended for applications wherein failure
of Winbond products could result or lead to a situation wherein personal injury, death or
severe property or environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sales.

Headquarters

No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5665577
http://www.winbond.com.tw/

Taipei Office

TEL: 886-2-8177-7168
FAX: 886-2-8751-3579

Winbond Electronics Corporation America

2727 North First Street, San Jose,
CA 95134, U.S.A.
TEL: 1-408-9436666
FAX: 1-408-5441798

Winbond Electronics (H.K.) Ltd.

No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong

FAX: 852-27552064

Unit 9-15, 22F, Millennium City,

TEL: 852-27513100

Please note that all data and specifications are subject to change without notice.

All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.

Winbond Electronics (Shanghai) Ltd.

200336 China

FAX: 86-21-62365998

27F, 2299 Yan An W. Rd. Shanghai,

TEL: 86-21-62365999

Winbond Electronics Corporation Japan

Shinyokohama Kohoku-ku,
Yokohama, 222-0033

FAX: 81-45-4781800

7F Daini-ueno BLDG, 3-7-18

TEL: 81-45-4781881

9F, No.480, Rueiguang Rd.,

Neihu District, Taipei, 114,

Taiwan, R.O.C.

Электронный компонент: W78ERD2A40DN