WV3HG2256M72AER-D6

April 2006
Rev. 1

ADVANCED*

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

4GB 2x256Mx72 DDR2 SDRAM RDIMM, w/PLL

DESCRIPTION

The WV3HG2256M72AER is a 2x256Mx72 Double Data
Rate DDR2 SDRAM high density module based on 1Gb
DDR2 SDRAM components. This memory module consists
of eighteen stacks of 256Mx4 bit with 8 banks DDR2
Synchronous DRAMs in FBGA packages, two - 14 bit
registered buffers in BGA packages mounted on a 240-pin
DIMM FR4 substrate.

* This product is under development, is not qualifi ed or characterized and is subject to

change without notice.

NOTE: Consult factory for availability of:

· Vendor source control options
· Industrial temperature option

FEATURES

240-pin, dual in-line memory module (DIMM)

Fast data transfer rates: PC2-6400*, PC2-5300*,
PC2-4300 and PC2-3200

Support ECC error detection and correction

= V

CCQ

= 1.8V± 0.1V

CCSPD

= +1.7V to +3.6V

JEDEC standard 1.8V I/O (SSTL_18-compatible)

Differential data strobe (DQS, DQS#) option

Four-bit prefetch architecture

DLL to align DQ and DQS transitions with CK

Multiple internal device banks for concurrent
operation

Supports duplicate output strobe (RDQS/RDQS#)

Programmable CAS# latency (CL): 3, 4, 5* and 6*

Adjustable data-output drive strength

On-die termination (ODT)

Serial Presence Detect (SPD) with EEPROM

Auto & self refresh: 64ms 8,192 cycle refresh

Gold edge contacts

RoHS

compliant

Dual

Rank

Package

option

· 240 Pin DIMM

· PCB 30.00mm (1.181") TYP

OPERATING FREQUENCIES

PC2-3200

PC2-4300

PC2-5300*

PC2-6400*

Clock Speed

200MHz

266MHz

333MHz

400MHz

CL-t

RCD

-t

3-3-3

4-4-4

5-5-5

6-6-6

* Consult factory for availability

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April 2006
Rev. 1

PIN CONFIGURATION

Pin No.

Symbol

Pin No.

Symbol

Pin No.

Symbol

Pin No.

Symbol

REF

121

181

CCQ

122

DQ4

182

DQ0

123

DQ5

183

DQ1

124

184

125

DM0/DQS9

185

CK0

DQS0#

126

NC/DQS9#

186

CK0#

DQS0

127

187

128

DQ6

188

DQ2

129

DQ7

189

DQ3

A10/AP

130

190

BA1

BA0

131

DQ12

191

CCQ

DQ8

CCQ

132

DQ13

192

RAS#

DQ9

WE#

133

193

CS0#

CAS#

134

DM1/DQS10

194

CCQ

DQS1#

CCQ

135

NC/DQS10#

195

ODT0

DQS1

CS1#

136

196

A13

ODT1

137

197

RESET#

CCQ

138

198

139

199

DQ36

DQ32

140

DQ14

200

DQ37

DQ10

DQ33

141

DQ15

201

DQ11

142

202

DM4/DQS13

DQS4#

143

DQ20

203

NC/DQS13#

DQ16

DQS4

144

DQ21

204

DQ17

145

205

DQ38

DQ34

146

DM2/DQS11

206

DQ39

DQS2#

DQ35

147

NC/DQS11#

207

DQS2

148

208

DQ44

DQ40

149

DQ22

209

DQ45

DQ18

DQ41

150

DQ23

210

DQ19

151

211

DM5/DQS14

DQS5#

152

DQ28

212

NC/DQS14#

DQ24

DQS5

153

DQ29

213

DQ25

154

214

DQ46

DQ42

155

DM3/DQS12

215

DQ47

DQS3#

DQ43

156

NC/DQS12#

216

DQS3

157

217

DQ52

DQ48

158

DQ30

218

DQ53

DQ26

DQ49

159

DQ31

219

DQ27

100

160

220

101

SA2

161

CB4

221

CB0

102

162

CB5

222

CB1

103

163

223

DM6/DQS15

104

DQS6#

164

DM8DQS17

224

NC/DQS15#

DQS8#

105

DQS6

165

NC/DQS17#

225

DQS8

106

166

226

DQ54

107

DQ50

167

CB6

227

DQ55

CB2

108

DQ51

168

CB7

228

CB3

109

169

229

DQ60

110

DQ56

170

CCQ

230

DQ61

CCQ

111

DQ57

171

CKE1

231

CKE0

112

172

232

DM7/DQS16

113

DQS7#

173

233

NC/DQS16#

BA2

114

DQS7

174

234

115

175

CCQ

235

DQ62

CCQ

116

DQ58

176

A12

236

DQ63

A11

117

DQ59

177

237

118

178

238

SPD

119

SDA

179

239

SA0

120

SCL

180

240

SA1

PIN NAMES

Pin Name

Function

A0-A13

Address Inputs

BA0,BA2

SDRAM Bank Address

DQ0-DQ63

Data Input/Output

CB0-CB7

Check Bits

DQS0-DQS17

Data strobes

DQS0#-DQS17#

Data strobes complement

DM0-DM8

Data Masks

ODT0, ODT1

On-die termination control

CK0,CK0#

Clock Inputs, positive line

CKE0, CKE1

Clock Enables

CS0#, CS1#

Chip Selects

RAS#

Row Address Strobe

CAS#

Column Address Strobe

WE#

Write Enable

RESET#

SA0-SA2

SPD address

SDA

SPD Data Input/Output

SCL

SPD Clock Input

Core Power

CCQ

I/O Power

Ground

REF

Power Supply for Reference

SPD

SPD Power supply

No connect

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FUNCTIONAL BLOCK DIAGRAM

Serial PD

SA0 SA1 SA2

SCL

SDA

CCSPD

CCQ

REF

Serial PD

DDR2 SDRAMs

P
L
L

CK0

CK0#

RESET#**

PCK0-PCK6, PCK8, PCK9

CK : DDR2 SDRAMs

PCK0#-PCK6#, PCK8#, PCK9#

CK# : DDR2 SDRAMs

PCK7

CK : Register

PCK7#

CK# : Register

VSS

RCS0#

DQS0

DQS0#

CS#

DQS DQS#

DQ0
DQ1
DQ2
DQ3

I/O 0
I/O 1
I/O 2
I/O 3

DM0/DQS9
NC/DQS9#

DQ4
DQ5
DQ6
DQ7

I/O 0
I/O 1
I/O 2
I/O 3

DQS1

DQS1#

DQ8
DQ9
DQ10
DQ11

I/O 0
I/O 1
I/O 2
I/O 3

DM1/DQS10
NC/DQS10#

DQ12
DQ13
DQ14
DQ15

I/O 0
I/O 1
I/O 2
I/O 3

DQS2

DQS2#

DQ16
DQ17
DQ18
DQ19

I/O 0
I/O 1
I/O 2
I/O 3

DM2/DQS11
NC/DQS11#

DQ20
DQ21
DQ22
DQ23

I/O 0
I/O 1
I/O 2
I/O 3

DQS3

DQS3#

DQ24
DQ25
DQ26
DQ27

I/O 0
I/O 1
I/O 2
I/O 3

DM3/DQS12
NC/DQS12#

DQ28
DQ29
DQ30
DQ31

I/O 0
I/O 1
I/O 2
I/O 3

DQS5

DQS5#

DQ40
DQ41
DQ42
DQ43

I/O 0
I/O 1
I/O 2
I/O 3

DM5/DQS14
NC/DQS14#

DQ44
DQ45
DQ46
DQ47

I/O 0
I/O 1
I/O 2
I/O 3

DQS4

DQS4#

DQ32
DQ33
DQ34
DQ35

I/O 0
I/O 1
I/O 2
I/O 3

DM4/DQS13
NC/DQS13#

DQ36
DQ37
DQ38
DQ39

I/O 0
I/O 1
I/O 2
I/O 3

DQS6

DQS6#

DQ48
DQ49
DQ50
DQ51

I/O 0
I/O 1
I/O 2
I/O 3

DM6/DQS15
NC/DQS15#

DQ52
DQ53
DQ54
DQ55

I/O 0
I/O 1
I/O 2
I/O 3

DQS8

DQS8#

CB0
CB1
CB2
CB3

I/O 0
I/O 1
I/O 2
I/O 3

DM8/DQS17
NC/DQS17#

CB4
CB5
CB6
CB7

I/O 0
I/O 1
I/O 2
I/O 3

DQS#7
DQS7#

DQ56
DQ57
DQ58
DQ59

I/O 0
I/O 1
I/O 2
I/O 3

DM7/DQS16
NC/DQS16#

DQ60
DQ61
DQ62
DQ63

I/O 0
I/O 1
I/O 2
I/O 3

RCS1#

CS#

DQS DQS#

CS#

DQS DQS#

CS#

DQS DQS#

CS#

DQS DQS#

CS#

DQS DQS#

CS#

DQS DQS#

CS#

DQS DQS#

CS#

DQS DQS#

CS#

DQS DQS#

CS#

DQS DQS#

CS#

DQS DQS#

CS#

DQS DQS#

CS#

DQS DQS#

CS#

DQS DQS#

CS#

DQS DQS#

CS#

DQS DQS#

CS#

DQS DQS#

CS#

DQS DQS#

CS#

DQS DQS#

CS#

DQS DQS#

CS#

DQS DQS#

CS#

DQS DQS#

CS#

DQS DQS#

CS#

DQS DQS#

CS#

DQS DQS#

CS#

DQS DQS#

CS#

DQS DQS#

CS#

DQS DQS#

CS#

DQS DQS#

CS#

DQS DQS#

CS#

DQS DQS#

CS#

DQS DQS#

CS#

DQS DQS#

CS#

DQS DQS#

CS#

DQS DQS#

1:2

R
E
G

S
T
E
R

RST#

CS1#

BA0-BA2
A0-A13
RAS#
CAS#
WE#
CKE0
CKE1

RESET#**

PCK7**

PCK7#**

RCS1# CS# : DDR2 SDRAMs
RBA0-RBA2

BA0-BA2 : DDR2 SDRAMs

RA0-RA13

A0-A13 : DDR2 SDRAMs

RRAS#

RAS#

DDR2

SDRAMs

RCAS#

CAS#

DDR2

SDRAMs

RWE#

WE#

DDR2

SDRAMs

RCKE0

CKE : DDR2 SDRAMs

RCKE1

CKE : DDR2 SDRAMs

ODT0
ODT1

RODT0

ODT : DDR2 SDRAMs

RODT1

ODT : DDR2 SDRAMs

CS0#

RCS0# CS# : DDR2 SDRAMs

NOTE: All resistor values are 22 ohms unless otherwise specifi ed.
** RESET#, PCK7 and PCK7# connect to both registers. Other signals connect to one of two registers.

WV3HG2256M72AER-D6

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White Electronic Designs

April 2006
Rev. 1

RECOMMENDED DC OPERATING CONDITIONS

All Voltages Referenced to V

Parameter

Symbol

Rating

Units

Notes

Min.

Type

Max.

Supply Voltage

1.7

1.8

1.9

I/O Input Reference Voltage

REF

0.49*V

0.50*V

0.51*V

I/O Termination Voltage

REF

-0.04

REF

+0.04

SPD Supply Voltage

CCSPD

1.7

3.6

Notes:
1. VREF is expected to equal VCCQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed ±1 percent of the

DC value. Peak-to-peak AC noise on VREF may not exceed ±2 percent of VREF. This measurement is to be taken at the nearest VREF bypass capacitor..

2. V

is not applied directly to the device. V

is a system supply for signal termination resistors, is expected to be set equal to V

REF

and must track variations in the DC level of V

REF

3. V

CCQ

of all IC's are tied to V

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Min

Max

Units

Voltage on V

pin relative to V

-0.5

2.3

, V

OUT

Voltage on any pin relative to V

-0.5

2.3

STG

Storage Temperature

-55

100

°C

Input leakage current; Any input 0V<V

; V

REF

input 0V<V

<0.95V;

Other pins not under test = 0V

Command/Address,
RAS#, CAS#, WE#,
CS#, CKE
CK, CK#
DM

-10

µA

Output leakage current; 0V<V

OUT

CCQ

; DQs and ODT are disable

DQ, DQS, DQS#

-10

µA

VREF

REF

leakage current; V

REF

= Valid V

REF

level

-72

µA

CAPACITANCE

= 25°C, f = 100MHz, V

= 1.8V

Parameter

Symbol

Min

Max

Units

Input Capacitance: (A0 ~ A13, BA0 ~ BA2, RAS#, CAS#, WE#)

IN1

Input Capacitance: (CKE0, CKE1), (ODT0, ODT1)

IN2

Input Capacitance: (CS0#, CS1#)

IN3

Input Capacitance: (CK0, CK0#)

IN4

Input Capacitance: (DM0 ~ DM8), (DQS0 ~ DQ17)

IN5 (665)

IN5 (534, 403)

Input/Output Capacitance: (DQ0 ~ DQ63), (CB0 ~ CB7)

OUT1 (665)

OUT1 (534, 403)

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OPERATING TEMPERATURE CONDITION

Parameter

Symbol

Rating

Units

Notes

Operating temperature (commercial)

TOPER

0 to +85°C

°C

1, 2

Notes:
1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JEDED JESD51.2
2. At 0°C to +85°C, operation temperature range, all DRAM specifi cation will be supported.

INPUT DC LOGIC LEVEL

All voltages referenced to V

Parameter

Symbol

Min

Max

Units

Input High (Logic 1) Voltage

(DC)

REF

+ 0.125

+ 0.300

Input Low (Logic 0) Voltage

(DC)

-0.300

REF

- 0.125

INPUT AC LOGIC LEVEL

All voltages referenced to V

Parameter

Symbol

Min

Max

Units

AC Input High (Logic 1) Voltage DDR2-400 & DDR-533

(AC)

REF

+ 0.250

AC Input High ( Logic 1) Voltage DDR2-667*

(AC)

REF

+ 0.200

AC Input Low (Logic 0) Voltage DDR2-400 & DDR2-533

(AC)

REF

- 0.250

AC Input Low (Logic 0) Voltage DDR2-667*

(AC)

REF

- 0.200

* Consult factory for availability

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April 2006
Rev. 1

DDR2 I

SPECIFICATIONS AND CONDITIONS

= +1.8V ± 0.1V

Symbol Proposed Conditions

806

665

534

403

Units

CC0*

Operating one bank active-precharge current;
t

= t

), t

= t

), t

RAS

= t

RAS

min(I

); CKE is HIGH, CS# is HIGH between valid commands;

Address bus inputs are SWITCHING; Data bus inputs are SWITCHING

TBD

2,336

2,246

2,156

CC1*

Operating one bank active-read-precharge current;
I

OUT

= 0mA; BL = 4, CL = CL(I

), AL = 0; t

= t

), t

= t

), t

RAS

= t

RAS

min(I

), t

RCD

); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING;

Data pattern is same as I

CC4W

TBD

2,516

2,426

2,336

CC2P**

Precharge power-down current;
All banks idle; t

= t

); CKE is LOW; Other control and address bus inputs are STABLE; Data

bus inputs are FLOATING

TBD

932

CC2Q**

Precharge quiet standby current;
All banks idle; t

= t

); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are

STABLE; Data bus inputs are FLOATING

TBD

1,940

1,760

CC2N**

Precharge standby current;
All banks idle; t

= t

); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are

SWITCHING; Data bus inputs are SWITCHING

TBD

2,120

1,940

CC3P**

Active power-down current;
All banks open; t

= t

); CKE is LOW; Other control and

address bus inputs are STABLE; Data bus inputs are FLOATING

Fast PDN Exit MRS(12) = 0

TBD

1,580

1,400

Slow PDN Exit MRS(12) = 1

TBD

932

CC3N**

Active standby current;
All banks open; t

= t

), t

RAS

= t

RAS

max(I

), t

= t

); CKE is HIGH, CS# is HIGH between

valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING

TBD

2,300

2,120

CC4W*

Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(I

), AL = 0; t

= t

), t

RAS

max(I

), t

= t

); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs

are SWITCHING; Data bus inputs are SWITCHING

TBD

3,056

2,876

2,516

CC4R*

Operating burst read current;
All banks open, Continuous burst reads, I

OUT

= 0mA; BL = 4, CL = CL(I

), AL = 0; t

= t

), t

RAS

max(I

), t

= t

); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs

are SWITCHING; Data pattern is same as I

CC4W

TBD

3,056

2,876

2,516

CC5B**

Burst auto refresh current;
t

= t

); Refresh command at every t

RFC

) interval; CKE is HIGH, CS# is HIGH between valid

commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING

TBD

8,420

8,240

8,060

CC6**

Self refresh current;
CK and CK# at 0V; CKE 0.2V; Other control and address bus
inputs
are FLOATING; Data bus inputs are FLOATING

Normal

TBD

360

CC7*

Operating bank interleave read current;
All bank interleaving reads, I

OUT

= 0mA; BL = 4, CL = CL(I

), AL = t

D(I

)-1*t

); t

= t

), t

RRD

= t

RRD

), t

RCD

= 1*t

); CKE is HIGH, CS# is HIGH between valid commands;

Address bus inputs are STABLE during DESELECTs; Data pattern is same as I

CC4R

; Refer to the

following page for detailed timing conditions

TBD

6,116

5,756

5,396

Note:
I

specs are based on SAMSUNG components. Other DRAM manufacturers parameters may be different.

* Value calculated as one module rank in this operation condition, and all other module ranks in I

CC2P

(CKE LOW) mode.

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AC TIMING PARAMETERS

= +1.8V ± 0.1V

AC Characteristics

806

665

534

403

Parameter

Symbol

Min

Max

Min

Max

Min

Max

Min

Max

Unit

Clock

Clock cycle time

CL = 6

CK (6)

TBD

CL = 5

CK (5)

TBD

3,000

8,000

CL = 4

CK (4)

TBD

3,750

8,000

3,750

8,000

5,000

8,000

CL = 3

CK (3)

TBD

5,000

8,000

5,000

8,000

5,000

8,000

CK high-level width

TBD

0.45

0.55

0.45

0.55

0.45

0.55

CK low-level width

TBD

0.45

0.55

0.45

0.55

0.45

0.55

Half clock period

TBD

MIN
(t

)

MIN
(t

)

MIN
(t

)

Clock jitter

JIT

TBD

125

Data

DQ output access time from CK/CK#

TBD

-450

+450

-500

+500

-600

+600

Data-out high-impedance window from CK/CK#

TBD

(

MAX)

(

MAX)

(

MAX)

Data-out low-impedance window from CK/CK#

TBD

(MIN)

(MAX)

(MIN)

(MAX)

(MIN)

(MAX)

DQ and DM input setup time relative to DQS

TBD

100

150

DQ and DM input hold time relative to DQS

TBD

175

225

275

DQ...DQS hold, DQS to fi rst DQ to go nonvalid,
per access relative to DQS

DIPW

TBD

0.35

Data hold skew factor

QHS

TBD

340

400

450

DQDQS hold, DQS to fi rst DQ to go nonvalid,
per access

TBD

QHS

Data valid output window (DVW)

DVW

TBD

DQSQ

Data Strobe

DQS input high pulse width

DQSH

TBD

0.35

DQS input low pulse width

DQSL

TBD

0.35

DQS output access time from CK/CK#

DQSCK

TBD

-400

+400

-450

+450

-500

+500

DQS falling edge to CK rising setup time

DSS

TBD

0.2

DQS falling edge from CK rising hold time

DSH

TBD

0.2

DQSDQ skew, DQS to last DQ valid, per group,
per access

DQSQ

TBD

240

300

350

DQS read preamble

RPRE

TBD

0.9

1.1

0.9

1.1

0.9

1.1

Note:

· AC specifi cation is based on SAMSUNG components. Other DRAM manufactures specifi cation may be different.

Continued on next page

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Rev. 1

AC TIMING PARAMETERS (Continued)

= +1.8V ± 0.1V

AC Characteristics

806

665

534

403

Parameter

Symbol

Min

Max

Min

Max

Min

Max

Min

Max

Unit

Data Strobe

DQS read preamble

RPST

TBD

0.4

0.6

0.4

0.6

0.4

0.6

DQS write preamble setup time

WPRES

TBD

DQS write preamble

WPRE

TBD

0.35

DQS write postamble

WPST

TBD

0.4

0.6

0.4

0.6

0.4

0.6

Write command to fi rst DQS latching
transition

DQSS

TBD

WL-0.25

WL+0.25

WL-0.25

WL+0.25

WL-0.25

WL+0.25

Command and

Address

Address and control input pulse width
for each input

IPW

TBD

0.6

Address and control input setup time

ISa

TBD

200

250

350

Address and control input hold time

IHa

TBD

275

375

475

CAS# to CAS# command delay

CCD

TBD

Active to Active (same bank) command

TBD

Active bank a to Active b bank
command

RRD

TBD

7.5

Active to Read or Write delay

RCD

TBD

Four Bank Activate period

FAW

TBD

37.5

Active to precharge command

RAS

TBD

70,000

Internal Read to precharge command
delay

RTP

TBD

7.5

Write recovery time

TBD

Auto precharge write recovery and
precharge time

DAL

TBD

Interval Write to Read command delay

WTR

TBD

7.5

Precharge command period

TBD

Precharge All command period

RPA

TBD

Load Mode command cycle time

MRD

TBD

CKE low to CK,CK# uncertainty

DELAY

TBD

Note:

· AC specifi cation is based on SAMSUNG components. Other DRAM manufactures specifi cation may be different.

Continued on next page

WV3HG2256M72AER-D6

ADVANCED

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

April 2006
Rev. 1

AC TIMING PARAMETERS (Continued)

= +1.8V ± 0.1V

AC Characteristics

806

665

534

403

Parameter

Symbol

Min

Max

Min

Max

Min

Max

Min

Max

Unit

Refresh to Active or Refresh to Refresh
command interval

RFC

TBD

127.5

70,000

127.5

70,000

127.5

70,000

Average periodic refresh interval

REFI

TBD

7.8

µs

Exit self refresh to non-read command

XSNR

TBD

RFC

(MIN)

+10

RFC

(MIN)

+10

RFC

(MIN)

+10

Exit self refresh to read command

XSRD

TBD

200

Exit self refresh timing reference

ISXR

TBD

ODT

ODT turn-on delay

AOND

TBD

ODT turn-on

AON

TBD

AC(MIN)

AC(MAX)

+1,000

AC(MIN)

AC(MAX)

+1,000

AC(MIN)

AC(MAX)

+1,000

ODT turn-off delay

AOFD

TBD

2.5

ODT turn-off

AOF

TBD

AC(MIN)

AC(MAX)

+600

AC(MIN)

AC(MAX)

+600

AC(MIN)

AC(MAX)

+600

ODT turn-on (power-down mode)

AONPD

TBD

AC(MIN)

+2,000

2x t

(MAX)

+ 1,000

AC(MIN)

+2,000

2x t

(MAX)

+ 1,000

AC(MIN)

+2,000

2x t

(MAX)

+ 1,000

ODT turn-off (power-down mode)

AOFPD

TBD

AC(MIN)

+2,000

2.5x t

+ t

(MAX)

1,000

AC(MIN)

+2,000

2.5x t

+ t

(MAX)

1,000

AC(MIN)

+2,000

2.5x t

+ t

(MAX)

1,000

ODT to power-down entry latency

ANPD

TBD

ODT power-down exit latency

AXPD

TBD

Power-Down

Exit active power-down to READ
command, MR[bit12=0]

XARD

TBD

Exit active power-down to READ
command, MR[bit12=1]

XARDS

TBD

7-AL

6-AL

Exit precharge power-down to any non-
READ command.

TBD

CKE minimum high/low time

CKE

TBD

Note:

· AC specifi cation is based on SAMSUNG components. Other DRAM manufactures specifi cation may be different.

WV3HG2256M72AER-D6

ADVANCED

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

April 2006
Rev. 1

30.50 (1.201)
29.851 (1.175)

PIN 1

17.80 (0.700)

TYP.

5.0 (0.197) TYP.

4.843 (123.0)

TYP.

1.0 (0.039)

TYP.

0.80 (0.032)

TYP.

4.00 (0.158)

(4X)

PIN 120

133.50 (5.256)
133.20 (5.244)

63.0 (2.480)

TYP.

55.0 (2.165)

TYP.

10.00 (0.394)

TYP.

BACK VIEW

FRONT VIEW

PIN 240

PIN 121

1.37 (0.054)
1.17 (0.046)

0.270 (6.73)

MAX

1.50 (0.059)

3.00 (0.118)

(4X)

5.175 (0.204)

(2X)

Detail B

PACKAGE DIMENSIONS FOR D6

* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)

ORDERING INFORMATION FOR D6

Part Number

Speed/Data Rate

CAS Latency

RCD

Height*

W3HG2256M72ACER806D6xxG**

400MHz/800Mb/s

30.00mm (1.181") TYP

W3HG2256M72ACER665D6xxG**

333MHz/667Mb/s

30.00mm (1.181") TYP

W3HG2256M72ACER534D6xxG

266MHz/533Mb/s

30.00mm (1.181") TYP

W3HG2256M72ACER403D6xxG

200MHz/400Mb/s

30.00mm (1.181") TYP

** Contact factory for availability
Notes:

· RoHS compliant product. (G = RoHS Compliant)

· Vendor specifi c part numbers are used to provide memory component source control. The place holder for this is shown as a lower case "x"

in the part numbers above and is to be replaced with respective vendors code. Consult factory for qualifi ed sourcing options.
(M = Micron, S = Samsung & consult factory for others)

· Consult factory for availability of industrial temperature (-40°C to 85°C) option

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