WV3HG2128M72EEU-D6

August 2006
Rev. 1

ADVANCED*

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

2GB 2x128Mx72 DDR2 SDRAM UNBUFFERED DIMM

DESCRIPTION

The WV3HG2128M72EEU is a 2x128Mx72 Double Data
Rate DDR2 SDRAM high density module. This memory
module consists of eighteen 128Mx8 bit with 4 banks
DDR2 Synchronous DRAMs in FBGA packages, mounted
on a 240-pin DIMM FR4 substrate.

* This product is under development, is not qualifi ed or characterized and is subject to

change or cancellation without notice.

NOTE: Consult factory for availability of:

· Vendor source control options
· Industrial temperature option
· Parity

function

FEATURES

Unbuffered 240-pin, dual in-line memory module
Fast data transfer rates: PC2-6400*, PC2-5300*,

PC2-4300 and PC2-3200

= V

CCQ

= 1.8V

CCSPD

= +1.7V to +3.6V

Differential data strobe (DQS, DQS#) option
Four-bit prefetch architecture
DLL to align DQ and DQS transitions with CK
Multiple internal device banks for concurrent

operation

Supports duplicate output strobe (RDQS/RDQS#)
Programmable CAS# latency (CL): 3, 4, 5* and 6*
Adjustable data-output drive strength
On-die termination (ODT)
Serial Presence Detect (SPD) with EEPROM
Auto & self refresh (64ms/8,192 cycle refresh)
Gold edge contacts
Dual

Rank

RoHS

compliant

Package

option

· 240 Pin DIMM
· 30.00mm (1.181") TYP

OPERATING FREQUENCIES

PC2-6400*

PC2-5300*

PC2-4300

PC2-3200

Clock Speed

400MHz

333MHz

266MHz

200MHz

CL-t

RCD

-t

6-6-6

5-5-5

4-4-4

3-3-3

* Consult factory for availability

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August 2006
Rev. 1

PIN CONFIGURATION

Pin No.

Symbol

Pin No.

Symbol

Pin No.

Symbol

Pin No.

Symbol

REF

121

181

122

DQ4

182

DQ0

123

DQ5

183

DQ1

124

184

125

DM0

185

CK0

DQS0#

126

186

CK0#

DQS0

127

187

128

DQ6

188

DQ2

129

DQ7

189

DQ3

A10/AP

130

190

BA1

BA0

131

DQ12

191

DQ8

132

DQ13

192

RAS#

DQ9

WE#

133

193

CS0#

CAS#

134

DM1

194

DQS1#

135

195

ODT0

DQS1

CS1#

136

196

A13

ODT1

137

CK1

197

138

CK1#

198

139

199

DQ36

DQ32

140

DQ14

200

DQ37

DQ10

DQ33

141

DQ15

201

DQ11

142

202

DM4

DQS4#

143

DQ20

203

DQ16

DQS4

144

DQ21

204

DQ17

145

205

DQ38

DQ34

146

DM2

206

DQ39

DQS2#

DQ35

147

207

DQS2

148

208

DQ44

DQ40

149

DQ22

209

DQ45

DQ18

DQ41

150

DQ23

210

DQ19

151

211

DM5

DQS5#

152

DQ28

212

DQ24

DQS5

153

DQ29

213

DQ25

154

214

DQ46

DQ42

155

DM3

215

DQ47

DQS3#

DQ43

156

216

DQS3

157

217

DQ52

DQ48

158

DQ30

218

DQ53

DQ26

DQ49

159

DQ31

219

DQ27

100

160

220

CK2

101

SA2

161

CB4

221

CK2#

CB0

102

162

CB5

222

CB1

103

163

223

DM6

104

DQS6#

164

DM8

224

DQS8#

105

DQS6

165

225

DQS8

106

166

226

DQ54

107

DQ50

167

CB6

227

DQ55

CB2

108

DQ51

168

CB7

228

CB3

109

169

229

DQ60

110

DQ56

170

230

DQ61

111

DQ57

171

CKE1

231

CKE0

112

172

232

DM7

113

DQS7#

173

233

BA2

114

DQS7

174

234

115

175

235

DQ62

116

DQ58

176

A12

236

DQ63

A11

117

DQ59

177

237

118

178

238

SPD

119

SDA

179

239

SA0

120

SCL

180

240

SA1

PIN NAMES

Pin Name

Function

A0-A13

Address Inputs

BA0,BA2

SDRAM Bank Address

DQ0-DQ63

Data Input/Output

CB0-CB7

Check Bits

DQS0-DQS8

Data strobes

DQS0#-DQS8#

Data strobes complement

DM0-DM8

Data masks

ODT0, ODT1

On-die termination controls

CK0,CK0#-CK2,CK2# Clock Inputs
CKE0, CKE1

Clock Enables

CS0#, CS1#

Chip Selects

RAS#

Row Address Strobe

CAS#

Column Address Strobe

WE#

Write Enable

SA0-SA2

SPD address

SDA

SPD Data Input/Output

SCL

SPD Clock Input

Power Supply

Ground

REF

Power Supply Reference

SPD

SPD Power

Spare pins, No connect

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FUNCTIONAL BLOCK DIAGRAM

CS0#

DQS0

DQS0#

DM0

DM/
RDQS

CS#

DQS

DQS#

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7

DQS1

DQS1#

DM1

DQS2

DQS2#

DM2

DQS3

DQS3#

DM3

DQS5

DQS5#

DM5

DQS4

DQS4#

DM4

DQS6

DQS6#

DM6

DQS7

DQS7#

DM7

CS1#

BA0-BA2

A0-A13

RAS#

CAS#

WE#

CKE0

CKE1

ODT0

ODT1

BA0-BA2: DDR 2 SDRAMs

A0-A13: DDR 2 SDRAMs

RAS#: DDR 2 SDRAMs

CAS#: DDR 2 SDRAMs

WE#: DDR 2 SDRAMs

CKE0: DDR 2 SDRAMs

CKE1: DDR 2 SDRAMs

ODT0: DDR 2 SDRAMs

ODT1: DDR 2 SDRAMs

CS0#

CS1#: DDR 2 SDRAMs

CS0#: DDR 2 SDRAMs

Serial PD

SA0

SA1

SDA

SCL

*Wire per Clock Loading
Table/Wiring Diagrams

Notes:
1. DQ, DM, DQS/DQS# resistors: 5.1 Ohms +/-5%
2. BAx, Ax RAS#, CAS#, WE# resistors: 5.1 Ohms +/- 5%

*Clock Wiring

Clock
Input

DDR2 SDRAMs

*CK0/CK0#

*CK1/CK1#

*CK2/CK2#

6 DDR2 SDRAMs

SA2

DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7

DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23

I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7

DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39

I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7

DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47

I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7

DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55

I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7

DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7

CCSPD

Serical PD

DDR2 SDRAMs

CC\

CCQ

VREF

DM/
RDQS

CS#

DQS

DQS#

DM/
RDQS

CS#

DQS

DQS#

DM/
RDQS

CS#

DQS

DQS#

DM/
RDQS

CS#

DQS

DQS#

DM/
RDQS

CS#

DQS

DQS#

DM/
RDQS

CS#

DQS

DQS#

DM/
RDQS

CS#

DQS

DQS#

DQS8

DQS8#

DM8

CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7

I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7

DM/
RDQS

CS#

DQS

DQS#

DM/
RDQS

CS#

DQS

DQS#

DM/
RDQS

CS#

DQS

DQS#

DM/
RDQS

CS#

DQS

DQS#

DM/
RDQS

CS#

DQS

DQS#

DM/
RDQS

CS#

DQS

DQS#

DM/
RDQS

CS#

DQS

DQS#

DM/
RDQS

CS#

DQS

DQS#

DM/
RDQS

CS#

DQS

DQS#

DM/
RDQS

CS#

DQS

DQS#

NOTE: All resistor values are 22 ohms unless otherwise specifi ed.

WV3HG2128M72EEU-D6

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August 2006
Rev. 1

DC OPERATING CONDITIONS

All voltages referenced to V

Parameter

Symbol

Min

Typical

Max

Unit

Notes

Supply Voltage

1.7

1.8

1.9

I/O Reference Voltage

REF

0.49 x V

0.50 x V

0.51 x V

I/O Termination Voltage

REF

-0.04

REF

+0.04

SPD Supply Voltage

CCSPD

1.7

3.6

Notes:
1

REF

is expected to equal V

CC/2

of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on

REF

may not exceed +/-1 percent of the

DC value. Peak-to-peak AC noise on V

REF

may not exceed +/-2 percent of V

REF

. This measurement is to be taken at the nearest V

REF

bypass capacitor.

2. V

is not applied directly to the device. V

is a system supply for signal termination resistors, is expected to be set equal to V

REF

and must track variations in the DC level of V

REF

3. V

CCQ

of all IC's are tied to V

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Min

Max

Units

Voltage on V

pin relative to V

-0.5

2.3

, V

OUT

Voltage on any pin relative to V

-0.5

2.3

STG

Storage Temperature

-55

100

°C

Input leakage current; Any input 0V<V

; V

REF

input

0V,V

,0.95V; Other pins not under test = 0V

Command/Address,
RAS#, CAS#, WE#,

-90

µA

CS#, CKE

-45

µA

CK, CK#

-30

µA

-10

µA

Output leakage current; 0V<V

; DQs and ODT are disable

DQ, DQS, DQS#

-10

µA

VREF

REF

leakage current; V

REF

= Valid V

REF

level

-36

µA

INPUT/OUTPUT CAPACITANCE

= 25°C, f = 100MHz

Parameter

Symbol

Min

Max

Unit

Input Capacitance (A0-A13, BA0~BA2, RAS#, CAS#, WE#)

IN1

Input Capacitance (CKE0, CKE1), (ODT0, ODT1)

IN2

Input Capacitance (CS0#, CS1#))

IN3

Input Capacitance (CK0, CK0#-CK2, CK2#)

IN4

Input Capacitance (DQS0~DQS8), (DM0-DM8)

IN5 (665)

IN5 (534, 403)

Input Capacitance (DQ0~DQ63), (CB0~CB7)

OUT (665)

OUT (534, 403)

WV3HG2128M72EEU-D6

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White Electronic Designs

August 2006
Rev. 1

OPERATING TEMPERATURE CONDITION

Parameter

Symbol

Rating

Units

Notes

Operating Temperature (Commercial)

TOPER

0ºC to 85ºC

ºC

1, 2

Notes:
1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JEDEC JESD51.2.
2. At 0 - 85

ºC, operation temperature range, all DRAM specifi cation will be supported.

INPUT DC LOGIC LEVEL

All voltages referenced to V

Parameter

Symbol

Min

Max

Units

Input High (Logic 1) Voltage

IH(DC)

REF

+ 0.125

+ 0.300

Input Low (Logic 0) Voltage

IL(DC)

-0.300

REF

- 0.125

INPUT AC LOGIC LEVEL

All voltages referenced to V

Parameter

Symbol

Min

Max

Units

AC Input Low (Logic 1) Voltage DDR2-400 & DDR2-533

IL(AC)

REF

+ 0.250

AC Input High (Logic 1) Voltage DDR2-667

IH(AC)

REF

+ 0.200

AC Input Low (Logic 0) Voltage DDR2-400 & DDR2-533

IL(AC)

REF

- 0.250

AC Input Low (Logic 0) Voltage DDR2-667

IL(AC)

REF

- 0.200

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DDR2 I

SPECIFICATIONS AND CONDITIONS

DDR2 SDRAM components only

Symbol Proposed Conditions

806

665

553

403

Units

CC0*

Operating one bank active-precharge current;
t

= t

), t

= t

), t

RAS

= t

RAS

min(I

); CKE is HIGH, CS# is HIGH between valid

commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING

TBD

918

873

828

CC1*

Operating one bank active-read-precharge current;
I

OUT

= 0mA; BL = 4, CL = CL(I

), AL = 0; t

= t

), t

= t

), t

RAS

= t

RAS

min(I

), t

RCD

= t

RCD

); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are

SWITCHING; Data pattern is same as I

TBD

1,008

963

918

CC2P*

Precharge power-down current;
All banks idle; t

= t

); CKE is LOW; Other control and address bus inputs are STABLE;

Data bus inputs are FLOATING

TBD

216

CC2Q**

Precharge quiet standby current;
All banks idle; t

= t

); CKE is HIGH, CS# is HIGH; Other control and address bus inputs

are STABLE; Data bus inputs are FLOATING

TBD

720

630

CC2N**

Precharge standby current;
All banks idle; t

= t

); CKE is HIGH, CS# is HIGH; Other control and address bus inputs

are SWITCHING; Data bus inputs are SWITCHING

TBD

810

720

CC3P**

Active power-down current;
All banks open; t

= t

); CKE is LOW; Other control and

address bus inputs are STABLE; Data bus inputs are FLOATING

Fast PDN Exit MRS(12) = 0

TBD

540

450

Slow PDN Exit MRS(12) = 1

TBD

216

CC3N**

Active standby current;
All banks open; t

= t

), t

RAS

= t

RAS

max(I

), t

= t

); CKE is HIGH, CS# is HIGH

between valid commands; Other control and address bus inputs are SWITCHING; Data bus
inputs are SWITCHING

TBD

900

810

CC4W*

Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(I

), AL = 0; t

= t

), t

RAS

max(I

), t

= t

); CKE is HIGH, CS# is HIGH between valid commands; Address bus

inputs are SWITCHING; Data bus inputs are SWITCHING

TBD

1,503

1,278

1,143

CC4R*

Operating burst read current;
All banks open, Continuous burst reads, I

OUT

= 0mA; BL = 4, CL = CL(I

), AL = 0; t

= t

RAS

= t

RAS

max(I

), t

= t

); CKE is HIGH, CS# is HIGH between valid commands; Address

bus inputs are SWITCHING; Data pattern is same as I

TBD

1,503

1,278

1,143

CC5B**

Burst auto refresh current;
t

= t

); Refresh command at every t

RFC

) interval; CKE is HIGH, CS# is HIGH between

valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING

TBD

3,960

3,870

3,780

CC6**

Self refresh current;
CK and CK\ at 0V; CKE 0.2V; Other control and address bus
inputs are FLOATING; Data bus inputs are FLOATING

Normal

TBD

180

CC7*

Operating bank interleave read current;
All bank interleaving reads, I

OUT

= 0mA; BL = 4, CL = CL(I

), AL = t

D(I

)-1*t

); t

), t

= t

), t

RRD

= t

RRD

), t

RCD

= 1*t

); CKE is HIGH, CS# is HIGH between

valid commands; Address bus inputs are STABLE during DESELECTs; Data bus inputs are
SWITCHING.

TBD

2,808

2,628

2,448

Note: I

specifi cation is based on

SAMSUNG components. Other DRAM Manufacturers specifi cation may be different.

*: Value calculated as one module rank in this operating condition, and all other module ranks in I

CC2P

(CKE LOW) mode.

**: Value calculated refl ects all module ranks in this operating condition.

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Rev. 1

AC TIMING PARAMETERS & SPECIFICATIONS

AC CHARACTERISTICS

806

665

534

403

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

Clock

Clock cycle time

CL = 6

CK (6)

TBD

CL = 5

CK (5)

TBD

3,000

8,000

CL = 4

CK (4)

TBD

3,750

8,000

3,750

8,000

5,000

8,000

CL = 3

CK (3)

TBD

5,000

8,000

5,000

8,000

5,000

8,000

CK high-level width

TBD

0.45

0.55

0.45

0.55

0.45

0.55

CK low-level width

TBD

0.45

0.55

0.45

0.55

0.45

0.55

Half clock period

TBD

MIN

CH,

)

MIN

CH,

)

MIN

CH,

)

Clock jitter

JIT

TBD

-125

125

-125

125

-125

125

Data

DQ output access time from CK/CK#

TBD

-450

+450

-500

+500

-600

+600

Data-out high-impedance window from
CK/CK#

TBD

AC(MAX)

Data-out low-impedance window from
CK/CK#

TBD

AC(MIN)

AC(MAX)

AC(MIN)

AC(MAX)

AC(MIN)

AC(MAX)

DQ and DM input setup time relative to
DQS

TBD

100

150

DQ and DM input hold time relative to DQS

TBD

225

275

DQ and DM input pulse width (for each
input)

DIPW

TBD

0.35

Data hold skew factor

QHS

TBD

340

400

450

DQ...DQS hold, DQS to fi rst DQ to go
nonvalid, per access

TBD

HP -

QHS

HP -

QHS

HP -

QHS

Data valid output window (DVW)

DVW

TBD

QH -

DQSQ

QH -

DQSQ

QH -

DQSQ

Data Strobe

DQS input high pulse width

DQSH

TBD

0.35

DQS input low pulse width

DQSL

TBD

0.35

DQS output access time from CK/CK#

DQSCK

TBD

-400

+400

-450

+450

-500

+500

DQS falling edge to CK rising ... setup time

DSS

TBD

0.2

DQS falling edge from CK rising ... hold
time

DSH

TBD

0.2

DQS...DQ skew, DQS to last DQ valid, per

group,

per access

DQSQ

TBD

240

300

350

DQS read preamble

RPRE

TBD

0.9

1.1

0.9

1.1

0.9

1.1

DQS read postamble

RPST

TBD

0.4

0.6

0.4

0.6

0.4

0.6

DQS write preamble setup time

WPRES

TBD

DQS write preamble

WPRE

TBD

0.35

DQS write postamble

WPST

TBD

0.4

0.6

0.4

0.6

0.4

0.6

Write command to fi rst DQS latching
transition

DQSS

TBD

WL-

0.25

WL+

0.25

WL-

0.25

WL+

0.25

WL-

0.25

WL+

0.25

Address and control input pulse width for

each input

IPW

TBD

0.6

Address and control input setup time

TBD

200

250

Address and control input hold time

TBD

275

375

475

Address and control input hold time

CCD

TBD

* AC specifi cation is based on

SAMSUNG components. Other DRAM manufactures specifi cation may be different.

Continued on next page

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Rev. 1

AC TIMING PARAMETERS (cont'd)

AC CHARACTERISTICS

806

665

534

403

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

Command and

Address

ACTIVE to ACTIVE (same bank) command

TBD

ACTIVE bank a to ACTIVE bank b command

RRD

TBD

7.5

ACTIVE to READ or WRITE delay

RCD

TBD

Four Bank Activate period

FAW

TBD

37.5

ACTIVE to PRECHARGE command

RAS

TBD

70,000

Internal READ to precharge command delay

RTP

TBD

7.5

Write recovery time

TBD

Auto precharge write recovery + precharge

time

DAL

TBD

Internal WRITE to READ command delay

WTR

TBD

7.5

PRECHARGE command period

TBD

PRECHARGE ALL command period

RPA

TBD

LOAD MODE command cycle time

MRD

TBD

CKE low to CK,CK# uncertainty

DELAY

TBD

Self Refresh

REFRESH to Active of Refresh to Refresh

command interfal

RFC

TBD

127.5

70,000

127.5

70,000

127.5

70,000

Average periodic refresh interval

REFI

TBD

7.8

µs

Exit self refresh to non-READ command

XSNR

TBD

RFC(MIN)

+10

RFC(MIN)

+10

RFC(MIN)

+10

Exit self refresh to READ command

XSRD

TBD

200

Exit self refresh timing reference

ISXR

TBD

ODT

ODT turn-on delay

AOND

TBD

ODT turn-on

AON

TBD

AC(MIN)

AC(MAX)

+1000

AC(MIN)

AC(MAX)

+1000

AC(MIN)

AC(MAX)

+1000

ODT turn-off delay

AOFD

TBD

2.5

ODT turn-off

AOF

TBD

AC(MIN)

AC(MAX)

+600

AC(MIN)

AC(MAX)

+600

AC(MIN)

AC(MAX)

+600

ODT turn-on (power-down mode)

AONPD

TBD

AC(MIN)

+2000

2 x t

AC(MAX)

+1000

AC(MIN)

+2000

2 x t

AC(MAX)

+1000

AC(MIN)

+2000

2 x t

AC(MAX)

+1000

ODT turn-off (power-down mode)

AOFPD

TBD

AC(MIN)

+2000

2.5 x

AC(MAX)

+1000

AC(MIN)

+2000

2.5 x

AC(MAX)

+1000

AC(MIN)

+2000

2.5 x

AC(MAX)

+1000

ODT to power-down entry latency

ANPD

TBD

ODT power-down exit latency

AXPD

TBD

Power-Down

Exit active power-down to READ command,

MR[bit12=0]

XARD

TBD

Exit active power-down to READ command,

MR[bit12=1]

XARDS

TBD

7-AL

6-AL

A Exit precharge power-down to any non-

READ command.

TBD

CKE minimum high/low time

CKE

TBD

* AC specifi cation is based on

SAMSUNG components. Other DRAM manufactures specifi cation may be different.

WV3HG2128M72EEU-D6

ADVANCED

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

August 2006
Rev. 1

30.50 (1.201)
29.85 (1.175)

PIN 1

17.80 (0.700)

TYP.

5.0 (0.197) TYP.

123.0 (4.843)

TYP.

1.0 (0.039)

TYP.

0.80 (0.032)

TYP.

4.00 (0.158)

(4X)

PIN 120

FRONT VIEW

133.50 (5.256)
133.20 (5.244)

63.0 (2.480)

TYP.

55.0 (2.165)

TYP.

10.00 (0.394)

TYP.

BACK VIEW

PIN 240

PIN 121

1.37 (0.054)
1.17 (0.046)

4.00 (0.158)

MAX

1.50 (0.059)

3.00 (0.118)

(4X)

5.175 (0.204)

(2X)

PACKAGE DIMENSIONS FOR D6

** ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)

ORDERING INFORMATION FOR D6

Part Number

Speed/Data Rate

Frequency

CAS Latency

RCD

Height**

WV3HG2128M72EEU806D6xxG*

400MHz/800Mb/s

30.00mm (1.181") TYP

WV3HG2128M72EEU665D6xxG*

333MHz/667Mb/s

30.00mm (1.181") TYP

WV3HG2128M72EEU534D6xxG

266MHz/533Mb/s

30.00mm (1.181") TYP

WV3HG2128M72EEU403D6xxG

200MHz/400Mb/s

30.00mm (1.181") TYP

* Contact factory for availability
NOTES:

· RoHS compliant product. (G = RoHS Compliant)

Vendor

specifi c part numbers are used to provide memory component source control. The place holder for this is shown as a lower case "x"

in the part numbers above and is to be replaced with respective vendors code. Consult factory for qualifi ed sourcing options.
(M = Micron, S = Samsung & consult factory for others)

· Consult factory for availability of industrial temperature (-40°C to 85°C) option

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