WV3HG128M72AER-AD6

March 2005
Rev. 1

ADVANCED*

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

1GB 128Mx72 DDR2 SDRAM RDIMM, VLP

DESCRIPTION

The WV3HG128M72AER is a 128Mx72 Double Data Rate
DDR2 SDRAM high density module. This memory module
consists of eighteen 128Mx4 bit with 4 banks DDR2
Synchronous DRAMs in FBGA packages, mounted on a
VLP 240-pin DIMM FR4 substrate.

* This product is under development, is not qualifi ed or characterized and is subject to

change or cancellation without notice.

NOTE: Consult factory for availability of:

· Vendor source control options
· Industrial temperature option

FEATURES

VLP (very low profi le) 240-pin, dual in-line memory
module

Fast data transfer rates: PC2-6400*, PC2-5300*,
PC2-4300 and PC2-3200

Utilizes 800*, 667*, 533 and 400 Mb/s DDR2
SDRAM components

= V

CCQ

= 1.8V

JEDEC standard 1.8V I/O (SSTL_18-compatible)

Differential data strobe (DQS, DQS#) option

Four-bit prefetch architecture

DLL to align DQ and DQS transitions with CK

Multiple internal device banks for concurrent
operation

Supports duplicate output strobe (RDQS/RDQS#)

Programmable CAS# latency (CL): 3, 4, 5* and 6*

Adjustable data-output drive strength

On-die termination (ODT)

Posted CAS# latency: 0, 1, 2, 3 and 4

Serial Presence Detect (SPD) with EEPROM

Auto &self refresh (64ms: 8,192 cycle refresh)

Gold edge contacts

RoHS

compliant

Package

option

· 240 Pin DIMM VLP

· PCB 18.29mm (0.720") Max

OPERATING FREQUENCIES

PC2-3200

PC2-4300

PC2-5300*

PC2-6400*

Clock Speed

200MHz

266MHz

333MHz

400MHz

CL-t

RCD

-t

3-3-3

4-4-4

5-5-5

6-6-6

* Consult factory for availability

WV3HG128M72AER-AD6

ADVANCED

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

March 2005
Rev. 1

PIN CONFIGURATION

Pin No.

Symbol

Pin No.

Symbol

Pin No.

Symbol

Pin No.

Symbol

REF

121

181

CCQ

122

DQ4

182

DQ0

123

DQ5

183

DQ1

124

184

125

DM0/DQS9

185

CK0

DQS0#

126

NC/DQS9#

186

CK0#

DQS0

127

187

128

DQ6

188

DQ2

129

DQ7

189

DQ3

A10/AP

130

190

BA1

BA0

131

DQ12

191

CCQ

DQ8

CCQ

132

DQ13

192

RAS#

DQ9

WE#

133

193

S0#

CAS#

134

DM1/DQS10

194

CCQ

DQS1#

CCQ

135

NC/DQS10#

195

ODT0

DQS1

136

196

A13

137

197

RESET#

CCQ

138

198

139

199

DQ36

DQ32

140

DQ14

200

DQ37

DQ10

DQ33

141

DQ15

201

DQ11

142

202

DM4/DQS13

DQS4#

143

DQ20

203

NC/DQS13#

DQ16

DQS4

144

DQ21

204

DQ17

145

205

DQ38

DQ34

146

DM2/DQS11

206

DQ39

DQS2#

DQ35

147

NC/DQS11#

207

DQS2

148

208

DQ44

DQ40

149

DQ22

209

DQ45

DQ18

DQ41

150

DQ23

210

DQ19

151

211

DM5/14

DQS5#

152

DQ28

212

NC/DQS14#

DQ24

DQS5

153

DQ29

213

DQ25

154

214

DQ46

DQ42

155

DM3/DQS12

215

DQ47

DQS3#

DQ43

156

NC/DQS12#

216

DQS3

157

217

DQ52

DQ48

158

DQ30

218

DQ53

DQ26

DQ49

159

DQ31

219

DQ27

100

160

220

101

SA2

161

CB4

221

CB0

102

162

CB5

222

CB1

103

163

223

DM6/DQS15

104

DQS6#

164

DM8/DQS17

224

NC/DQS15#

DQS8#

105

DQS6

165

NC/DQS17#

225

DQS8

106

166

226

DQ54

107

DQ50

167

CB6

227

DQ55

CB2

108

DQ51

168

CB7

228

CB3

109

169

229

DQ60

110

DQ56

170

CCQ

230

DQ61

CCQ

111

DQ57

171

231

CKE0

112

172

232

DM7/DQS16

113

DQS7#

173

233

NC/DQS16#

114

DQS7

174

234

115

175

CCQ

235

DQ62

CCQ

116

DQ58

176

A12

236

DQ63

A11

117

DQ59

177

237

118

178

238

SPD

119

SDA

179

239

SA0

120

SCL

180

240

SA1

PIN NAMES

Pin Name

Function

CK0,CK0#

Clock Inputs

CKE0

Clock Enable

CB0-CB7

Check Bits

RAS#

Row Address Strobe

CAS#

Column Address Strobe

WE#

Write Enable

S0#

Chip Select

A0-A13

Address Inputs

BA0,BA1

SDRAM Bank Address

ODT0

On-die termination control

SCL

SPD Clock Input

SDA

SPD Data Input/Output

SA0-SA2

SPD address

DQ0-DQ63

Data Input/Output

DM0-DM8

Data Masks

DQS0-DQS17

Data strobes

DQS0#-DQS17#

Data strobes complement

CC,

CCQ

Core and I/O Power

Ground

REF

Input/Output Reference

SPD

SPD Power

No connect

RESET#

Reset Input

WV3HG128M72AER-AD6

ADVANCED

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

March 2005
Rev. 1

FUNCTIONAL BLOCK DIAGRAM

Serial PD

SA0 SA1 SA2

SCL

SDA

CCSPD

CCQ

REF

Serial PD

DDR2 SDRAMs

1:2

R
E
G

S
T
E
R

RST#

S0#

BA0 - BA1

A0 - A13

RAS#

CAS#

WE#

CKE0

ODT0

RESET#

PCK7

PCK7#

P
L
L

CK0

CK0#

RESET#

PCK0-PCK6, PCK8, PCK9

CK : DDR2 SDRAMs

PCK0#-PCK6#, PCK8#, PCK9#

CK# : DDR2 SDRAMs

PCK7

CK : Register

PCK7#

CK# : Register

RS0# : DDR2 SDRAMs

RBA0 - RBA1 : DDR2 SDRAMs

RA0 - RA13 : DDR2 SDRAMs

RRAS# : DDR2 SDRAMs

RCAS# : DDR2 SDRAMs

RWE# : DDR2 SDRAMs

RCKE0 : DDR2 SDRAMs

RODT0 : DDR2 SDRAMs

RS0#

DQ0
DQ1
DQ2
DQ3

I/O 0
I/O 1
I/O 2
I/O 3

CS# DQS DQS#

DQS0

DQS0#

DQS1

DQS1#

DQ8
DQ9

DQ10
DQ11

I/O 0
I/O 1
I/O 2
I/O 3

CS# DQS DQS#

DQS2

DQS2#

DQ16
DQ17
DQ18
DQ19

I/O 0
I/O 1
I/O 2
I/O 3

CS# DQS DQS#

DQS3

DQS3#

DQ24
DQ25
DQ26
DQ27

I/O 0
I/O 1
I/O 2
I/O 3

CS# DQS DQS#

DQS4

DQS4#

DQ32
DQ33
DQ34
DQ35

I/O 0
I/O 1
I/O 2
I/O 3

CS# DQS DQS#

DQS5

DQS5#

DQ40
DQ41
DQ42
DQ43

I/O 0
I/O 1
I/O 2
I/O 3

CS# DQS DQS#

DQS6

DQS6#

DQ48
DQ49
DQ50
DQ51

I/O 0
I/O 1
I/O 2
I/O 3

CS# DQS DQS#

DQS7

DQS7#

DQ56
DQ57
DQ58
DQ59

I/O 0
I/O 1
I/O 2
I/O 3

CS# DQS DQS#

DQS8

DQS8#

CB0
CB1
CB2
CB3

I/O 0
I/O 1
I/O 2
I/O 3

CS# DQS DQS#

DQ4
DQ5
DQ6
DQ7

I/O 0
I/O 1
I/O 2
I/O 3

CS# DQS DQS#

DM0/DQS9

NC/DQS9#

DM1/DQS10

NC/DQS10#

DQ12
DQ13
DQ14
DQ15

I/O 0
I/O 1
I/O 2
I/O 3

CS# DQS DQS#

DM2/DQS11

NC/DQS11#

DQ20
DQ21
DQ22
DQ23

I/O 0
I/O 1
I/O 2
I/O 3

CS# DQS DQS#

DM3/DQS12

NC/DQS12#

DQ28
DQ29
DQ30
DQ31

I/O 0
I/O 1
I/O 2
I/O 3

CS# DQS DQS#

DM4/DQS13

NC/DQS13#

DQ36
DQ37
DQ38
DQ39

I/O 0
I/O 1
I/O 2
I/O 3

CS# DQS DQS#

DM5/DQS14

NC/DQS14#

DQ44
DQ45
DQ46
DQ47

I/O 0
I/O 1
I/O 2
I/O 3

CS# DQS DQS#

DM6/DQS15

NC/DQS15#

DQ52
DQ53
DQ54
DQ55

I/O 0
I/O 1
I/O 2
I/O 3

CS# DQS DQS#

DM7/DQS16

NC/DQS16#

DQ60
DQ61
DQ62
DQ63

I/O 0
I/O 1
I/O 2
I/O 3

CS# DQS DQS#

DM8/DQS17

NC/DQS17#

CB4
CB5
CB6
CB7

I/O 0
I/O 1
I/O 2
I/O 3

CS# DQS DQS#

NOTE: All resistor values are 22 ohms unless otherwise specifi ed.

WV3HG128M72AER-AD6

ADVANCED

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

March 2005
Rev. 1

DC OPERATING CONDITIONS

All voltages referenced to V

Parameter

Symbol

Min

Typical

Max

Unit

Notes

Supply Voltage

1.7

1.8

1.9

I/O Reference Voltage

REF

0.49 x V

0.50 x V

0.51 x V

I/O Termination Voltage

REF

-0.04

REF

+0.04

SPD Supply Voltage

CCSPD

1.7

3.6

Notes:
1

REF

is expected to equal V

CC/2

of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on

REF

may not exceed +/-1 percent of the

DC value. Peak-to-peak AC noise on V

REF

may not exceed +/-2 percent of V

REF

. This measurement is to be taken at the nearest V

REF

bypass capacitor.

2. V

is not applied directly to the device. V

is a system supply for signal termination resistors, is expected to be set equal to V

REF

and must track variations in the DC level of V

REF

3. V

CCQ

of all IC's are tied to V

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Min

Max

Units

Voltage on V

pin relative to V

-0.5

2.3

, V

OUT

Voltage on any pin relative to V

-0.5

2.3

STG

Storage Temperature

-55

100

°C

Input leakage current; Any input 0V<V

; V

REF

input

0V,V

,0.95V; Other pins not under test = 0V

Command/Address,
RAS#, CAS#, WE#,

-5

µA

CK, CK#

-10

µA

-2

µA

Output leakage current; 0V<V

; DQs and ODT are disable

DQ, DQS, DQS#

-5

µA

VREF

REF

leakage current; V

REF

= Valid V

REF

level

-36

µA

Power dissipaion

CAPACITANCE

= 25°C, f = 100MHz, V

= V

CCQ

= 1.8V

Parameter

Symbol

Max

Units

Input Capacitance: CK, CK#

CCK

Input Capacitance: CKE, CS#

Input Capacitance: Addr. RAS#, CAS#, WE#

Input/Output Capacitance: DQ, DQS, DM, DQS#

Note: Based on

SAMSUNG

components

WV3HG128M72AER-AD6

ADVANCED

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

March 2005
Rev. 1

OPERATING TEMPERATURE CONDITION

Parameter

Symbol

Rating

Units

Notes

Operating Case Temperature (Commercial)

TOPER

0 to +85°C

°C

1, 2

NOTE:
1. Operation temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JEDEC JESD51.2
2. At 0 - 85

°C, operation temperature range, all DRAM specifi cation will be supported.

INPUT DC LOGIC LEVEL

All voltages referenced to V

Parameter

Symbol

Min

Max

Unit

Input High (Logic 1) Voltage

(DC)

REF

+ 0.125

+ 0.300

Input High (Logic 0) Voltage

(DC)

-0.300

REF

- 0.125

INPUT AC LOGIC LEVEL

All voltages referenced to V

Parameter

Symbol

Min

Max

Unit

AC Input High (Logic 1) Voltage

(AC)

REF

+ 0.250

AC Input High (Logic 0) Voltage

(AC)

REF

- 0.250

INPUT/OUTPUT CAPACITANCE

TA=25°C, f=100MHz

Parameter

Symbol

Min

Max

Unit

Input capacitance (0A~A13, BA0~BA1,
RAS#, CAS#, WE#)

6.5

7.5

Input capacitance (CKE0), (ODT0)

6.5

7.5

Input capacitance (CS0#)

6.5

7.5

Input capacitance (CK0, CK0#)

Input capacitance (DQS0 ~ DQS17,
DQS0# ~ DQS17#)

5 (534, 403)

6.5

Input capacitance (DQ0~DQ63),
(CB0~CB7)

OUT

1 (534, 403)

6.5

Notes: Based on ELPIDA components

WV3HG128M72AER-AD6

ADVANCED

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

March 2005
Rev. 1

DDR2 I

SPECIFICATIONS AND CONDITIONS

= +1.8V ± 0.1V

Symbol

Proposed Conditions

534

403

Units

CC0

Operating one bank active-precharge current;
t

= t

), t

= t

), t

RAS

= t

RAS

min(I

); CKE is HIGH, CS# is HIGH between valid commands;

Address bus inputs are SWITCHING; Data bus inputs are SWITCHING

2,420

2,250

CC1

Operating one bank active-read-precharge current;
I

OUT

= 0mA; BL = 4, CL = CL(I

), AL = 0; t

= t

), t

= t

), t

RAS

= t

RAS

min(I

), t

RCD

= t

RCD

);

CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is
same as I

D6W

2,640

2,400

CC2P

Precharge power-down current;
All banks idle; t

= t

); CKE is LOW; Other control and address bus inputs are STABLE; Data bus

inputs are FLOATING

784

724

CC2Q

Precharge quiet standby current;
All banks idle; t

= t

); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are STABLE;

Data bus inputs are FLOATING

1,110

1,040

CC2N

Precharge standby current;
All banks idle; t

= t

); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are

SWITCHING; Data bus inputs are SWITCHING

1,090

1,130

CC3P

Active power-down current;
All banks open; t

= t

); CKE is LOW; Other control and address

bus inputs are STABLE; Data bus inputs are FLOATING

Fast PDN Exit MRS(12) = 0

1,190

Slow PDN Exit MRS(12) = 1

600

570

CC3N

Active standby current;
All banks open; t

= t

), t

RAS

= t

RAS

max(I

), t

= t

); CKE is HIGH, CS# is HIGH between valid

commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING

1,840

1,730

DAD6W

Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(I

), AL = 0; t

= t

), t

RAS

= t

RAS

max(I

), t

= t

); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data

bus inputs are SWITCHING

3,820

2,900

DAD6R

Operating burst read current;
All banks open, Continuous burst reads, I

OUT

= 0mA; BL = 4, CL = CL(I

), AL = 0; t

= t

), t

RAS

max(I

), t

= t

); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are

SWITCHING; Data pattern is same as I

D6W

3,590

3,000

CC5B

Burst auto refresh current;
t

= t

); Refresh command at every t

RFC

) interval; CKE is HIGH, CS# is HIGH between valid

commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING

4,150

3,880

CC6

Self refresh current;
CK and CK\ at 0V; CKE 0.2V; Other control and address bus inputs
are FLOATING; Data bus inputs are FLOATING

CC7

Operating bank interleave read current;
All bank interleaving reads, I

OUT

= 0mA; BL = 4, CL = CL(I

), AL = t

D(I

)-1*t

); t

= t

), t

RRD

= t

RRD

), t

RCD

= 1*t

); CKE is HIGH, CS# is HIGH between valid commands; Address

bus inputs are STABLE during DESELECTs; Data pattern is same as I

DAD6R

; Refer to the following page for

detailed timing conditions

5,900

5,570

Note: I

specifi cation is based on SAMSUNG components. Other DRAM Manufacturers specifi cation may be different.

WV3HG128M72AER-AD6

ADVANCED

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

March 2005
Rev. 1

DDR2 I

SPECIFICATIONS AND CONDITIONS

= +1.8V ± 0.1V

Symbol

Proposed Conditions

534

403

Units

CC0

Operating one bank active-precharge current;
t

= t

), t

= t

), t

RAS

= t

RAS

min(I

); CKE is HIGH, CS# is HIGH between valid commands;

Address bus inputs are SWITCHING; Data bus inputs are SWITCHING

2,390

2,120

CC1

Operating one bank active-read-precharge current;
I

OUT

= 0mA; BL = 4, CL = CL(I

), AL = 0; t

= t

), t

= t

), t

RAS

= t

RAS

min(I

), t

RCD

= t

RCD

);

CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is
same as I

D6W

2,660

2,390

CC2P

Precharge power-down current;
All banks idle; t

= t

); CKE is LOW; Other control and address bus inputs are STABLE; Data bus

inputs are FLOATING

680

644

CC2Q

Precharge quiet standby current;
All banks idle; t

= t

); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are STABLE;

Data bus inputs are FLOATING

950

860

CC2N

Precharge standby current;
All banks idle; t

= t

); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are

SWITCHING; Data bus inputs are SWITCHING

1,040

950

CC3P

Active power-down current;
All banks open; t

= t

); CKE is LOW; Other control and address

bus inputs are STABLE; Data bus inputs are FLOATING

Fast PDN Exit MRS(12) = 0

1,220

1,130

Slow PDN Exit MRS(12) = 1

950

860

CC3N

Active standby current;
All banks open; t

= t

), t

RAS

= t

RAS

max(I

), t

= t

); CKE is HIGH, CS# is HIGH between valid

commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING

1,670

1,580

DAD6W

Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(I

), AL = 0; t

= t

), t

RAS

= t

RAS

max(I

), t

= t

); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data

bus inputs are SWITCHING

3,560

3,020

DAD6R

Operating burst read current;
All banks open, Continuous burst reads, I

OUT

= 0mA; BL = 4, CL = CL(I

), AL = 0; t

= t

), t

RAS

max(I

), t

= t

); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are

SWITCHING; Data pattern is same as I

D6W

3,560

3,020

CC5B

Burst auto refresh current;
t

= t

); Refresh command at every t

RFC

) interval; CKE is HIGH, CS# is HIGH between valid

commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING

5,000

4,640

CC6

Self refresh current;
CK and CK\ at 0V; CKE 0.2V; Other control and address bus inputs
are FLOATING; Data bus inputs are FLOATING

108

CC7

Operating bank interleave read current;
All bank interleaving reads, I

OUT

= 0mA; BL = 4, CL = CL(I

), AL = t

D(I

)-1*t

); t

= t

), t

RRD

= t

RRD

), t

RCD

= 1*t

); CKE is HIGH, CS# is HIGH between valid commands; Address

bus inputs are STABLE during DESELECTs; Data pattern is same as I

DAD6R

; Refer to the following page for

detailed timing conditions

5,900

5,540

Note: I

specifi cation is based on ELPIDA components. Other DRAM Manufacturers specifi cation may be different.

WV3HG128M72AER-AD6

ADVANCED

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

March 2005
Rev. 1

AC TIMING PARAMETERS

= +1.8V ± 0.1V

AC CHARACTERISTICS

534

403

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

UNIT

Clock

Clock cycle time

CL = 4

CK (4)

3,750

8,000

5,000

8,000

CL = 3

CK (3)

5,000

8,000

5,000

8,000

CK high-level width

0.45

0.55

0.45

0.55

CK low-level width

0.45

0.55

0.45

0.55

Half clock period

MIN (t

, t

)

MIN (t

, t

)

Clock jitter

-125

125

-125

125

Data

DQ output access time from CK/CK#

-500

+500

-600

+600

Data-out high-impedance window from CK/CK#

MAX

Data-out low-impedance window from CK/CK#

MIN

MAX

MIN

MAX

DQ and DM input setup time relative to DQS

100

150

DQ and DM input hold time relative to DQS

225

275

A DQ and DM input pulse width (for each input)

0.35

Data hold skew factor

QHS

400

450

DQ...DQS hold, DQS to fi rst DQ to go nonvalid, per access

- t

QHS

- t

QHS

Data valid output window (DVW)

DVW

QH -

DQSQ

QH -

DQSQ

Data Strobe

DQS input high pulse width

DQSH

0.35

DQS input low pulse width

DQSL

0.35

DQS output access time from CK/CK#

DQSCK

-450

+450

-500

+500

DQS falling edge to CK rising ... setup time

DSS

0.2

DQS falling edge from CK rising ... hold time

DSH

0.2

DQS...DQ skew, DQS to last DQ valid, per group,
per access

DQSQ

300

350

DQS read preamble

RPRE

0.9

1.1

0.9

1.1

DQS read postamble

RPST

0.4

0.6

0.4

0.6

DQS write preamble setup time

WPRES

DQS write preamble

WPRE

0.35

DQS write postamble

WPST

0.4

0.6

0.4

0.6

Write command to fi rst DQS latching transition

DQSS

WL - 0.25

WL + 0.25

WL - 0.25

WL + 0.25

Continued on next page

WV3HG128M72AER-AD6

ADVANCED

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

March 2005
Rev. 1

AC TIMING PARAMETERS (cont'd)

= +1.8V ± 0.1V

AC CHARACTERISTICS

534

403

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

UNIT

Command and

Address

Address and control input pulse width for each input

0.6

Address and control input setup time

250

350

Address and control input hold time

375

475

CAS# to CAS# command delay

CCD

ACTIVE to ACTIVE (same bank) command

ACTIVE bank a to ACTIVE bank b command

RRD

7.5

ACTIVE to READ or WRITE delay

RCD

Four Bank Activate period

FAW

37.5

ACTIVE to PRECHARGE command

RAS

70,000

Internal READ to precharge command delay

RTP

7.5

6 Write recovery time

Auto precharge write recovery + precharge time

DAL

+ t

Internal WRITE to READ command delay

WTR

7.5

PRECHARGE command period

PRECHARGE ALL command period

RPA

LOAD MODE command cycle time

MRD

OCD Drive mode delay

CKE low to CK,CK# uncertainty

DELAY

+ t

Refresh

REFRESH to REFRESH command interval

RFC

105

70,000

105

70,000

Average periodic refresh interval

REF

7.8

µs

Self Refresh

Exit self refresh to non-READ command

XSNR

RFC

(MIN) + 10

RFC

(MIN) + 10

Exit self refresh to READ command

XSRD

200

Exit self refresh timing reference

SXR

Exit self refresh timing reference

SXR

250

350

ODT

ODT turn-on delay

AOND

ODT turn-on

AON

(MIN)

(MAX) +

1000

(MIN)

(MAX) +

1000

ODT turn-off delay

AOFD

2.5

ODT turn-off

AOF

(MIN)

(MAX) +

600

(MIN)

(MAX) +

600

ODT turn-on (power-down mode)

AONPD

(MIN) +

2000

2 x t

(MAX) +

1000

(MIN) +

2000

2 x t

(MAX) +

1000

ODT turn-off (power-down mode)

AOFPD

(MIN) +

2000

2.5 x t

(MAX) +

1000

(MIN) +

2000

2.5 x t

(MAX) +

1000

ODT to power-down entry latency

ANPD

ODT power-down exit latency

AXPD

Power-Down

Exit active power-down to READ command, MR[bit12=0]

XARD

Exit active power-down to READ command, MR[bit12=1]

XARDS

6 - AL

A Exit precharge power-down to any non-READ command.

CKE minimum high/low time

CKE

WV3HG128M72AER-AD6

ADVANCED

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

March 2005
Rev. 1

PIN 1

18.29 (0.720)

TYP.

5.0 (0.197) TYP.

123.0 (4.843)

TYP.

1.0 (0.039)

TYP.

0.80 (0.032)

TYP.

2.00 (0.079)

(4X)

PIN 120

FRONT VIEW

133.50 (5.256)
133.20 (5.244)

63.0 (2.480)

TYP.

55.0 (2.165)

TYP.

10.00 (0.394)

TYP.

BACK VIEW

PIN 240

PIN 121

1.50 (0.059)

3.00 (0.118)

(4X)

5.175 (0.204)

(2X)

PLL

PACKAGE DIMENSIONS FOR AD6

* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)

ORDERING INFORMATION FOR AD6

Part Number

Speed/Data Rate

CAS Latency

RCD

Height*

WV3HG128M72AER534AD6xxG

266MHz/533Mb/s

18.29mm (0.72")

WV3HG128M72AER403AD6xxG

200MHz/400Mb/s

18.29mm (0.72")

NOTES:

· RoHS products. ("G" = RoHS Compliant)

· Vendor specifi c part numbers are used to provide memory component source control. The place holder for this is shown as a lower case "x"

in the part numbers above and is to be replaced with respective vendors code. Consult factory for qualifi ed sourcing options.
(E = Ellpida, M = Micron, S = Samsung & consult factory for others)

· Consult factory for availability of industrial temperature (-40°C to 85°C) option

WV3HG128M72AER-AD6

ADVANCED

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

March 2005
Rev. 1

Document Title

1GB 128Mx72 DDR2 SDRAM REGISTERED, w/PLL

DRAM DIE OPTIONS:
·

SAMSUNG: C-Die, will move to E-Die Q3'06

MICRON: U27Y: B-Die, will move to U37Y: D-Die Q4"06

ELPIDA: E-Die

Revision History

Rev #

History

Release Date

Status

Rev 0

Created

March 2005

Advanced

Rev 1

1.0

Updated "Absolute Maximum Ratings"

1.1

Added Elpida "CAP" specifi cations

1.2

Added Elpida "I

" specifi cations

1.3

Updated "AC Timing Parameters"

1.4

Added Elpida to part marking info & number guide

1.5

Added "Industrial Temperature" to part numbering guide

1.6

Added DRAM die rev option

April 2006

Advanced

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: WV3HG128M72AER534AD6EG

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: WV3HG128M72AER534AD6EG