1
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
March 2006
Rev. 0
PRELIMINARY*
WV3EG64M64ETSU-D4
White Electronic Designs
512MB 64Mx64 DDR SDRAM, UNBUFFERED, SO-DIMM
FEATURES
Fast data transfer rate: PC3200 & PC2700
Clock speeds of 200MHz & 166MHz
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency : DDR400 (3 clock),
DDR333 (2.5 clock)
Programmable Burst Length (2, 4 or 8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto and self refresh, 7.8s refresh interval (8K
(64ms refresh)
Serial presence detect (SPD) with EEPROM
Serial presence detect with EEPROM
V
CC
= V
CCQ
= +2.5
V
0.2V (166MHz)
V
CC
= V
CCQ
= +2.6V 0.1V (200MHz)
Gold edge contacts
JEDEC standard 200 pin, small-outline, SO-DIMM
package
PCB height option:
D4: 31.75 mm (1.25") TYP
NOTE: Consult factory for availability of:
RoHS compliant products
Vendor source control options
Industrial temperature option
DESCRIPTION
The WV3EG64M64ETSU is a 64Mx64 Double Data Rate
SDRAM memory module based on 512Mb DDR SDRAM
components. The module consists of eight 64Mx8 DDR
SDRAMs TSOP-II packages mounted on a 200 pin FR4
substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system ap pli ca tions.
* This product is under development, is not qualifi ed or characterized and is subject to
change without notice.
OPERATING FREQUENCIES
DDR400@CL=3
DDR333@CL2.5
Clock Speed
200MHz
166MHz
CL-t
RCD
-t
RP
3-3-3
2.5-3-3
WV3EG64M64ETSU-D4
2
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
March 2006
Rev. 0
PRELIMINARY
PIN NAMES
Symbol
Description
A0-A12
Address input
BA0, BA1
Bank Address
DQ0-DQ63
Input/Output: Data I/Os, Data bus
CK0, CK0#
CK1, CK1#
Clock Input
CKE0
Clock Enable Input
CS0#
Chip Select Input
WE#, CAS#, RAS# Command Input
DQS0-DQS7
Data Strobe
DM0-DM7
Data Write Mask
V
CC
Supply: Power Supply
V
CCQ
Power Supply for DQS
V
CCSPD
Supply: Serial EEPROM Positive
Power Supply
V
REF
Supply: SSTL_2 reference voltage
V
SS
Supply: Ground
SCL
Serial Clock
SA0-SA2
Presence Detect Address Input
SDA
Input/Output: Serial Presence-
Detect Data
NC
No Connect
PIN CONFIGURATION
PIN#
SYMBOL
PIN#
SYMBOL
PIN#
SYMBOL
PIN#
SYMBOL
1
V
REF
51
V
SS
101
A9
151
DQ42
2
V
REF
52
V
SS
102
A8
152
DQ46
3
V
SS
53
DQ19
103
V
SS
153
DQ43
4
V
SS
54
DQ23
104
V
SS
154
DQ47
5
DQ0
55
DQ24
105
A7
155
V
CC
6
DQ4
56
DQ28
106
A6
156
V
CC
7
DQ1
57
V
CC
107
A5
157
V
CC
8
DQ5
58
V
CC
108
A4
158
CK1#
9
V
CC
59
DQ25
109
A3
159
V
SS
10
V
CC
60
DQ29
110
A2
160
CK1
11
DQS0
61
DQS3
111
A1
161
V
SS
12
DM0
62
DM3
112
A0
162
V
SS
13
DQ2
63
V
SS
113
V
CC
163
DQ48
14
DQ6
64
V
SS
114
V
CC
164
DQ52
15
V
SS
65
DQ26
115
A10
165
DQ49
16
V
SS
66
DQ30
116
BA1
166
DQ53
17
DQ3
67
DQ27
117
BA0
167
V
CC
18
DQ7
68
DQ31
118
RAS#
168
V
CC
19
DQ8
69
V
CC
119
WE#
169
DQS6
20
DQ12
70
V
CC
120
CAS#
170
DM6
21
V
CC
71
NC
121
CS0#
171
DQ50
22
V
CC
72
NC
122
NC
172
DQ54
23
DQ9
73
NC
123
NC
173
V
SS
24
DQ13
74
NC
124
NC
174
V
SS
25
DQS1
75
V
SS
125
V
SS
175
DQ51
26
DM1
76
V
SS
126
V
SS
176
DQ55
27
V
SS
77
NC
127
DQ32
177
DQ56
28
V
SS
78
NC
128
DQ36
178
DQ60
29
DQ10
79
NC
129
DQ33
179
V
CC
30
DQ14
80
NC
130
DQ37
180
V
CC
31
DQ11
81
V
CC
131
V
CC
181
DQ57
32
DQ15
82
V
CC
132
V
CC
182
DQ61
33
V
CC
83
NC
133
DQS4
183
DQS7
34
V
CC
84
NC
134
DM4
184
DM7
35
CK0
85
NC
135
DQ34
185
V
SS
36
V
CC
86
NC
136
DQ38
186
V
SS
37
CK0#
87
V
SS
137
V
SS
187
DQ58
38
V
SS
88
V
SS
138
V
SS
188
DQ62
39
V
SS
89
NC
139
DQ35
189
DQ59
40
V
SS
90
V
SS
140
DQ39
190
DQ63
41
DQ16
91
NC
141
DQ40
191
V
CC
42
DQ20
92
V
CC
142
DQ44
192
V
CC
43
DQ17
93
V
CC
143
V
CC
193
SDA
44
DQ21
94
V
CC
144
V
CC
194
SA0
45
V
CC
95
NC
145
DQ41
195
SCL
46
V
CC
96
CKE0
146
DQ45
196
SA1
47
DQS2
97
NC
147
DQS5
197
V
CCSPD
48
DM2
98
NC
148
DM5
198
SA2
49
DQ18
99
A12
149
V
SS
199
NC
50
DQ22
100
A11
150
V
SS
200
NC
WV3EG64M64ETSU-D4
3
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
March 2006
Rev. 0
PRELIMINARY
FUNCTIONAL BLOCK DIAGRAM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS
S0#
A0 - A12
A0 - A12: DDR SDRAMs
RAS#
RAS#: DDR SDRAMs
CAS#
CAS#: DDR SDRAMs
WE#
WE#: DDR SDRAMs
A0
Serial PD
A1
A2
SA0
SA1
SA2
SCL
SDA
SP
DM
DQS0
DM0
S0#
DQS4
DM4
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
S0#
DQS1
DM1
S0#
DQS5
DM5
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
S0#
DQS2
DM2
S0#
DQS6
DM6
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
S0#
DQS3
DM3
S0#
DQS7
DM7
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ64
CS0#
CK0
CK0#
DDR SDRAM x 4
DDR SDRAM x 4
120 Ohms
CKE0: DDR SDRAMs
CKE0
BA0 - BA1: DDR SDRAMs
BA0 - BA1
CK1
CK1#
120 Ohms
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DM
V
REF
V
SS
DDR SDRAMs
DDR SDRAMs
V
CCSPD
V
CC/
V
CCQ
DDR SDRAMs
SPD
Note: 1. All resistor values are 22 unless otherwise specifi ed.
WV3EG64M64ETSU-D4
4
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
March 2006
Rev. 0
PRELIMINARY
DC OPERATING CONDITIONS
T
A
= 0C to 70C
Parameter/Condition
Symbol
Min
Max
Units
Notes
Supply Voltage DDR400 (nominal VCC 2.6)
V
CC
2.5
2.7
V
I/O Supply Voltage DDR400 (nominal VCC 2.6)
V
CCQ
2.5
2.7
V
Supply Voltage DDR333
V
CC
2.3
2.7
V
I/O Supply Voltage DDR333
V
CCQ
2.3
2.7
V
I/O Reference Voltage
V
REF
0.49 V
CCQ
0.51 V
CCQ
V
1
I/O Termination Voltage (system)
V
TT
V
REF
- 0.04
V
REF
+ 0.04
V
2
Input High (Logic 1) Voltage
V
IH(DC)
V
REF
+ 0.15
V
CC
+ 0.30
V
Input Low (Logic 0) Voltage
V
IL(DC)
-0.3
V
REF
- 0.15
V
Input voltage level, CK and CK#
V
IN(DC)
-0.3
V
CCQ
+ 0.30
V
Input differential voltage, CK and CK#
V
ID(DC)
-0.3
V
CCQ
+ 0.60
V
3
Input crossing point voltage, CK and CK#
V
IX(DC)
-0.3
V
CCQ
+ 0.60
V
Input leakage current
Addr, CAS#,
RAS#, WE#
I
I
-16
16
A
CS#, CKE
-16
16
A
CK, CK#
-8
8
A
DM
-2
2
A
Output leakage current
I
OZ
-5
5
A
Output high current (normal strength)
V
OUT
= v + 0.84V
I
OH
-16.8
--
mA
Output high current (normal strength)
V
OUT
= v - 0.84V
I
OL
-16.8
--
mA
Output high current (half strength)
V
OUT
= V
TT
+ 0.45V
V
OH
-9
--
mA
Output high current (half strength)
V
OUT
= V
TT
- 0.45V
V
OL
9
--
mA
Notes:
1. V
REF
is expected to be equal to 0.5*V
CCQ
of the transmitting device, and to track variations in the DC level of the same. Peak to peak noise on V
REF
may not exceed +/-2% of the DC
values.
2. V
TT
is not applied directly to the device. V
TT
is a system supply for signal termination resistors, is expected to be set equal to V
REF
, and must track variations in the DC level of V
REF
.
3. V
ID
is the magnitude of the difference between the input level on CK and the input level of CK#.
4. Industrial grade modules are specifi ed to a DRAM t
CASE
of 85C and -40C
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Units
Voltage on any in relative to V
SS
V
IN
, V
OUT
-0.5 ~ 3.6
V
Voltage on V
CC
& V
CCQ
supply relative to V
SS
V
CC
, V
CCQ
-1.0 ~ 3.6
V
Voltage on V
REF
supply relative to V
SS
V
REF
-1.0 ~ 3.6
V
Storage temperature
T
STG
-55 ~ +150
C
Operating temperature
T
A
0 ~ 70
C
Power dissipation
P
D
8
W
Short circuit output current
I
OS
50
mA
Notes:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceed.
Functional operation should be restricted to recommended operating condition.
Exposing to higher than recommended voltage for extended periods of time could affect device reliability.
WV3EG64M64ETSU-D4
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
March 2006
Rev. 0
PRELIMINARY
INPUT/OUTPUT CAPACITANCE
T
A
= 25C, f = 100MHz
Parameter
Symbol
Min
Max
Units
Input capacitance (A0 ~ A12, BA0 ~ BA1, RAS#, CAS# WE#)
C
IN1
20
28
pF
Input capacitance (CKE0)
C
IN2
20
28
pF
Input capacitance (CS0#)
C
IN3
20
28
pF
Input capacitance (CK0, CK0#, CK1, CK1#)
C
IN4
12
16
pF
Input capacitance (DM0 ~ DM7)
C
IN5
8
9
pF
Input capacitance (DQ0 ~ DQ63), (DQS0 ~ DQS7)
C
OUT1
8
9
pF
Notes:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceed.
Functional operation should be restricted to recommended operating condition.
Exposing to higher than recommended voltage for extended periods of time could affect device reliability.
AC OPERATING CONDITIONS
Parameter
Symbol
Min
Max
Units
Input High (Logic 1) Voltage
V
IH(AC)
V
REF
+ 0.31
V
Input Low (Logic 0) Voltage
V
IL(AC)
V
REF
- 0.31
V
Input Differential Voltage, CK and CK# inputs
V
ID(AC)
0.7
V
CCQ
+ 0.6
V
Input crossing point voltage, CK and CK# input
V
IX(AC)
0.5*V
CCQ
- 0.2
0.5*V
CCQ
+ 0.2
V
WV3EG64M64ETSU-D4
6
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
March 2006
Rev. 0
PRELIMINARY
I
CC
SPECIFICATIONS AND CONDITIONS
0C T
A
+70C DDR400: V
CC
= V
CCQ
= +2.6V 0.1V
Symbol
Parameter/Condition
Max
Max
Units
DDR400
@CL=3
DDR333
@CL=2.5
I
CC0
OPERATING CURRENT: One device bank; Active-Precharge; t
RC
= t
RC
(MIN); t
CK
= t
CK
(MIN);
DQ, DM and DQS inputs changing once per clock cycle; Address and control inputs changing
once every two clock cycles
960
840
mA
I
CC1
OPERATING CURRENT: One device bank; Active-Read-Precharge; Burst = 4; t
RC
= t
RC
(MIN);
t
CK
= t
CK
(MIN); I
OUT
= 0mA; Address and control inputs changing once per clock cycle
1,200
1,080
mA
I
CC2P
PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle; Power-down
mode; t
CK
= t
CK
(MIN); CKE = (LOW)
40
40
mA
I
CC2F
IDLE STANDBY CURRENT: CS# = HIGH; All device banks are idle; t
CK
= t
CK
(MIN); CKE =
HIGH; Address and other control inputs changing once per clock cycle. V
IN
= V
REF
for DQ, DQS,
and DM
240
240
mA
I
CC3P
ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; Power-down mode;
t
CK
= t
CK
(MIN); CKE = LOW
360
200
mA
I
CC3N
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank active; t
RC
= t
RAS
(MAX); t
CK
= t
CK
(MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and
other control inputs changing once per clock cycle
480
360
mA
I
CC4R
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One device bank active; Address
and control inputs changing once per clock cycle; t
CK
= t
CK
(MIN); I
OUT
= 0mA
1,240
1,120
mA
I
CC4W
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank active; Address
and control inputs changing once per clock cycle; t
CK
= t
CK
(MIN); DQ, DM, and DQS inputs
changing twice per clock cycle
1,400
1,200
mA
I
CC5
AUTO REFRESH BURST CURRENT:
t
REFC
= t
RFC
(MIN)
1,760
1,640
mA
I
CC6
SELF REFRESH CURRENT: CKE 0.2V
40
40
mA
I
CC7
OPERATING CURRENT: Four device bank interleaving READs (Burst = 4) with auto precharge,
t
RC
= minimum t
RC
allowed; t
CK
= t
CK
(MIN); Address and control inputs change only during
Active READ, or WRITE commands
3,080
2,880
mA
Notes:
I
CC
parameters are based on SAMSUNG components. Other DRAM manufactures parameter may be different
WV3EG64M64ETSU-D4
7
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
March 2006
Rev. 0
PRELIMINARY
I
CC
SPECIFICATIONS AND CONDITIONS
0C T
A
+70C, DDR400: V
CC
= V
CCQ
= +2.6V 0.1V
Symbol
Parameter/Condition
Max
Max
Units
DDR400
@CL=3
DDR333
@CL=2.5
I
CC0
OPERATING CURRENT: One device bank; Active-Precharge; t
RC
= t
RC
(MIN); t
CK
= t
CK
(MIN);
DQ, DM and DQS inputs changing once per clock cycle; Address and control inputs changing
once every two clock cycles
TBD
1,040
mA
I
CC1
OPERATING CURRENT: One device bank; Active-Read-Precharge; Burst = 4; t
RC
= t
RC
(MIN);
t
CK
= t
CK
(MIN); I
OUT
= 0mA; Address and control inputs changing once per clock cycle
TBD
1,280
mA
I
CC2P
PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle; Power-down
mode; t
CK
= t
CK
(MIN); CKE = (LOW)
TBD
40
mA
I
CC2F
IDLE STANDBY CURRENT: CS# = HIGH; All device banks are idle; t
CK
= t
CK
(MIN); CKE =
HIGH; Address and other control inputs changing once per clock cycle. V
IN
= V
REF
for DQ, DQS,
and DM
TBD
360
mA
I
CC3P
ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; Power-down mode;
t
CK
= t
CK
(MIN); CKE = LOW
TBD
280
mA
I
CC3N
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank active; t
RC
= t
RAS
(MAX); t
CK
= t
CK
(MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and
other control inputs changing once per clock cycle
TBD
400
mA
I
CC4R
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One device bank active; Address
and control inputs changing once per clock cycle; t
CK
= t
CK
(MIN); I
OUT
= 0mA
TBD
1,320
mA
I
CC4W
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank active; Address
and control inputs changing once per clock cycle; t
CK
= t
CK
(MIN); DQ, DM, and DQS inputs
changing twice per clock cycle
TBD
1,400
mA
I
CC5
AUTO REFRESH BURST CURRENT:
t
REFC
= t
RFC
(MIN)
TBD
2,320
mA
I
CC6
SELF REFRESH CURRENT: CKE 0.2V
TBD
40
mA
I
CC7
OPERATING CURRENT: Four device bank interleaving READs (Burst = 4) with auto precharge,
t
RC
= minimum t
RC
allowed; t
CK
= t
CK
(MIN); Address and control inputs change only during
Active READ, or WRITE commands
TBD
3,240
mA
Notes:
I
CC
parameters are based on MICRON components. Other DRAM manufactures parameter may be different
WV3EG64M64ETSU-D4
8
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
March 2006
Rev. 0
PRELIMINARY
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC
OPERATING CONDITIONS
0C T
A
+70C;
AC Characteristics
403
335
Units
Parameter
Symbol
Min
Max
Min
Max
Row Cycle Time
t
RC
55
60
t
CK
Refresh row cycle time
t
RFC
70
72
ps
Row active
t
RAS
40
70K
42
70K
ps
RAS# to CAS# delay
t
RCD
15
18
t
CK
Row percharge time
t
RP
15
18
ns
Row active to row active delay
t
RRD
10
12
ns
Write recovery time
t
WR
15
15
ns
Last data in to READ command
t
WTR
2
1
ns
Clock cycle time
CL = 2.5
t
CK
6
12
6
12
ns
CL = 3
5
10
ns
CK high-level width
t
CH
0.45
0.55
0.45
0.55
t
CK
CK low-level width
t
CL
0.45
0.55
0.45
0.55
t
CK
Access window of DQS from CK/CK#
t
DQSCK
-0.55
+0.55
-0.6
+0.6
ns
Access window of DQs from CK/CK#
t
AC
-0.65
+0.65
-0.7
+0.7
ns
DQS-DQ skew, DQS to last DQ valid, per group, per
access
t
DQSQ
-
0.4
-
0.4
ns
Read preamble
t
RPRE
0.9
1.1
0.9
1.1
t
CK
Read postamble
t
RPST
0.4
0.6
0.4
0.6
t
CK
CK to valid DQS-in
t
DQSS
0.72
1.28
0.75
1.25
t
CK
DQS-in setup time
t
WPRES
0
0
ns
DQS-in hold time
t
WPRE
0.25
0.25
t
CK
DQS falling edge to CK rising-setup time
t
DSS
0.2
0.2
t
CK
DQS falling edge to CK rising-hold time
t
DSH
0.2
0.2
t
CK
Notes:
Industrial grade modules are specifi ed to a DRAM t
CASE
of 85C and -40C
Continued on next page
WV3EG64M64ETSU-D4
9
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
March 2006
Rev. 0
PRELIMINARY
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC
OPERATING CONDITIONS
0C T
A
+70C
AC Characteristics
403
335
Units
Parameter Symbol
Min
Max
Min
Max
DQS-in high level width
t
DQSH
0.35
0.35
t
CK
DQS-in low level width
t
DQSL
0.35
0.35
t
CK
Address and control input setup time (fast)
t
ISF
0.6
0.75
ns
Address and control input hold time (fast)
t
IHF
0.6
0.75
ns
Address and control input setup time (slow)
t
ISs
0.7
0.8
ns
Address and control input hold time (slow)
t
IHS
0.7
0.8
ns
Data-out high-impedance time from CK/CK#
t
HZ
+0.65
+0.70
ns
Data-out low-impedance time from CK/CK#
t
LZ
-0.65
-0.70
ns
Mode register set cycle
t
MRD
10
12
ns
DQ and DM input setup time to DQS
t
DS
0.4
0.45
ns
DQ and DM input hold time to DQS
t
DH
0.4
0.45
ns
Control & address input pulse width
t
IPW
2.2
2.2
ns
DQ & DM input pulse width
t
DIPW
1.75
1.75
ns
Exit self refresh to non-Read command
t
XSNR
75
75
ns
Exit self refresh to Read command
t
XSRD
200
200
t
CK
Refresh interval time
t
REFI
7.8
7.8
s
Output DQS valid window
t
QH
t
HP -
t
QHS
t
HP -
t
QHS
ns
Clock Half period
t
HP
t
CL(MIN) or
t
CH(MAX)
t
CL(MIN) or
t
CH(MAX)
ns
Data hold skew factor
t
QHS
0.5
0.5
ns
DQS write postable
t
WPST
0.4
0.6
0.4
0.6
ns
Active read with auto precharge command
t
RAP
15
18
ns
Auto precharge write recovery + precharge time
t
DAL
t
WR/
t
CK
+
t
RP/
t
CK
t
WR/
t
CK
+
t
RP/
t
CK
t
CK
Notes:
Industrial grade modules are specifi ed to a DRAM t
CASE
of 85C and -40C
WV3EG64M64ETSU-D4
10
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
March 2006
Rev. 0
PRELIMINARY
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
200-PIN DDR2 SO-DIMM DIMENSIONS
ORDERING INFORMATION FOR D4
Part Number
Speed
CAS Latency
t
RCD
t
RP
Height*
WV3EG64M64ETSU403D4xxG
200MHz/400Mbps
3
3
3
31.75 (1.25") TYP
WV3EG64M64ETSU335D4xxG
166MHz/333Mbps
2.5
3
3
31.75 (1.25") TYP
NOTES:
Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant)
Vendor specifi c part numbers are used to provide memory components source control. The place holder for this is shown as lower case "-x" in the part numbers above and is to
be replaced with the respective vendors code. Consult factory for qualifi ed sourcing options. (M = Micron, S = Samsung & consult factory for others)
Consult factory for availability of industrial temperature (-40C to 85C) option
3.80 (0.150)
MAX
1.10 (0.043)
0.90 (0.035)
PIN 1
67.75 (2.667)
67.45 (2.656)
20.00 (0.787)
TYP
1.80 (0.071)
(2X)
0.60 (0.024)
TYP
0.45 (0.018)
TYP
4.10 (0.161)(2X)
PIN 199
PIN 200
PIN 2
2.15 (0.085)
6.000 (.236)
2.504 (63.60)
2.55 (0.100)
1.00 (0.039)
TYP
TYP
BACK VIEW
FRONT VIEW
31.90 (1.256)
31.60 (1.244)
1.866 (47.40)
TYP
0.449 (11.40)
TYP
0.165 (4.2)
TYP
3.90( 0.154)
WV3EG64M64ETSU-D4
11
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
March 2006
Rev. 0
PRELIMINARY
PART NUMBERING GUIDE
W 3 E G 64M 64 E T S U xxx D4 x x G
WEDC
MEMORY (SDRAM)
DDR
GOLD
DEPTH)
BUS WIDTH
x8
TSOP
(400M/bs = V
CC
/V
CCQ
= +2.6V 0.1V)
2.5V
UNBUFFERED
SPEED (Mbs)
PACKAGE 200 PIN
TEMPERATURE RANGE
(Blank = 0C - 70C ambient)
(I = -40C to 85C DRAM case temp)
COMPONENT VENDOR NAME
(M = MICRON)
(S = SAMSUNG)
G = RoHS COMPLIANT
WV3EG64M64ETSU-D4
12
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
March 2006
Rev. 0
PRELIMINARY
Document Title
512MB - 64Mx64 DDR SDRAM, UNBUFFERED SO-DIMM
Revision History
Rev #
History
Release Date
Status
Rev 0
Created
3-06
Preliminary
PDF 
ZIP