White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

March 2005
Rev. 0

ADVANCED*

WV3EG128M72EFSR-D3

1GB 128Mx72 DDR SDRAM REGISTERED w/PLL, FBGA

DESCRIPTION

The WV3EG128M72EFSR is a 128Mx72 Double Data
Rate SDRAM memory module based on 512Mb DDR
SDRAM component. The module consists of eighteen
64Mx8 DDR components in FBGA packages mounted on
a 184 Pin FR4 substrate.

Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lenths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.

* This product is under development, is not qualifi ed or characterized and is subject to

change or cancellation without notice.

FEATURES

Double-data-rate architecture
DDR266 and DDR333

· JEDEC design specifi cations

Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2,5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto and self refresh
Serial presence detect
Power Supply:

· V

= V

CCQ

= +2.5V ±0.2V (100, 133 and

166MHz)

184 pin DIMM package
PCB

height:

· D3: 29.97mm (1.18")

NOTE: Consult factory for availability of:

Lead-Free

Products

· Vendor source control options
· Industrial temperature options

OPERATING FREQUENCIES

DDR333 @CL=2.5

DDR266 @CL=2

DDR266 @CL=2.5

Clock Speed

166MHz

133MHz

CL-t

RCD

-t

2.5-3-3

2-2-2

2.5-3-3

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White Electronic Designs

March 2005
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ADVANCED

WV3EG128M72EFSR-D3

PIN CONFIGURATION

PIN

SYMBOL

PIN

SYMBOL

PIN

SYMBOL

PIN

SYMBOL

REF

DQS8

139

DQ0

DQ4

140

DM8/DQS17

CB2

DQ5

141

A10

DQ1

CCQ

142

CB6

DQS0

CB3

DM0/DQS9

143

CCQ

DQ2

BA1

DQ6

144

CB7

DQ32

DQ7

145

DQ3

CCQ

100

146

DQ36

DQ33

101

147

DQ37

RESET#

DQS4

102

148

DQ34

103

149

DM4/DQS13

DQ8

104

CCQ

150

DQ38

DQ9

BA0

105

DQ12

151

DQ39

DQS1

DQ35

106

DQ13

152

CCQ

DQ40

107

DM1/DQS10

153

DQ44

CCQ

108

154

RAS#

WE#

109

DQ14

155

DQ45

DQ41

110

DQ15

156

CCQ

DQ10

CAS#

111

CKE1

157

CS0#

DQ11

112

CCQ

158

CS1#

CKE0

DQS5

113

159

DM5/DQS14

CCQ

DQ42

114

DQ20

160

DQ16

DQ43

115

A12

161

DQ46

DQ17

116

162

DQ47

DQS2

117

DQ21

163

DQ48

118

A11

164

CCQ

DQ49

119

DM2/DQS11

165

DQ52

DQ18

120

166

DQ53

121

DQ22

167

CCQ

122

168

DQ19

CCQ

123

DQ23

169

DM6/DQS15

DQS6

124

170

DQ54

DQ24

DQ50

125

171

DQ55

DQ51

126

DQ28

172

CCQ

DQ25

127

DQ29

173

DQS3

CCID

128

CCQ

174

DQ60

DQ56

129

DM3/DQS12

175

DQ61

DQ57

130

176

DQ26

131

DQ30

177

DM7/DQS16

DQ27

DQS7

132

178

DQ62

DQ58

133

DQ31

179

DQ63

DQ59

134

CB4

180

CCQ

135

CB5

181

SA0

CB0

136

CCQ

182

SA1

CB1

SDA

137

CK0

183

SA2

SCL

138

CK0#

184

CCSPD

PIN NAMES

A0-A12

Address input (Multiplexed)

BA0-BA1

Bank Select Address

DQ0-DQ63

Data Input/Output

CB0-CB7

Check bits

DQS0-DQS8

Data Strobe Input/Output

CK0

Clock Input

CK0#

Clock Input

CKE0, CKE1

Clock Enable input

CS0#, CS1#

Chip Select Input

RAS#

Row Address Strobe

CAS#

Column Address Strobe

DM0-DM8

Data-in Mask

WE#

Write Enable

Power Supply

CCQ

Power Supply for DQS

Ground

REF

Power Supply for Reference

CCSPD

Serial EEPROM Power Supply

SDA

Serial data I/O

SCL

Serial clock

SA0-SA2

Address in EEPROM

CCID

Indentifi cation Flag

No Connect

RESET#

Reset Enable

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WV3EG128M72EFSR-D3

DM0/DQS9

DM1/DQS10

DQ20
DQ21

DQ22
DQ23

DQ16

DQ17
DQ18
DQ19

DM2/DQS11

DQ28
DQ29

DQ30
DQ31

DQ24

DQ25
DQ26
DQ27

DM3/DQS12

DQ36
DQ37

DQ38
DQ39

DQ32

DQ33
DQ34
DQ35

DM5/DQS14

DQ44
DQ45

DQ46
DQ47

DQ40

DQ41
DQ42
DQ43

DM6/DQS15

DQ52
DQ53

DQ54
DQ55

DQ48

DQ49
DQ50

DQ51

DQ60
DQ61
DQ62

DQ63

DQ56
DQ57

DQ58
DQ59

DM7/DQS17

RCS0#

RCS1#

DQS0

DQS5

DQS1

DQS6

DQS2

DQS3

DM6/DQS16

DQS7

DQS8

CB4

CB5
CB6
CB7

CB0
CB1
CB2

CB3

DQS4

DM4/DQS13

PCK

RAS#
CAS#
CKE0
CKE1

RCS1#

CS1#

BA0-BA1

A0-A12

CS0#

RCS0#

PCK#

RESET#

RBA0-RBA1
RA0-RA12
RRAS#
RCAS#
RCKE0

RWE#

RCKE1

WE#

BA0-BA1: SDRAMs
A0-A12: SDRAMs
RAS#: SDRAMs
CAS#: SDRAMs
CKE: SDRAMs
CKE: SDRAMs
WE#: DQRAMs

SA0

SERIAL PD

SDA

SA1

SA2

REF

DDR SDRAMS

PLL

DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
REGISTER X 2

SCL

CCQ

DDR SDRAMS

CK0

CK0#

120

SPD

CCSPD

DQ4
DQ5
DQ6

DQ7

DQ0
DQ1

DQ2
DQ3

I/O7
I/O6

I/O1
I/O0

I/O5
I/O4

I/O3
I/O2

I/O0
I/O1
I/O6

I/O7
I/O2
I/O3
I/O4

I/O5

CS#

DQS

DQ12
DQ13
DQ14

DQ8
DQ9

DQ10

DQ11

DQ15

I/O7
I/O6

I/O1
I/O0

I/O5
I/O4

I/O3
I/O2

I/O0
I/O1
I/O6

I/O7
I/O2
I/O3
I/O4

I/O5

CS#

DQS

I/O7
I/O6

I/O1
I/O0

I/O5
I/O4

I/O3
I/O2

I/O0
I/O1
I/O6

I/O7
I/O2
I/O3
I/O4

I/O5

CS#

DQS

I/O7
I/O6

I/O1
I/O0

I/O5
I/O4

I/O3
I/O2

I/O0
I/O1
I/O6

I/O7
I/O2
I/O3
I/O4

I/O5

CS#

DQS

I/O7
I/O6

I/O1
I/O0

I/O5
I/O4

I/O3
I/O2

I/O0
I/O1
I/O6

I/O7
I/O2
I/O3
I/O4

I/O5

CS#

DQS

I/O7
I/O6

I/O1
I/O0

I/O5
I/O4

I/O3
I/O2

I/O0
I/O1
I/O6

I/O7
I/O2
I/O3
I/O4

I/O5

CS#

DQS

I/O7
I/O6

I/O1
I/O0

I/O5
I/O4

I/O3
I/O2

I/O0
I/O1
I/O6

I/O7
I/O2
I/O3
I/O4

I/O5

CS#

DQS

I/O7
I/O6

I/O1
I/O0

I/O5
I/O4

I/O3
I/O2

I/O0
I/O1
I/O6

I/O7
I/O2
I/O3
I/O4

I/O5

CS#

DQS

I/O7
I/O6

I/O1
I/O0

I/O5
I/O4

I/O3
I/O2

I/O0
I/O1
I/O6

I/O7
I/O2
I/O3
I/O4

I/O5

CS#

DQS

FUNCTIONAL BLOCK DIAGRAM

Note: All resistor values are 22 unless otherwise indicated.

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March 2005
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ADVANCED

WV3EG128M72EFSR-D3

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Value

Units

Voltage on any pin relative to V

, V

OUT

-0.5 to 3.6

Voltage on V

supply relative to V

, V

CCQ

-1.0 to 3.6

Storage Temperature

STG

-55 to +150

°C

Power Dissipation

Short Circuit Current

Note:

Permanent device damage may occur if `ABSOLUTE MAXIMUM RATINGS' are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability

DC CHARACTERISTICS

0°C

70°C, V

= 2.5V ± 0.2V

Parameter

Symbol

Min

Max

Unit

Supply Voltage (for device with nominal V

of 2.5V)

2.3

I/O Supply Voltage

CCQ

2.3

I/O Reference Voltage

REF

CCQ

/2-50mV

CCQ

/2+50mV

I/O Termination Voltage (systems)

REF

-0.04

REF

+0.04

Input Logic High Voltage

(DC)

REF

+0.15

CCQ

+0.3

Input Logic Low Voltage

(DC)

-0.3

REF

-0.15

Input Voltage Level, CK and CK# inputs

(DC)

-0.3

CCQ

+0.3

Input Differential Voltage, CK and CK# inputs

(DC)

0.3

CCQ

+0.6

Input Crossing Point Voltage, CK and CK# inputs

(DC)

1.15

1.35

Input Leakage Current

-2

Output Leakage Current

-5

Output High Current (Normal strength driver); V

OUT

= V

+ 0.84V

-16.8

Output High Current (Normal strength driver); V

OUT

= V

- 0.84V

16.8

Output High Current (Half strength driver); V

OUT

= V

+ 0.45V

-9

Output High Current (Half strength driver); V

OUT

= V

- 0.45V

CAPACITANCE

= 25°C. f = 1MHz, V

= 2.5V

Parameter

Symbol

Max

Unit

Input Capacitance (A0-A12)

IN1

Input Capacitance (RAS#, CAS#, WE#)

IN2

Input Capacitance (CKE0, CKE1)

IN3

Input Capacitance (CK0#, CK0)

IN4

Input Capacitance (CS0#, CS1#)

IN5

Input Capacitance (DQM0-DQM8)

IN6

Input Capacitance (BA0-BA1)

IN7

Data input/output capacitance (DQ0-DQ63)(DQS)

OUT

Data input/output capacitance (CB0-CB7)

OUT

Notes:
1.

Includes ± 25mV margin for DC offset on V

REF

, and a combined total of ± 50mV

margin for all AC noise and DC offset on V

REF

, bandwidth limited to 20MHz. The

DRAM must accommodate DRAM current spikes on V

REF

and internal DRAM

noise coupled TO V

REF

, both of which may result in V

REF

noise. V

REF

should be

de-coupled with an inductance of 3nH.

2. V

is not applied directly to the device. V

is a system supply for signal

termination resistors, is expected to be set equal to V

REF

, and must track variations

in the DC level of V

REF

3. V

is the magnitude of the difference between the input level on CK and the input

level on CK#.

These parameters should be tested at the pin on actual components and may
be checked at either the pin or the pad in simulation. The AC and DC input
specifi cations are relative to a V

REF

envelop that has been bandwidth limited to

200MHZ.

The value of V

is expected to equal 0.5*V

CCQ

of the transmitting device and must

track variations in the dc level of the same.

These charactericteristics obey the SSTL-2 class II standards.

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White Electronic Designs

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ADVANCED

WV3EG128M72EFSR-D3

SPECIFICATIONS AND TEST CONDITIONS

Recommended operating conditions, 0°C

70°C, V

CCQ

= 2.5V ± 0.2V, V

= 2.5V ± 0.2V

Includes DDR SDRAM component only

Parameter

Symbol

Conditions

DDR333@

CL=2.5

Max

DDR266@

CL=2

Max

DDR266@

CL=2.5

Max

Units

Operating Current

DD0

One device bank; Active - Precharge; t

(MIN);

(MIN); DQ,DM and DQS inputs changing once

per clock cycle; Address and control inputs changing
once every two cycles.

4140

Operating Current

DD1

One device bank; Active-Read-Precharge Burst = 2;
t

(MIN); t

(MIN); l

OUT

= 0mA; Address and

control inputs changing once per clock cycle.

4680

Precharge Power-
Down Standby Current

DD2P

All device banks idle; Power-down mode; t

(MIN);

CKE=(low)

180

rnA

Idle Standby Current

DD2F

CS# = High; All device banks idle; t

(MIN); CKE

= high; Address and other control inputs changing once
per clock cycle. V

= V

REF

for DQ, DQS and DM.

1620

Active Power-Down
Standby Current

DD3P

One device bank active; Power-Down mode; t

(MIN);

CKE=(low)

1260

Active Standby Current

DD3N

CS# = High; CKE = High; One device bank; Active-
Precharge; t

RAS

(MAX); t

(MIN); DQ, DM and

DQS inputs changing twice per clock cycle; Address
and other control inputs changing once per clock cycle.

1800

Operating Current

DD4R

Burst = 2; Reads; Continuous burst; One device bank
active; Address and control inputs changing once per
clock cycle; T

= T

(MIN); l

OUT

= 0mA.

4770

Operating Current

DD4W

Burst = 2; Writes; Continuous burst; One device bank
active; Address and control inputs changing once per
clock cycle; t

(MIN); DQ,DM and DQS inputs

changing once per clock cycle.

4590

rnA

Auto Refresh Current

DD5

= t

(MIN)

7020

Self Refresh Current

DD6

CKE

0.2V

180

Operating Current

DD7A

Four bank interleaving Reads (BL=4) with auto
precharge with t

(MIN); t

(MIN); Address

and control inputs change only during Active Read or
Write commands.

9090

9000

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White Electronic Designs

March 2005
Rev. 0

ADVANCED

WV3EG128M72EFSR-D3

SPECIFICATIONS AND TEST CONDITIONS

Recommended operating conditions, 0°C

70°C, V

CCQ

= 2.5V ± 0.2V, V

= 2.5V ± 0.2V

Includes PLL and register power

Parameter

Symbol

Conditions

DDR333@

CL=2.5

Max

DDR266@

CL=2

Max

DDR266@

CL=2.5

Max

Units

Operating Current

DD0

One device bank; Active - Precharge; t

(MIN);

(MIN); DQ,DM and DQS inputs changing once

per clock cycle; Address and control inputs changing
once every two cycles.

4725

Operating Current

DD1

One device bank; Active-Read-Precharge Burst = 2;
t

(MIN); t

(MIN); l

OUT

= 0mA; Address and

control inputs changing once per clock cycle.

5265

Precharge Power-
Down Standby Current

DD2P

All device banks idle; Power-down mode; t

(MIN);

CKE=(low)

180

rnA

Idle Standby Current

DD2F

CS# = High; All device banks idle; t

(MIN); CKE

= high; Address and other control inputs changing once
per clock cycle. V

= V

REF

for DQ, DQS and DM.

1930

Active Power-Down
Standby Current

DD3P

One device bank active; Power-Down mode; t

(MIN);

CKE=(low)

1260

Active Standby Current

DD3N

CS# = High; CKE = High; One device bank; Active-
Precharge; t

RAS

(MAX); t

(MIN); DQ, DM and

DQS inputs changing twice per clock cycle; Address
and other control inputs changing once per clock cycle.

2110

Operating Current

DD4R

Burst = 2; Reads; Continuous burst; One device bank
active; Address and control inputs changing once per
clock cycle; T

= T

(MIN); l

OUT

= 0mA.

5355

Operating Current

DD4W

Burst = 2; Writes; Continuous burst; One device bank
active; Address and control inputs changing once per
clock cycle; t

(MIN); DQ,DM and DQS inputs

changing once per clock cycle.

5535

5175

rnA

Auto Refresh Current

DD5

= t

(MIN)

7640

7605

Self Refresh Current

DD6

CKE

0.2V

455

Operating Current

DD7A

Four bank interleaving Reads (BL=4) with auto
precharge with t

(MIN); t

(MIN); Address

and control inputs change only during Active Read or
Write commands.

9675

9585

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ADVANCED

WV3EG128M72EFSR-D3

DD1

: OPERATING CURRENT : ONE BANK

1. Typical Case : V

=2.5V, T=25°C

2. Worst Case : V

=2.7V, T=10°C

3. Only one bank is accessed with t

(min), Burst

Mode, Address and Control inputs on NOP edge
are changing once per clock cycle. I

OUT

= 0mA

4. Timing

Patterns

DDR200 (100 MHz, CL=2) : t

CK=

10ns, CL2,

BL=4, t

RCD=

2*t

, t

RAS=

5*t

Read : A0 N R0 N N P0 N A0 N - repeat the
same timing with random address changing;
50% of data changing at every burst

DDR266 (133MHz, CL=2.5) : t

CK=

7.5ns,

CL=2.5, BL=4, t

RCD=

3*t

, t

RC=

9*t

, t

RAS=

5*t

Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst

DDR266 (133MHz, CL=2) : t

=7.5ns, CL=2,

BL=4, t

RCD

=3*t

, t

=9*t

, t

RAS

=5*t

Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst

DDR333 (166MHz, CL=2.5) : t

=6ns, BL=4,

RCD

=10*t

, t

RAS

=7*t

Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst

DD7A

: OPERATING CURRENT : FOUR BANKS

1. Typical Case : V

=2.5V, T=25°C

2. Worst Case : V

=2.7V, T=10°C

3. Four banks are being interleaved with t

(min),

Burst Mode, Address and Control inputs on NOP
edge are not changing. Iout=0mA

4. Timing

Patterns

DDR200 (100 MHz, CL=2) : t

=10ns, CL2,

BL=4, t

RRD

=2*t

, t

RCD

=3*t

, Read with

Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0
- repeat the same timing with random address
changing; 100% of data changing at every
burst

DDR266 (133MHz, CL=2.5) : t

=7.5ns,

CL=2.5, BL=4, t

RRD

=3*t

, t

RCD

=3*t

Read with Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst

DDR266 (133MHz, CL=2) : t

=7.5ns, CL2=2,

BL=4, t

RRD

=2*t

, t

RCD

=2*t

Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst

DDR333 (166MHz, CL=2.5) : t

=6ns,

BL=4, t

RRD

=3*t

, t

RCD

=3*t

, Read with

Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst

DETAILED TEST CONDITIONS FOR DDR SDRAM I

DD1

& I

DD7A

Legend:

A = Activate, R = Read, W = Write, P = Precharge, N = NOP

A (0-3) = Activate Bank 0-3

R (0-3) = Read Bank 0-3

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ADVANCED

WV3EG128M72EFSR-D3

DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND

RECOMMENDED AC OPERATING CONDITIONS

0°C T

+70°C; V

= +2.5V ±0.2V, V

CCQ

= +2.5V ±0.2V

AC Characteristics

335

262

265

Parameter

Symbol

Min

Max

Min

Max

Min

Max

Units

Notes

Access window of DQs from CK, CK#

-0.7

+0.7

-0.75

+0.75

-0.75

+0.75

CK high-level width

0.45

0.55

0.45

0.55

0.45

0.55

CK low-level width

0.45

0.55

0.45

0.55

0.45

0.55

Clock cycle time

CL=3

(3)

7.5

CL=2.5

(2.5)

7.5

CL=2

(2)

7.5

DQ and DM input hold time relative to DQS

0.45

0.5

14,17

DQ and DM input setup time relative to DQS

0.45

0.5

14,17

DQ and DM input pulse width (for each input)

DIPW

1.75

Access window of DQS from CK, CK#

DQSCK

-0.6

+0.6

-0.75

+0.75

-0.75

+0.75

DQS input high pulse width

DQSH

0.35

DQS input low pulse width

DQSL

0.35

DQS-DQ skew, DQS to last DQ valid, per group, per access

DQSQ

0.4

0.5

13,14

Write command to fi rst DQS latching transition

DQSS

0.75

1.25

0.75

1.25

0.75

1.25

DQS falling edge to CK rising - setup time

DSS

0.2

DQS falling edge from CK rising - hold time

DSH

0.2

Half clock period

, t

Data-out high-impedance window from CK, CK#

+0.7

+0.75

8,19

Data-out low-impedance window from CK, CK#

-0.7

-0.75

8,20

Address and control input hold time (fast slew rate)

IHf

0.75

0.90

Address and control input set-up time (fast slew rate)

ISf

0.75

0.90

Address and control input hold time (slow slew rate)

IHs

0.8

Address and control input setup time (slow slew rate)

ISs

0.8

Address and control input pulse width (for each input)

IPW

2.2

LOAD MODE REGISTER command cycle time

MRD

DQ-DQS hold, DQS to fi rst DQ to go non-valid, per access

-t

QHS

-t

QHS

-t

QHS

13,14

Data hold skew factor

QHS

0.55

0.75

ACTIVE to PRECHARGE command

RAS

70,000

120,000

ACTIVE to READ with Auto precharge command

RAP

ACTIVE to ACTIVE/AUTO REFRESH command period

AUTO REFRESH command period

RFC

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White Electronic Designs

March 2005
Rev. 0

ADVANCED

WV3EG128M72EFSR-D3

DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND

RECOMMENDED AC OPERATING CONDITIONS (continued)

Notes 1-5, 7; notes appear following parameter tables; 0°C T

+70°C; V

= +2.5V ±0.2V, V

CCQ

= +2.5V ±0.2V

AC Characteristics

335

262

265

Parameter

Symbol

Min

Max

Min

Max

Min

Max

Units

Notes

ACTIVE to READ or WRITE delay

RCD

PRECHARGE command period

DQS read preamble

RPRE

0.9

1.1

0.9

1.1

0.9

1.1

DQS read postamble

RPST

0.4

0.6

0.4

0.6

0.4

0.6

ACTIVE bank a to ACTIVE bank b command

RRD

DQS write preamble

WPRE

0.25

DQS write preamble setup time

WPRES

10,11

DQS write postamble

WPST

0.4

0.6

0.4

0.6

0.4

0.6

Write recovery time

Internal WRITE to READ command delay

WTR

Average periodic refresh interval

REFI

7.8

Exit SELF REFRESH to non-READ command

XSNR

Exit SELF REFRESH to READ command

XSRD

200

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White Electronic Designs

March 2005
Rev. 0

ADVANCED

WV3EG128M72EFSR-D3

12. The refresh period is 64ms. This equates to an average refresh

rate of 15.625µs (256Mb component) or 7.8125µs (512 Mb
component). However, an AUTO REFRESH command must be
asserted at least once every 140.6µs (256 Mb component) or
70.3µs (512Mb component); burst refreshing or posting by the
DRAM controller greater than eight refresh cycles is not allowed.

13. The valid data window is derived by achieving other specifi cations

- t

CK/2

), t

DQSQ

, and t

= t

- t

QHS

). The data valid

window derates directly proportional with the clock duty cycle
and a practical data valid window can be derived. The clock is
allowed a maximum duty cycled variation of 45/55. Functionality
is uncertain when operating beyond a 45/55 ratio. The data valid
window derating curves are provided below for duty cycles ranging
between 50/50 and 45/55.

14. Referenced to each output group: x4 = DQS with DQ0-DQ4.

15. READs and WRITEs with auto precharge are not allowed to be

issued until t

RAS

(MIN) can be satisfi ed prior to the internal precharge

command being issued.

16. JEDEC specifi es CK and CK# input slew rate must be > 1V/ns

(2V/ns differentially).

17. DQ and DM input slew rates must not deviate from DQS by more

than 10%. If the DQ/DM/DQS slew rate is less than 0.5V/ns,
timing must be derated: 50ps must be added to t

and t

for

each 100mV/ns reduction in slew rate. If slew rates exceed 4V/ns,
functionality is uncertain.

18. t

min is the lesser of t

min and t

min actually applied to the

device CK and CK# inputs, collectively during bank active.

19. This maximum value is derived from the referenced test load. In

practice, the values obtained in a typical terminated design may
refl ect up to 310ps less for t

(MAX) and last DVW. t

(MAX) will

prevail over the t

DQSCK

(MAX) + t

RPST

(MAX) condition. t

(MIN)

will prevail over t

DQSCK

(MIN) + PRE (MAX) condition.

20. For slew rates greater than 1V/ns the (LZ) transition will start about

310ps earlier.

21. CKE must be active (High) during the entire time a refresh

command is executed. That is, from the time the AUTO REFRESH
command is registered, CKE must be active at each rising clock
edge, until t

REF

later.

22. Whenever the operating frequency is altered, not including jitter,

the DLL is required to be reset. This is followed by 200 clock cycles
(before READ commands).

Notes

All voltages referenced to V

Tests for AC timing, I

, and electrical AC and DC characteristics

may be conducted at normal reference / supply voltage levels, but
the related specifi cations and device operations are guaranteed for
the full voltage range specifi ed.

Outputs are measured with equivalent load:

Output

OUT

)

Reference

Point

30pF

AC timing and I

tests may use a V

-to-V

swing of up to 1.5V

in the test environment, but input timing is still referenced to V

REF

(or to the crossing point for CK/CK#), and parameter specifi cations
are guaranteed for the specifi ed AC input levels under normal use
conditions. The minimum slew rate for the input signals used to
test the device is 1V/ns in the range between V

(AC) and V

(AC).

The AC and DC input level specifi cations are defi ned in the SSTL_
2 standard (i.e., the receiver will effectively switch as a result of the
signal crossing the AC input level, and will remain in that state as
long as the signal does not ring back above [below] the DC input
LOW [high] level).

Command/Address input slew rate = 0.5V/ns. For -75 with slew
rates 1V/ns and faster, t

and t

are reduced to 900ps. If the

slew rate is less than 0.5V/ns, timing must be derated: t

has an

additional 50ps per each 100mV/ns reduction in slew rate from the
500mV/ns. t

has 0ps added, that is, it remains constant. If the

slew rate exceeds 4.5V/ns, functionality is uncertain.

Inputs are not recognized as valid until V

REF

stabilizes. Exception:

during the period before V

REF

stabilizes, CKE

0.3 x V

CCQ

recognized as LOW.

8. t

and t

transitions occur in the same access time windows as

valid data transitions. These parameters are not referenced to a
specifi c voltage level, but specify when the device output is no
longer driving (HZ) and begins driving (LZ).

The maximum limit for this parameter is not a device limit. The
device will operate with a greater value for this parameter, but
system performance (bus turnaround) will degrade accordingly.

10. This is not a device limit. The device will operate with a negative

value, but system performance could be degraded due to bus
turnaround.

11.

It is recommended that DQS be valid (HIGH or LOW) on or before
the WRITE command. The case shown (DQS going from High-Z to
logic LOW) applies when no WRITEs were previously in progress
on the bus. If a previous WRITE was in progress, DQS could be
high during this time, depending on t

DQSS

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

March 2005
Rev. 0

ADVANCED

WV3EG128M72EFSR-D3

133.35 (5.25)

128.95 (5.076)

2x 3.00 (2x 0.118)

4x 4.00+/-0.1

64.77 (2.55)

1.80 (0.070)

3.80 (0.149)

6.35 (0.25)
4.175 (0.164)

2.175 (0.085)

49.53 (1.95)

120.65 (4.75)

6.35

1.0 ±0.05

(0.039 ±0.002)

1.27

(0.05)

0.20 ±0.15
(0.008 ±0.006)

2.50 (0.098)

184

3.99 MAX

0
0
.
2
1

1.27 +/-0.1

2x DIA. 2.50 +0.1/-0.00

29.97 ±0.15

(1.18 ±0.006)

19.80

(0.779)

10.00

(0.393)

(2x DIA 0.098 + 0.004/-0.00)

(0.25)

(4x 0.157+/-0.004)

(0.05+/-0.004)

)
2
7
4
.
0
(

(0.157 MAX)

PACKAGE DIMENSIONS FOR D3

* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)

ORDERING INFORMATION FOR D3

Part Number

Speed

CAS Latency

RCD

Height*

WV3EG128M72EFSR335D3

166MHz/333Mb/s

2.5

29.97 (1.18")

WV3EG128M72EFSR262D3

133MHz/266Mb/s

29.97 (1.18")

WV3EG128M72EFSR265D3

133MHz/266Mb/s

2.5

29.97 (1.18")

NOTES:

· Consult Factory for availability of Lead-Free products. (F = Lead-Free, G = RoHS Compliant)

· Vendor specifi c part numbers are used to provide memory components source control. The place holder for this is shown as lower case "x" in the part numbers above

and is to be replaced with the respective vendors code. Consult factory for qualifi ed sourcing options. (M = Micron, S = Samsung & consult factory for others)

· Consult factory for availability of industrial temperature (-40°C to 85°C) option

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