1
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White Electronic Designs
WEDPN16M72VR-XB2X
January 2005
Rev. 1
GENERAL DESCRIPTION
The 128MByte (1Gb) SDRAM is a high-speed CMOS,
dynamic random-access, memory using 5 chips containing
268,435,456 bits. Each chip is internally confi gured as a
quad-bank DRAM with a synchronous interface. Each of
the chip's 67,108,864-bit banks is organized as 8,192 rows
by 512 columns by 16 bits. The MCP also incorporates
two 16-bit universal bus drivers for input control signals
and addresses.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed (BA0, BA1 select the bank; A0-
12 select the row). The address bits registered coincident
with the READ or WRITE command are used to select the
starting column location for the burst access.
The SDRAM provides for programmable READ or WRITE
burst lengths of 1, 2, 4 or 8 locations, or the full page, with
a burst terminate option. An AUTO PRECHARGE function
may be enabled to provide a self-timed row precharge that
is initiated at the end of the burst sequence.
The 1Gb SDRAM uses an internal pipelined architecture
to achieve high-speed operation. This architecture is
compatible with the 2n rule of prefetch architectures, but
it also allows the column address to be changed on every
clock cycle to achieve a high-speed, fully random access.
Precharging one bank while accessing one of the other
three banks will hide the precharge cycles and provide
seamless, high-speed, random-access operation.
The 1Gb SDRAM is designed to operate in 3.3V, low-power
memory systems. An auto refresh mode is provided, along
with a power-saving, power-down mode.
All inputs and outputs are LVTTL compatible. SDRAMs offer
substantial advances in DRAM operating performance,
including the ability to synchronously burst data at a high
data rate with automatic column-address generation,
the ability to interleave between internal banks in order
to hide precharge time and the capability to randomly
change column addresses on each clock cycle during a
burst access.
16MX72 REGISTERED SYNCHRONOUS DRAM
FEATURES
Registered for enhanced performance of bus
speeds
100, 125, 133**MHz
Package:
219 Plastic Ball Grid Array (PBGA), 25 x 25mm
Single 3.3V 0.3V power supply
Fully Synchronous; all signals registered on positive
edge of system clock cycle
Internal pipelined operation; column address can be
changed every clock cycle
Internal banks for hiding row access/precharge
Programmable Burst length 1,2,4,8 or full page
8,192 refresh cycles
Commercial,
Industrial
and
Military
Temperature
Ranges
Organized as 16M x 72
Weight: WEDPN16M72VR-XB2X - 2.5 grams
typical
BENEFITS
59%
SPACE
SAVINGS
Reduced part count
Reduced
I/O
count
40% I/O Reduction
Reduced trace lengths for lower parasitic
capacitance
Glueless connection to memory controller/PCI
bridge
Suitable for hi-reliability applications
Laminate interposer for optimum TCE match
* This product is subject to change without notice.
** Available at commercial and industrial temperatures only.
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White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WEDPN16M72VR-XB2X
January 2005
Rev. 1
FIGURE 1 PIN CONFIGURATION
NOTE: DNU = Do Not Use; to be left unconnected for future upgrades.
NC = Not Connected Internally.
DNU* Pin K16 is reserved for optional CS2# pinout (CS# of U4). Contact factory for information.
Top View
1
2
3
4
5
6
7
8
9 10
11 12 13 14 15 16
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
DQ
1
DQ
3
DQ
6
DQ
7
CAS#
CS
0
#
V
SS
V
SS
NC
NC
DQ
56
DQ
57
DQ
60
DQ
62
Vss
V
SS
DQ
30
DQ
28
DQ
25
DQ
24
CLK
1
LE#
V
CC
V
CC
DNU*
NC
DQ
39
DQ
38
DQ
35
DQ
33
V
CC
DQ
0
DQ
2
DQ
4
DQ
5
DQMB0
WE#
RAS#
V
SS
V
SS
NC
NC
DQMB7
DQ
58
DQ
59
DQ
61
DQ
63
DQ
31
DQ
29
DQ
27
DQ
26
NC
DQMB3
NC
V
CC
V
CC
NC
NC
DQMB4
DQ
37
DQ
36
DQ
34
DQ
32
DQ
14
DQ
12
DQ
10
DQ
8
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
DQ
55
DQ
53
DQ
51
DQ
49
DQ
17
DQ
19
DQ
21
DQ
23
V
SS
V
SS
V
SS
Vss
V
SS
V
SS
V
SS
V
SS
DQ
40
DQ
42
DQ
44
DQ
46
DQ
15
DQ
13
DQ
11
DQ
9
DQMB1
CLK
0
CKE
V
CC
V
CC
NC
NC
NC
DQ
54
DQ
52
DQ
50
DQ
48
DQ
16
DQ
18
DQ
20
DQ
22
DQMB2
OE#
CS
1
#
V
SS
V
SS
NC
CLK
2
DQMB5
DQ
41
DQ
43
DQ
45
DQ
47
V
SS
V
SS
V
CC
V
CC
NC
NC
NC
V
SS
V
SS
NC
NC
DQMB6
NC
V
SS
V
CC
V
CC
V
CC
V
CC
V
SS
V
SS
NC
NC
NC
V
CC
V
CC
NC
NC
NC
NC
V
CC
V
SS
V
SS
A
9
A
0
A
2
A
12
NC
DQMB9
DQ
73
DQ
75
DQ
77
DQ
79
A
8
A
1
A
3
DNU
NC
NC
DQ
70
DQ
68
DQ
66
DQ
64
A
10
A
7
A
5
DNU
BA
0
NC
DQ
72
DQ
74
DQ
76
DQ
78
A
11
A
6
A
4
DNU
BA
1
NC
DQ
71
DQ
69
DQ
67
DQ
65
V
SS
V
SS
V
CC
V
CC
NC
NC
NC
V
SS
V
CC
V
CC
V
CC
V
CC
V
SS
V
SS
NC
NC
DQMB8
V
CC
V
SS
V
SS
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White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WEDPN16M72VR-XB2X
January 2005
Rev. 1
A
0-12
BA
0-1
CLK
0
CLK
CAS#
DQ
0
DQ
15
CKE
B
CKE
CS
0B
#
CS#
DQMB
0B
DQML
DQMB
1B
CLK
0
CKE
B
CS
1B
#
DQMB
2B
DQMB
3B
CLK
1
CKE
B
CS
0B
#
DQMB
4B
DQMB
5B
CLK
1
CKE
B
CS
1B
#
DQMB
6B
DQMB
7B
CLK
0
CKE
B
CS
0B
#
DQMB
8B
DQMB
9B
DQMH
DQ
0
DQ
15
U1
A
0-12
BA
0-1
CLK
DQ
16
DQ
31
RAS
B
#
WE
B
#
CAS
B
#
DQ
0
DQ
15
WE#
U0
RAS#
CAS#
WE# RAS#
CAS#
WE# RAS#
CAS#
WE# RAS#
CAS#
WE# RAS#
CKE
CS#
DQML
DQMH
DQ
0
DQ
15
U2
A
0-12
BA
0-1
CLK
DQ
32
DQ
47
CKE
CS#
DQML
DQMH
DQ
0
DQ
15
U3
A
0-12
BA
0-1
CLK
DQ
48
DQ
63
CKE
CS#
DQML
DQMH
DQ
0
DQ
15
U4
A
0-12
BA
0-1
CLK
DQ
64
DQ
79
CKE
CS#
DQML
DQMH
A
0-12
BA
0-
BA
1
CLK
2
OE#
LE#
U6
DQMB
0-9
74ALVC16334
U5
WE#
CKE
RAS#
CS
0-1
#
LE#
74ALVC16334
CAS#
WE
B
#
CKE
B
RAS
B
#
CS
0B-1B
#
CAS
B
#
LE#
OE#
OE#
CLK
CLK
DQMB
0B-9B
FIGURE 2 FUNCTIONALIN BLOCK DIAGRAM
4
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WEDPN16M72VR-XB2X
January 2005
Rev. 1
FUNCTIONAL DESCRIPTION
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed (BA0 and BA1 select the bank,
A0-12 select the row). The address bits (A0-8) registered
coincident with the READ or WRITE command are used to
select the starting column location for the burst access.
Prior to normal operation, the SDRAM must be initialized.
The following sections provide detailed information
covering device initialization, register defi nition, command
descriptions and device operation.
INITIALIZATION
SDRAMs must be powered up and initialized in a predefi ned
manner. Operational procedures other than those specifi ed
may result in undefi ned operation. Once power is applied
to V
CC
and V
CCQ
(simultaneously) and the clock is stable
(stable clock is defi ned as a signal cycling within timing
constraints specified for the clock pin), the SDRAM
requires a 100s delay prior to issuing any command
other than a COMMAND INHIBIT or a NOP. Starting at
some point during this 100s period and continuing at
least through the end of this period, COMMAND INHIBIT
or NOP commands should be applied.
Once the 100s delay has been satisfi ed with at least
one COMMAND INHIBIT or NOP command having been
applied, a PRECHARGE command should be applied. All
banks must be precharged, thereby placing the device in
the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles
must be performed. After the AUTO REFRESH cycles
are complete, the SDRAM is ready for Mode Register
programming. Because the Mode Register will power up
in an unknown state, it should be loaded prior to applying
any operational command.
REGISTER DEFINITION
MODE REGISTER
The Mode Register is used to defi ne the specifi c mode
of operation of the SDRAM. This defi nition includes the
selec-tion of a burst length, a burst type, a CAS latency,
an operating mode and a write burst mode, as shown in
Figure 3. The Mode Register is programmed via the LOAD
MODE REGISTER command and will retain the stored
information until it is programmed again or the device
loses power.
Mode register bits M0-M2 specify the burst length, M3
specifi es the type of burst (sequential or interleaved), M4-M6
specify the CAS latency, M7 and M8 specify the operating
mode, M9 specifi es the WRITE burst mode, and M10 and
M11 are reserved for future use. Address A12 (M12) is
undefi ned but should be driven LOW during loading of the
mode register.
The Mode Register must be loaded when all banks are
idle, and the controller must wait the specifi ed time before
initiating the subsequent operation. Violating either of these
requirements will result in unspecifi ed operation.
BURST LENGTH
Read and write accesses to the SDRAM are burst oriented,
with the burst length being programmable, as shown
in Figure 3. The burst length determines the maximum
number of column locations that can be accessed for a
given READ or WRITE command. Burst lengths of 1, 2, 4
or 8 locations are available for both the sequential and the
interleaved burst types, and a full-page burst is available
for the sequential type. The full-page burst is used in
conjunction with the BURST TERMINATE command to
generate arbitrary burst lengths.
Reserved states should not be used, as unknown operation
or incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of
columns equal to the burst length is effectively selected.
All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a
boundary is reached. The block is uniquely selected by
A1-8 when the burst length is set to two; by A2-8 when
the burst length is set to four; and by A3-8 when the burst
length is set to eight. The remaining (least signifi cant)
address bit(s) is (are) used to select the starting location
within the block. Full-page bursts wrap within the page if
the boundary is reached.
BURST TYPE
Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the
burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by
the burst length, the burst type and the starting column
address, as shown in Table 1.
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WEDPN16M72VR-XB2X
January 2005
Rev. 1
TABLE 1 BURST DEFINITION
FIGURE 3 MODE REGISTER DEFINITION
M3 = 0
1
2
4
8
Reserved
Reserved
Reserved
Full Page
M3 = 1
1
2
4
8
Reserved
Reserved
Reserved
Reserved
Operating Mode
Standard Operation
All other states reserved
0
-
0
-
Defined
-
0
1
Burst Type
Sequential
Interleaved
CAS Latency
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
Burst Length
M0
0
1
0
1
0
1
0
1
Burst Length
CAS Latency
BT
A
9
A
7
A
6
A
5
A
4
A
3
A
8
A
2
A
1
A
0
Mode Register (Mx)
Address Bus
M1
0
0
1
1
0
0
1
1
M2
0
0
0
0
1
1
1
1
M3
M4
0
1
0
1
0
1
0
1
M5
0
0
1
1
0
0
1
1
M6
0
0
0
0
1
1
1
1
M6-M0
M8
M7
Op Mode
A
10
A
11
Reserved* WB
0
1
Write Burst Mode
Programmed Burst Length
Single Location Access
M9
*Should program
M12, M11, M10 = 0, 0, 0
to ensure compatibility
with future devices.
Unused
A
12
Burst
Length
Starting Column
Address
Order of Accesses Within a Burst
Type = Sequential
Type = Interleaved
2
A0
0
0-1
0-1
1
1-0
1-0
4
A1
A0
0
0
0-1-2-3
0-1-2-3
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
2-3-0-1
1
1
3-0-1-2
3-2-1-0
8
A2
A1
A0
0
0
0
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7
0
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
0
1
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
0
4-5-6-7-0-1-2-3
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1
1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
Full
Page
(y)
n = A0-9/8/7
(location 0-y)
Cn, Cn + 1, Cn + 2
Cn + 3, Cn + 4...
...Cn - 1,
Cn...
Not Supported
NOTES:
1. For full-page accesses: y = 512.
2. For a burst length of two, A1-8 select the block-of-two burst; A0 selects the starting
column within the block.
3. For a burst length of four, A2-8 select the block-of-four burst; A0-1 select the starting
column within the block.
4. For a burst length of eight, A3-8 select the block-of-eight burst; A0-2 select the
starting column within the block.
5. For a full-page burst, the full row is selected and A0-8 select the starting column.
6. Whenever a boundary of the block is reached within a given sequence above, the
following access wraps within the block.
7. For a burst length of one, A0-8 select the unique column to be accessed, and Mode
Register bit M3 is ignored.
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