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White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
White Electronic Designs
WED9LC6816V
September 2003 Rev 1
ECO #16493
256Kx32 SSRAM/4Mx32 SDRAM
External Memory Solution for Texas Instruments
TMS320C6000 DSP
FEATURES
n
Clock speeds:
SSRAM: 200, 166,150, and 133 MHz
SDRAMs: 125 and 100 MHz
n
DSP Memory Solution
Texas Instruments TMS320C6201
Texas Instruments TMS320C6701
n
Packaging:
153 pin BGA, JEDEC MO-163
n
3.3V Operating supply voltage
n
Direct control interface to both the SSRAM and
SDRAM ports on the C6x
n
Common address and databus
n
65% space savings vs. monolithic solution
n
Reduced system inductance and capacitance
DESCRIPTION
The WED9LC6816V is a 3.3V, 256K x 32 Synchronous
Pipeline SRAM and a 4Mx32 Synchronous DRAM array
constructed with one 256K x 32 SBSRAM and two 4Mx16
SDRAM die mounted on a multilayer laminate sub-
strate. The device is packaged in a 153 lead, 14mm by
22mm, BGA.
The WED9LC6816V provides a total memory solution
for the Texas Instruments TMS320C6201 and the
TMS320C6701 DSPs The Synchronous Pipeline SRAM
is available with clock speeds of 200, 166,150,v and
133 MHz, allowing the user to develop a fast external
memory for the SSRAM interface port .
The SDRAM is available in clock speeds of 125 and
100 MHz, allowing the user to develop a fast external
memory for the SDRAM interface port.
The WED9LC6816V is available in both commercial
and industrial temperature ranges.
FIG. 1 PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
A
DQ
19
DQ
23
V
CC
V
SS
V
SS
V
SS
V
CC
DQ
24
DQ
28
B
DQ
18
DQ
22
V
CC
V
SS
SDCE
V
SS
V
CC
DQ
25
DQ
29
C
V
CCQ
V
CCQ
V
CC
SDWE
SDA
10
NC
V
CC
V
CCQ
V
CCQ
D
DQ
17
DQ
21
V
CC
V
SS
V
SS
V
SS
V
CC
DQ
26
DQ
30
E
DQ
16
DQ
20
V
CC
V
SS
SDCLK
V
SS
V
CC
DQ
27
DQ
31
F
V
CCQ
V
CCQ
V
CC
V
SS
V
SS
V
SS
V
CC
V
CCQ
V
CCQ
G
NC
NC
NC
SDRAS
SDCAS
V
SS
A
2
A
4
A
5
H
NC
NC
A
8
V
SS
V
SS
NC
A
1
A
3
A
10
J
A
6
A
7
A
9
V
SS
V
SS
NC
A
0
A
11
A
12
K
A
17
NC/A
18
NC/A
19
V
SS
V
SS
NC
NC
A
13
A
14
L
NC
NC
NC
BWE
2
BWE
3
NC
NC
A
15
A
16
M
V
CCQ
V
CCQ
V
CC
BWE
0
BWE
1
NC
V
CC
V
CCQ
V
CCQ
N
DQ
12
DQ
11
V
CC
V
SS
V
SS
V
SS
V
CC
DQ
4
DQ
0
P
DQ
13
DQ
10
V
CC
V
SS
SSCLK
V
SS
V
CC
DQ
5
DQ
1
R
V
CCQ
V
CCQ
V
CC
V
SS
V
SS
V
SS
V
CC
V
CCQ
V
CCQ
T
DQ
14
DQ
9
V
CC
SSADC
SSWE
NC
V
CC
DQ
6
DQ
2
U
DQ
15
DQ
8
V
CC
SSOE
SSCE
NC
V
CC
DQ
7
DQ
3
A
0-17
Address Bus
DQ
0-31
Data Bus
SSCLK
SSRAM Clock
SSADC
SSRAM Address Status Control
SSWE
SSRAM Write Enable
SSOE
SSRAM Output Enable
SDCLK
SDRAM Clock
SDRAS
SDRAM Row Address Strobe
SDCAS SDRAM Column Address Strobe
SDWE
SDRAM Write Enable
SDA
10
SDRAM Address
10/auto precharge
BWE
0-3
SSRAM Byte Write Enables
SDRAM SDQM 0-3
SSCE
Chip Enable SSRAM Device
SDCE
Chip Enable SDRAM Device
V
CC
Power Supply pins, 3.3V
V
CCQ
Data Bus Power Supply pins,
3.3V (2.5V future)
V
SS
Ground
NC
No Contact
T
OP
V
IEW
P
IN
D
ESCRIPTION
2
White Electronic Designs Corporation Westborough, MA (508) 366-5151
White Electronic Designs
WED9LC6816V
FIG. 2 BLOCK DIAGRAM
DQ
8-15
DQ
0-7
DQ
9-16
DQ
1-8
DQ
8-15
DQ
0-7
A
0-17
DQ
8-15
DQ
0-7
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
BWE
BW
1
BW
2
BW
3
BW
4
CE
2
OE
ADSC
CLK
DQ
0-31
A
0
A
1
DQ
24-31
DQ
16-23
DQ
25-32
DQ
17-24
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
11
A
10
/AP
BA
0
BA
1
LDQM
UDQM
CS
RAS
CAS
WE
CLK
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
11
A
10
/AP
BA
0
BA
1
LDQM
UDQM
CS
RAS
CAS
WE
CLK
A
12
A
13
A
12
A
13
DQ
8-15
DQ
0-7
DQ
24-31
DQ
16-23
SSWE
BWE
0
BWE
1
BWE
2
BWE
3
SSCE
SSOE
SSADC
SSCLK
SDA
10
SDCE
SDRAS
SDCAS
SDWE
SDCLK
3
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
White Electronic Designs
WED9LC6816V
O
UTPUT
F
UNCTIONAL
D
ESCRIPTIONS
Symbol
Type
Signal
Polarity
Function
SSCLK
Input
Pulse
Positive Edge
The system clock input. All of the SSRAM inputs are sampled on the rising edge of the clock.
SSADS
When sampled at the positive rising edge of the clock, SSADS, SSOE, and SSWE define
SSOE
Input
Pulse
Active Low
SSWE
the operation to be executed by the SSRAM.
SSCE
Input
Pulse
Active Low
SSCE disable or enable SSRAM device operation.
SDCLK
Input
Pulse
Positive Edge
The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock.
SDCE
Input
Pulse
Active Low
SDCE disable or enable device operation by masking or enabling all inputs except SDCLK and BWE
0-3
.
SDRAS
When sampled at the positive rising edge of the clock, SDCAS, SDRAS, and SDWE define
SDCAS
Input
Pulse
Active Low
SDWE
the operation to be executed by the SDRAM.
Address bus for SSRAM and SDRAM
A
0
and A
1
are the burst address inputs for the SSRAM
During a Bank Active command cycle, A
0-11
, SDA
10
defines the row address (RA
0-10
)
when sampled at the rising clock edge.
During a Read or Write command cycle, A
0-7
defines the column address (CA
0-7
) when
A
0-17
,
Input
Level
sampled at the rising clock edge. In addition to the row address, SDA
10
is used to invoke
SDA10
Autoprecharge operation at the end of the Burst Read or Write Cycle. If SDA
10
is high,
autoprecharge is selected and A
12
and A
13
define the bank to be precharged. If SDA
10
is
low, autoprecharge is disabled.
During a Precharge command cycle, SDA
10
is used in conjunction with A
12
and A
13
to
control which bank(s) to precharge. If SDA
10
is high, all banks will be precharged regardless
of the state of A
12
and A
13
. If SDA
10
is low, then A
12
and A
13
are used to define which
bank to precharge.
DQ
0-31
Input
Level
Data Input/Output are multiplexed on the same pins.
Output
BWE
0-3
perform the byte write enable function for the SSRAM and DQM function for the
BWE
0-3
Input
Pulse
SDRAM. BWE
0
is associated with DQ
0-7
, BWE
1
with DQ
8-15
, BWE
2
with DQ
16-23
and BWE
3
with DQ
24-31
.
V
CC
, V
SS
Supply
Power and ground for the input buffers and the core logic.
V
CCQ
Supply
Data base power supply pins, 3.3V (2.5V future).
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White Electronic Designs Corporation Westborough, MA (508) 366-5151
White Electronic Designs
WED9LC6816V
A
BSOLUTE
M
AXIMUM
R
ATINGS
Voltage on V
CC
Relative to V
SS
-0.5V to +4.6V
Vin (DQx)
-0.5V to Vcc +0.5V
Storage Temperature (BGA)
-55C to +125C
Junction Temperature
+150C
Short Circuit Output Current
100 mA
*Stress greater than those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other
conditions greater than those indicated in operational sections of
this specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
R
ECOMMENDED
DC O
PERATING
C
ONDITIONS
(V
CC
= 3.3V -5% / +10%
UNLESS
OTHERWISE
NOTED
; 0C T
A
70C,
C
OMMERCIAL
; -40C T
A
85C, I
NDUSTRIAL
)
Parameter
Symbol Min
Max
Units
Supply Voltage (1)
V
CC
3.135
3.6
V
Input High Voltage (1,2)
V
IH
2.0 V
CC
+0.3
V
Input Low Voltage (1,2)
V
IL
-0.3
0.8
V
Input Leakage Current
IL
I
-10
10
A
0 V
IN
V
CC
Output Leakage (Output Disabled)
IL
O
-10
10
A
0 V
IN
V
CC
SSRAM Output High (I
OH
= -4mA) (1)
V
OH
2.4
V
SSRAM Output Low (I
OL
= 8mA) (1)
V
OL
0.4
V
SDRAM Output High (I
OH
= -2mA)
V
OH
2.4
V
SDRAM Output Low (I
OL
= 2mA)
V
OL
0.4
V
NOTES:
1. All voltages referenced to V
SS
(GND).
2. Overshoot: V
IH
+6.0V for t t
KC
/2
Underershoot: V
IL
-2.0V for t t
KC
/2
DC E
LECTRICAL
C
HARACTERISTICS
(V
CC
= 3.3V -5% / +10%
UNLESS
OTHERWISE
NOTED
; 0C T
A
70C, C
OMMERCIAL
; -40C T
A
85C, I
NDUSTRIAL
)
Description
Conditions
Symbol Frequency
Typ
Max
Units
133MHz
500
625
Power Supply Current:
150MHz
500
650
Operating (1,2,3)
SSRAM Active / DRAM Auto Refresh
I
CC
1
166MHz
550
700
mA
200MHz
600
800
133MHz
325
425
Power Supply Current
150MHz
350
450
Operating (1,2,3)
SSRAM Active / DRAM Idle
I
CC
2
166MHz
400
495
mA
200MHz
450
585
Power Supply Current
83MHz
500
625
SSRAM Active / SSRAM Idle
I
CC
3
100MHz
500
650
mA
Operating (1,2,3)
125MHz
550
700
SSCE and SDCE V
CC
-0.2V,
CMOS Standby
All other inputs at V
SS
+0.2 V
IN
or
I
SB
1
20.0
40.0
mA
V
IN
V
CC
-0.2V, Clk frequency = 0
SSCE and SDCE V
IH
min
TTL Standby
All other inputs at V
IL
max V
IN
or
I
SB
2
30.0
55.0
mA
V
IN
V
CC
-0.2V, Clk frequency = 0
Auto Refresh
I
CC
5
250
300
mA
NOTES:
1. I
CC
(operating) is specified with no output current. I
CC
(operating) increases with faster cycle times and greater output loading.
2. "Device idle" means device is deselected (CE = V
IH
) Clock is running at max frequency and Addresses are switching each cycle.
3. Typical values are measured at 3.3V, 25C. I
CC
(operating) is specified at specified frequency.
BGA C
APACITANCE
Description
Conditions
Symbol
Typ
Max
Units
Address Input Capacitance (1)
T
A
= 25C; f = 1MHz
C
I
5
8
pF
Input/Output Capacitance (DQ) (1)
T
A
= 25C; f = 1MHz
C
O
8
10
pF
Control Input Capacitance (1)
T
A
= 25C; f = 1MHz
C
A
5
8
pF
Clock Input Capacitance (1)
T
A
= 25C; f = 1MHz
C
CK
4
6
pF
NOTE:
1. This parameter is sampled.
5
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
White Electronic Designs
WED9LC6816V
SSRAM AC C
HARACTERISTICS
(V
CC
= 3.3V -5% / +10%
UNLESS
OTHERWISE
NOTED
; 0C T
A
70C, C
OMMERCIAL
; -40C T
A
85C, I
NDUSTRIAL
)
Symbol 200MHz 166MHz 150MHz 133MHz
Parameter
Min
Max
Min
Max
Min
Max
Min
Max
Units
Clock Cycle Time
t
KHKH
5
6
7
8
ns
Clock HIGH Time
t
KLKH
1.6
2.4
2.6
2.8
ns
Clock LOW Time
t
KHKL
1.6
2.4
2.6
2.8
ns
Clock to output valid
t
KHQV
2.5
3.5
3.8
4.0
ns
Clock to output invalid
t
KHQX
1.5
1.5
1.5
1.5
ns
Clock to output on Low-Z
t
KQLZ
0
0
0
0
ns
Clock to output in High-Z
t
KQHZ
1.5
3
1.5
3.5
1.5
3.8
1.5
4.0
ns
Output Enable to output valid
t
OELQV
2.5
3.5
3.8
4.0
ns
Output Enable to output in Low-Z
t
OELZ
0
0
0
0
ns
Output Enable to output in High-Z
t
OEHZ
3.0
3.5
3.5
3.8
ns
Address, Control, Data-in Setup Time to Clock
t
S
1.5
1.5
1.5
1.5
ns
Address, Control, Data-in Hold Time to Clock
t
H
0.5
0.5
0.5
0.5
ns
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