ChipFind - документация

Электронный компонент: WED8L24513V

Скачать:  PDF   ZIP
1
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED8L24513V
Aug, 2002
Rev. 0A
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
PIN NAMES
BLOCK DIAGRAM
PIN CONFIGURATION
Asynchronous SRAM, 3.3V, 512Kx24
FEATURES
512Kx24 bit CMOS Static
Random Access Memory Array
Fast Access Times: 10, 12, and 15ns
Master Output Enable and Write Control
TTL Compatible Inputs and Outputs
Fully Static, No Clocks
Surface Mount Package
119 Lead BGA (JEDEC MO-163), No. 391
Small Footprint, 14mmx22mm
Multiple Ground Pins for Maximum Noise
Immunity
Single +3.3V (5%) Supply Operation
DSP Memory Solution
Motorola DSP5630x
Analog Devices SHARC
TM
DESCRIPTION
The WED8L24513VxxBC is a 3.3V, twelve megabit SRAM
constructed with three 512Kx8 die mounted on a multi-layer
laminate substrate. With 10 to 15ns access times, x24 width
and a 3.3V operating voltage, the WED8L24513V is ideal
for creating a single chip memory solution for the Motorola
DSP5630x (Figure 7) or a two chip solution for the Analog
Devices SHARC
TM
DSP (Figure 8).
The single or dual chip memory solutions offer improved
system performance by reducing the length of board traces
and the number of board connections compared to using
multiple monolithic devices.
The JEDEC Standard 119 lead BGA provides a 61% space
savings over using three 512Kx8, 400 mil wide SOJs and the
BGA package has a maximum height of 110 mils compared
to 148 mils for the SOJ packages.
A0-18
Address Inputs
E#
Chip Enable
W#
Master Write Enable
G#
Master Output Enable
DQ0-23 Common Data Input/Output
V
CC
Power (3.3V 5%)
GND
Ground
NC
No Connection
1
2
3
4
5
6
7
A
NC
AO
A1
A2
A3
A4
NC
B
NC
A5
A6
E#
A7
A8
NC
C
I/012
NC
NC
NC
NC
NC
I/00
D
I/013
V
CC
GND
GND
GND
V
CC
I/01
E
I/014
GND
V
CC
GND
V
CC
GND
I/02
F
I/015
V
CC
GND
GND
GND
V
CC
I/03
G
I/016
GND
V
CC
GND
V
CC
GND
I/04
H
I/017
V
CC
GND
GND
GND
V
CC
I/05
J
NC
GND
V
CC
GND
V
CC
GND
NC
K
I/018
V
CC
GND
GND
GND
V
CC
I/06
L
I/019
GND
V
CC
GND
V
CC
GND
I/07
M
I/020
V
CC
GND
GND
GND
V
CC
I/08
N
I/021
GND
V
CC
GND
V
CC
GND
I/09
P
I/022
V
CC
GND
GND
GND
V
CC
I/010
R
I/023
A18
NC
NC
NC
A17
I/011
T
NC
A9
A10
W#
A11
A12
NC
U
NC
A13
A14
G#
A15
A16
NC
512K x 24
Memory
Array
19
A0-A18
G#
W#
E#
DQ0-7
DQ8-15
DQ16-23
2
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED8L24513V
Aug, 2002
Rev. 0A
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
*Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions greater than those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
NOTE: For t
EHQZ
, t
GHQZ
and t
WLQZ
, Figure 2
ABSOLUTE MAXIMUM RATINGS
AC TEST CONDITIONS
RECOMMENDED DC OPERATING CONDITIONS
Input Pulse Levels
V
SS
to 3.0V
Input Rise and Fall Times
5ns
Input and Output Timing Levels
1.5V
Output Load
Figure 1
Voltage on any pin relative to VSS
-0.5V to 4.6V
Operating Temperature TA (Ambient)
Commercial
Industrial
0C to + 70C
-40C to +85C
Storage Temperature
-55C to +125C
Power Dissipation
1.5 Watts
Output Current.
50 mA
Parameter
Sym
Min
Typ
Max
Units
Supply Voltage
V
CC
3.135
3.3
3.465
V
Supply Voltage
V
SS
0
0
0
V
Input High Voltage
V
IH
2.2
--
V
CC
+0.3
V
Input Low Voltage
V
IL
-0.3
--
0.8
V
FIG. 1
FIG. 2
(f = 1.0MH
Z
, V
IN
= V
CC
or V
SS
)
These parameters are sampled, not 100% tested.
DC ELECTRICAL CHARACTERISTICS
TRUTH TABLE
CAPACITANCE
G# E#
W#
Mode
Output
Power
X
H
X
Standby
High Z
I
CC2
,I
CC3
H
L
H
Output Deselect
High Z
I
CC1
L
L
H
Read
D
OUT
I
CC1
X
L
L
Write
D
IN
I
CC1
353
5 pF
D
OUT
319
V
CC
R
L
= 50
V
L
= 1.5V
Q
Z0 = 50
65 pF
Parameter
Sym
Conditions
Min
Max
Units
10ns
12-15ns
Operating Power Supply Current
I
CC1
W# = V
IL
, II/O = 0mA,
Min Cycle
450
350
mA
Standby (TTL) Supply Current
I
CC2
E# > V
IH
, V
IN
< V
IL
or
V
IN
> V
IH
, f=MH
Z
150
150
mA
Full Standby CMOS
Supply Current
I
CC3
E# > V
CC
-0.2V
V
IN
> V
CC
-0.2V or
V
IN
< 0.2V
90
90
mA
Input Leakage Current
I
LI
V
IN
= 0V to V
CC
10
10
A
Output Leakage Current
I
LO
V I/O = 0V to V
CC
10
10
A
Output High Volltage
V
OH
I
OH
= -4.0mA
2.4
V
Output Low Voltage
V
OL
I
OL
= 4.0mA
0.4
0.4
V
Parameter
Sym
Max
Unit
Address Lines
CA
8
pF
Data Lines
CD/Q
10
pF
Write & Output Enable Lines
W#, G#
8
pF
Chip Enable Lines
E# - E2#
8
pF
3
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED8L24513V
Aug, 2002
Rev. 0A
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
AC CHARACTERISTICS READ CYCLE
Parameter
Symbol
10ns
12ns
15ns
Units
JEDEC Alt.
Min
Max
Min
Max
Min
Max
Read Cycle Time
t
AVAV
t
RC
10
12
15
ns
Address Access Time
t
AVQV
t
AA
10
12
15
ns
Chip Enable Access Time
t
ELQV
t
ACS
10
12
15
ns
Chip Enable to Output in Low Z (1)
t
ELQX
t
CLZ
3
3
3
ns
Chip Disable to Output in High Z (1)
t
EHQZ
t
CHZ
5
6
7
ns
Output Hold from Address Change
t
AVQX
t
OH
3
3
3
ns
Output Enable to Output Valid
t
GLQV
t
OE
5
6
7
ns
Output Enable to Output in Low Z (1)
t
GLQX
t
OLZ
0
0
0
ns
Output Disable to Output in High Z(1)
t
GHQZ
t
OHZ
5
6
7
ns
FIG. 3 READ CYCLE 1 - W# HIGH, G#, E# LOW
FIG. 4 READ CYCLE 2 - W# HIGH
A
Q
t
AVQV
t
ELQV
t
GLQV
t
ELQX
t
GLQX
t
AVAV
t
EHQZ
t
GHQZ
G#
E#
NOTE 1: Parameter is guaranteed, but not tested.
A
Q
t
AVQX
t
AVQV
t
AVAV
DATA 2
ADDRESS 1
ADDRESS 2
DATA 1
4
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED8L24513V
Aug, 2002
Rev. 0A
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
NOTE 1: Parameter is guaranteed, but not tested.
AC CHARACTERISTICS WRITE CYCLE
FIG. 5 WRITE CYCLE 1 - W# CONTROLLED
A
D
t
AVWH
t
ELWH
t
WHAX
t
WLWH
t
DVWH
t
WLQZ
t
WHQX
t
AVWL
t
WHDX
t
AVAV
DATA VALID
HIGH Z
W#
E#
Q
Parameter
Symbol
10ns
12ns
15ns
Units
JEDEC
Alt.
Min
Max
Min
Max
Min
Max
Write Cycle Time
t
AVAV
t
WC
10
12
15
ns
Chip Enable to End of Write
t
ELWH
t
ELEH
t
CW
t
CW
8
8
9
9
9
9
ns
ns
Address Setup Time
t
AVWL
t
AVEL
t
AS
t
AS
0
0
0
0
0
0
ns
ns
Address Valid to End of Write
t
AVWH
t
AVEH
t
AW
t
AW
8
8
9
9
10
10
ns
ns
Write Pulse Width
t
WLWH
t
WLEH
t
WP
t
WP
8
8
10
10
11
11
ns
ns
Write Recovery Time
t
WHAX
t
EHAX
t
WR
t
WR
0
0
0
0
0
0
ns
ns
Data Hold Time
t
WHDX
t
EHDX
t
DH
t
DH
0
0
0
0
0
0
ns
ns
Write to Output in High Z (1)
t
WLQZ
t
WHZ
0
5
0
6
0
7
ns
Data to Write Time
t
DVWH
t
DVEH
t
DW
t
DW
6
6
6
6
7
7
ns
ns
Output Active from End of Write (1)
t
WHQX
t
WLZ
3
3
3
ns
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED8L24513V
Aug, 2002
Rev. 0A
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
FIG. 6 WRITE CYCLE 2 - E# CONTROLLED
Commercial (0C to +70)
ORDERING INFORMATION
Part Number
Speed
(ns)
Package
No.
WED8L24513V10BC
10
391
WED8L24513V12BC
12
391
WED8L24513V15BC
15
391
Part Number
Speed
(ns)
Package
No.
WED8L24513V12BI
12
391
WED8L24513V15BI
15
391
PACKAGE NO. 391
119 LEAD BGA
JEDEC MO-163
A
D
t
AVEH
t
ELEH
t
EHAX
t
DVEH
t
EHDX
t
AVAV
DATA VALID
HIGH Z
W#
t
WLEH
E#
Q
t
AVEL
0.110 MAX
0.711 (0.028)
MAX
1.27 (0.050)
TYP
1.27 (0.050) TYP
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
14.00 (0.551) TYP
A1
CORNER
20.32 (0.800)
TYP
22.00 (0.866)
TYP
7.62 (0.300)
TYP
R 1.52 (0.062)
MAX (4x)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
Industrial (-40C to +85C)
6
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED8L24513V
Aug, 2002
Rev. 0A
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
FIG. 7 INTERFACING THE MOTOROLA DSP5630x DSP FAMILY WITH THE
WED8L24513V (512K x 24)
Address Bus
A23-0
Databus
D23-0
Motorola
DSP5630x
WED8L24513V
(512K x 24)
AA0
AA1
AA2
AA3
WR#
RD#
A18-0
E#
W#
G#
DQ0-23
WED8L24513V
(512K x 24)
A18-0
E#
W#
G#
DQ0-23
WED8L24513V
(512K x 24)
A18-0
E#
W#
G#
DQ0-23
Notes:
1. In this example three 512K x 24 external memory
arrays are shown, one for X data, one for Y data and
one for Program. Specific applications may require
one, two, or all three arrays.
2. Any combination of AA0-AA3 may be used as chip
selects. However, each chip select may only be used
to select one memory array.
Address Bus
A31-0
Databus
D47-0
Analog
ADSP-2106xL
WED8L24513V
(512K x 24)
MS
X
WR#
RD#
A18-0
E#
W#
G#
DQ16-23
DQ8-15
DQ0-7
WED8L24513V
(512K x 24)
A18-0
E#
W#
G#
DQ16-23
DQ8-15
DQ0-7
FIG. 8 INTERFACING THE ANALOG DEVICES 2106XL DSP FAMILY WITH THE
WED8L24513V (512K X 24)