1
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED416S16030A
April 2006
Rev. 1
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
The WED416S16030A is 268,435,456 bits of synchronous
high data rate DRAM organized as 4 x 4,196,304 words x
16 bits. Synchronous design allows precise cycle control
with the use of system clock. I/O transactions are possible
on every clock cycle. Range of operating frequencies,
programmable burst lengths and programmable latencies
allow the same device to be useful for a variety of high
bandwidth, high performance memory system applica-
tions.
Available in a 54 pin TSOP type II package the
WED416S16030A is tested over the industrial temp range
(-40C to +85C) providing a solution for rugged main
memory applications.
4M x 16 Bits x 4 Banks Synchronous DRAM
Single 3.3V power supply
Fully Synchronous to positive Clock Edge
Clock Frequency = 133, 125, and 100MH
Z
SDRAM CAS Latency = 2
Burst
Operation
Sequential or Interleave
Burst length = programmable 1,2,4,8 or full page
Burst Read and Write
Multiple Burst Read and Single Write
DATA Mask Control per byte
Auto Refresh (CBR) and Self Refresh
8192 refresh cycles across 64ms
Automatic and Controlled Precharge Commands
Suspend Mode and Power Down Mode
Industrial
Temperature
Range
PIN DESCRIPTION
A0-12
Address Inputs
BA0, BA1 Bank Select Addresses
CE#
Chip Select
WE#
Write Enable
CK
Clock Input
CKE
Clock Enable
DQ0-15
Data Input/Output
L(U)DQM Data Input/Output Mask
RAS#
Row Address Strobe
CAS#
Column Address Strobe
V
DD
Power (3.3V)
V
DDQ
Data Output Power
V
SS
Ground
V
SSQ
Data Output Ground
NC
No Connection
PIN CONFIGURATION
FEATURES
DESCRIPTION
*This product is subject to change without notice.
Pin
Front
Pin
Front
Pin
Front
1
V
CC
19
CE#
37
CKE
2
DQ0
20
BA0
38
CK
3
V
CCQ
21
BA1
39
UDQM
4
DQ1
22
A10/AP
40
NC/RFU
5
DQ2
23
A0
41
V
SS
6
V
SSQ
24
A1
42
DQ8
7
DQ3
25
A2
43
V
CCQ
8
DQ4
26
A3
44
DQ9
9
V
CCQ
27
V
CC
45
DQ10
10
DQ5
28
V
SS
46
V
SSQ
11
DQ6
29
A4
47
DQ11
12
V
SSQ
30
A5
48
DQ12
13
DQ7
31
A6
49
V
CCQ
14
V
CC
32
A7
50
DQ13
15
LDQM
33
A8
51
DQ14
16
WE#
34
A9
52
V
SSQ
17
CAS#
35
A11
53
DQ15
18
RAS#
36
A12
54
V
SS
2
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED416S16030A
April 2006
Rev. 1
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
Symbol
Type
Signal
Polarity
Function
CK
Input
Pulse
Positive Edge The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock.
CKE
Input
Level
Active High
Activates the CK signal when high and deactivates the CK signal when low. By deactivating the
clock, CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh mode.
CE#
Input
Pulse
Active Low
CE# disable or enable device operation by masking or enabling all inputs except CK, CKE and
DQM.
RAS#, CAS#
WE#
Input
Pulse
Active Low
When sampled at the positive rising edge of the clock, CAS#, RAS#, and WE# defi ne the operation
to be executed by the SDRAM.
BA0,BA1
Input
Level
--
Selects which SDRAM bank is to be active.
A0-12,
A10/AP
Input
Level
--
During a Bank Activate command cycle, A0-12 defi nes the row address (RA0-12) when sampled at
the rising clock edge.
During a Read or Write command cycle, A0-8 defi nes the column address (CA0-8) when sampled
at the rising clock edge. In addition to the row address, A10/AP is used to invoke Autoprecharge
operation at the end of the Burst Read or Write cycle. If A10/AP is high, autoprecharge is selected
and BA0, BA1 defi nes the bank to be precharged . If A10/AP is low, autoprecharge is disabled.
During a Precharge command cycle, A10/AP is used in conjunction with BA0, BA1 to control which
bank(s) to precharge. If A10/AP is high, all banks will be precharged regardless of the state of BA0,
BA1. If A10/AP is low, then BA0, BA1 is used to defi ne which bank to precharge.
DQ0-15
Input/Output
Level
--
Data Input/Output are multiplexed on the same pins
L(U)DQM
Input
Pulse
Mask
Active High
The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high.
In Read mode, DQM has a latency of two clock cycles and controls the output buffers like an output
enable. In Write mode, DQM has a latency of zero and operates as a word mask by allowing input
data to be written if it is low but blocks the Write operation if DQM is high.
V
CC
, V
SS
Supply
Power and ground for the input buffers and the core logic.
V
CCQ
, V
SSQ
Supply
Isolated power and ground for the output buffers to improve noise immunity.
INPUT/OUTPUT FUNCTIONAL DESCRIPTION
3
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED416S16030A
April 2006
Rev. 1
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
Parameter/Condition
Symbol
All Speeds
Units
Notes
Operating Current Active Mode; Burst = 2; READ or WRITE t
RC
= t
RC(MIN)
I
CC1
135
mA
3, 18, 19,
32
Standby Current Power-Down Mode; All banks idle; CKE = LOW
I
CC2
2
mA
32
Standby Current: Active Mode; CKE = HIGH; CS# = HIGH; All banks active after tRCD met;
No accesses in progress
I
CC3
40
mA
3, 12, 19,
32
Operating Current: Burst Mode; Page burst: READ or WRITE; All banks active
I
CC4
135
mA
3, 18, 19,
32
Auto Refresh Current
CS# = HIGH: CKE = HIGH
t
RFC =
t
RFC(MIN)
I
CC5
285
mA
3, 12, 18,
19, 32, 33
t
RFC =
7.81 s
I
CC6
3.5
mA
Self Refresh Current: CKE 0.2V
Standard
I
CC7
2.5
mA
4
Low Power (L)
I
CC7
1.5
mA
Parameter
Symbol
Max
Unit
Input Capacitance (A0-12, BA0-1)
CI1
4
pF
Input Capacitance (CK, CKE, RAS#,
CAS#, WE#, CE#, L(U)DQM )
CI2 4
pF
Input/Output Capacitance (DQ0-15)
C
OUT
6.5
pF
Parameter
Symbol Min
Typ
Max
Unit
Notes
Supply Voltage
V
CC
3.0
3.3 3.6
V
Input High Voltage
V
IH
2.0
3.0
V
CC
+0.3
V
Input Low Voltage
V
IL
-0.3
--
0.8
V
Output High Voltage
V
OH
2.4
--
--
V
(I
OH
= -4mA)
Output Low Voltage
V
OL
--
--
0.4
V
(I
OL
= 4mA)
Input Leakage Voltage
I
IL
-5
--
5
A
Output Leakage Voltage
I
OL
-5
--
5
A
RECOMMENDED DC OPERATING CONDITIONS
(Voltage Referenced to: V
SS
= 0V, 40C Ta 85C)
ABSOLUTE MAXIMUM RATINGS
CAPACITANCE
(T
A
= 25C, f = 1MH
Z
, V
CC
= 3.3V
TO
3.6V)
Parameter
Symbol Min
Max Units
Power Supply Voltage
V
DD
-1.0
+4.6
V
Input Voltage
V
IN
-1.0
+4.6
V
Output Voltage
V
OUT
-1.0
+4.6
V
Operating Temperature
t
OPR
-40
+85
C
Storage Temperature
t
STG
-55
+125
C
Power Dissipation
P
D
1.0
W
Short Circuit Output Current
I
OS
50
mA
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions greater than those indicated
in the operational sections of this specifi cation is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
OPERATING CURRENT CHARACTERISTICS
(V
CC
= 3.3V, -40C Ta +85C)
NOTES:
1. Measured with outputs open.
2. Refresh period is 64ms.
4
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED416S16030A
April 2006
Rev. 1
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
OPERATING AC PARAMETERS
(Vcc = 3.3V, -40C Ta +85C)
Parameter
Symbol
7
75
8
10
Unit
Notes
Clock Cycle Time
CAS latency = 3
t
CK
7.5
7.5
8
10
ns
1
CAS latency = 2
7.5
8
10
1
Clock to Valid Output Delay
t
AC
5.4
6
6
7
ns
1,2
Output Data Hold Time
t
OH
3
3
3
3
ns
2
Clock High Pulse Width
t
CH
2.5
2.5
3
3
ns
3
Clock Low Pulse Width
t
CL
2.5
2.5
3
3
ns
3
Input Setup Time
t
CMS
1.5
1.5
2
2
ns
3
Input Hold Time
t
CMH
0.8
0.8
1
1
ns
3
Clock to Output in Low-Z
t
LZ
1
1
1
1
ns
2
Clock to Output in High-Z
t
HZ
5.4
6
6
7
ns
Row Active to Row Active Delay
t
RRD
15
15
20
20
ns
4
RAS# to CAS# Delay
t
RCD
20
20
20
20
ns
4
Row Precharge Time
t
RP
20
20
20
20
ns
4
Row Active Time
t
RAS
45
45
50
50
ns
4
Row Cycle Time - Operation
t
RC
65
65
70
70
ns
4
Last Data In to New Column Address Delay
t
CDL
1
1
1
1
CK
5
Last Data In to Row Precharge
t
RDL
2
2
2
2
CK
5
Last Data In to Burst Stop
t
BDL
1
1
1
1
CK
5
Column Address to Column Address Delay
t
CCD
1
1
1
1
CK
6
Number of Valid Output Data
CAS latency = 3
2
2
2
2
ea
7
CAS latency = 2
1
1
1
1
Data Setup Time
t
DS
1.5
1.5
2
2
ns
Data Hold Time
t
DH
0.8
0.8
1
1
ns
NOTES:
1.
Parameters depend on programmed CAS latency.
2.
If clock rise time is longer than 1ns, (t
RISE
2-0.5)ns should be added to the parameter.
3.
Assumed input rise and fall time = 1ns. If t
RISE
& t
FALL
are longer than 1ns, [(t
RISE
+ t
FALL
)/2]-1ns should be added to the parameter.
4.
The minimum number of clock cycles required is determined by dividing the minimum time required by the clock cycle time and then
rounding up to the next higher integer.
5.
Minimum delay is required to complete write.
6.
All devices allow every cycle column address changes.
7.
In case of row precharge interrupt, auto precharge and read burst stop.
AC CHARACTERISTICS
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED416S16030A
April 2006
Rev. 1
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
Command
CKE
CE#
RAS#
CAS#
WE#
DQM
BA0,1
A10/AP
A0-9,
A11-12
Notes
Previous
Cycle
Current
Cycle
Register
Mode Register Set
H
X
L
L
L
L
X
OP CODE
Refresh
Auto(CBR)
Entry Self
H
H
L
L
L
H
X
X
X
X
Precharge
Single Bank
H
X
L
L
H
L
X
BA
L
X
2
All Banks
X
H
X
Bank Activate
H
X
L
L
H
H
X
BA
Row Address
2
Write
Auto Precharge Disable
H
X
L
H
L
L
X
BA
L
Column
Address
2
Auto Precharge Enable
H
Read
Auto Precharge Disable
H
X
L
H
L
H
X
BA
L
Column
Address
2
Auto Precharge Enable
H
Burst Stop
H
X
L
H
H
L
X
X
X
X
3
No Operation
H
X
L
H
H
H
X
X
X
X
Device Select
H
X
H
X
X
X
X
X
X
X
Clock Suspend/Standby Mode
L
X
X
X
X
X
X
X
X
X
4
Data
Write/Output Enable
H
X
X
X
X
X
L
X
X
X
5
Mask/Output Disable
H
Power Down Mode
Entry
X
L
H
X
X
X
X
X
X
X
6
Exit
H
NOTES:
1. All of the SDRAM operations are defi ned by states of CE#, WE#, RAS#, CAS#, and DQM at the positive rising edge of the clock.
2. Bank Select (BA), if BA0, BA1 = 0, 0 then bank A is selected, if BA0, BA1 = 1, 0 then bank B, if BA0, BA1 = 0, 1 then bank C, if BA0, BA1 = 1, 1 then bank D is selected, respectively.
3. During a Burst Write cycle there is a zero clock delay, for a Burst Read cycle the delay is equal to the CAS# latency.
4. During normal access mode, CKE is held high and CK is enabled. When it is low, it freezes the internal clock and extends data Read and Write operations. One clock delay is
required for mode entry and exit.
5. The DQM has two functions for the data DQ Read and Write operations. During a Read cycle, when DQM goes high at a clock timing the data outputs are disabled and become high
impedance after a two clock delay. DQM also provides a data mask function for Write cycles. When it activates, the Write operation at the clock is prohibted (zero clock latency).
6. All banks must be precharged before entering the Power Down Mode. The Power Down Mode does not perform any Refresh operations, therefore the device cannot remain in this
mode longer than the Refresh period (t
REF
) of the device. One clock delay is required for mode entry and exit.
COMMAND TRUTH TABLE
(X = Don't Care, H = Logic High, L = Logic Low)
PDF 
ZIP