PRELIMINARY*
1
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
June 2006
Rev. 2
WED3EG7218S-JD3
FEATURES
Double-data-rate architecture
DDR200, DDR266, DDR333 and DDR400
JEDEC design specifi ed
BI-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input.
Auto and self refresh
Serial presence detect
Power supply:
V
CC
= V
CCQ
= 2.5V0.2V
(100, 133 and 166MHz)
V
CC
= V
CCQ
= 2.6V0.1V
(200MHz)
JEDEC 184 pin DIMM package
JD3 PCB height: 30.48 (1.20") Max
NOTE: Consult factory for availability of:
RoHS
Products
Vendor source control options
Industrial temperature option
128MB 16Mx72 DDR SDRAM UNBUFFERED
DESCRIPTION
The WED3EG7218S is a 16Mx72 Double Data Rate
SDRAM memory module based on 128Mb DDR SDRAM
component. The module consists of nine 16Mx8 DDR
SDRAMs in 66 pin TSOP packages mounted on a 184
pin FR4 substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
* This product is under development, is not qualifi ed or characterized and is subject to
change without notice.
OPERATING FREQUENCIES
DDR400 @CL=3
DDR333 @CL=2.5
DDR266 @CL=2
DDR266 @CL=2.5
DDR200 @CL=2
Clock Speed
200MHz
166MHz
133MHz
133MHz
100MHz
CL-t
RCD
-t
RP
3-3-3
2.5-3-3
2-2-2
2.5-3-3
2-2-2
2
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED3EG7218S-JD3
June 2006
Rev. 2
PRELIMINARY
PIN CONFIGURATION
PIN NAMES
Pin
Front
Pin
Front
Pin
Front
Pin
Front
1
V
REF
47
DQS8
93
V
SS
139
V
SS
2
DQ0
48
A0
94
DQ4
140
DQM8
3
V
SS
49
CB2
95
DQ5
141
A10
4
DQ1
50
V
SS
96
V
CCQ
142
CB6
5
DQS0
51
CB3
97
DQM0
143
V
CCQ
6
DQ2
52
BA1
98
DQ6
144
CB7
7
V
CC
53
DQ32
99
DQ7
145
V
SS
8
DQ3
54
V
CCQ
100
V
SS
146
DQ36
9
NC
55
DQ33
101
NC
147
DQ37
10
NC
56
DQS4
102
NC
148
V
CC
11
V
SS
57
DQ34
103
*A13
149
DQM4
12
DQ8
58
V
SS
104
V
CCQ
150
DQ38
13
DQ9
59
BA0
105
DQ12
151
DQ39
14
DQS1
60
DQ35
106
DQ13
152
V
SS
15
V
CCQ
61
DQ40
107
DQM1
153
DQ44
16
CK1
62
V
CCQ
108
V
CC
154
RAS#
17
CK1#
63
WE#
109
DQ14
155
DQ45
18
V
SS
64
DQ41
110
DQ15
156
V
CCQ
19
DQ10
65
CAS#
111
*CKE1
157
CS0#
20
DQ11
66
V
SS
112
V
CCQ
158
*CS1#
21
CKE0
67
DQS5
113
*BA2
159
DQM5
22
V
CCQ
68
DQ42
114
DQ20
160
V
SS
23
DQ16
69
DQ43
115
A12
161
DQ46
24
DQ17
70
V
CC
116
V
SS
162
DQ47
25
DQS2
71
CS2#
117
DQ21
163
*CS3#
26
V
SS
72
DQ48
118
A11
164
V
CCQ
27
A9
73
DQ49
119
DQM2
165
DQ52
28
DQ18
74
V
SS
120
V
CC
166
DQ53
29
A7
75
CK2#
121
DQ22
167
NC
30
V
CCQ
76
CK2
122
A8
168
V
CC
31
DQ19
77
V
CCQ
123
DQ23
169
DQM6
32
A5
78
DQS6
124
V
SS
170
DQ54
33
DQ24
79
DQ50
125
A6
171
DQ55
34
V
SS
80
DQ51
126
DQ28
172
V
CCQ
35
DQ25
81
V
SS
127
DQ29
173
NC
36
DQS3
82
V
DDID
128
V
CCQ
174
DQ60
37
A4
83
DQ56
129
DQM3
175
DQ60
38
V
CC
84
DQ57
130
A3
176
V
SS
39
DQ26
85
V
CC
131
DQ30
177
DQM7
40
DQ27
86
DQS7
132
V
SS
178
DQ62
41
A2
87
DQ58
133
DQ31
179
DQ63
42
V
SS
88
DQ59
134
CB4
180
V
CCQ
43
A1
89
V
SS
135
CB5
181
SA0
44
CB0
90
NC
136
V
CCQ
182
SA1
45
CB1
91
SDA
137
CK0
183
SA2
46
V
CC
92
SCL
138
CK0#
184
V
CCSPD
A0 A12
Address input (Multiplexed)
BA0-BA1
Select Bank Address
DQ0-DQ63
Data Input/Output
CB0-CB7
Check bits
DQS0-DQS8
Data Strobe Input/Output
CK0, CK1, CK2
Clock input
CK0#, CK1#, CK2#
Clock input
CKE0
Clock Enable input
CS0#
Chip select Input
RAS#
Row Address Strobe
CAS#
Column Address Strobe
WE#
Write Enable
DQM0-DQM8
Data-in Mask
V
CC
Power Supply (2.5V)
V
CCQ
Power Supply for DQS (2.5V)
V
SS
Ground
V
REF
Power Supply for Reference
V
CCSPD
Serial EEPROM Power Supply (2.3V to 3.6V)
SDA
Serial data I/O
SCL
Serial clock
SA0-SA2
Address in EEPROM
V
DDID
V
DD
Identifi cation Flag
NC
No Connect
* Not Used
3
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED3EG7218S-JD3
June 2006
Rev. 2
PRELIMINARY
FUNCTIONAL BLOCK DIAGRAM
CS0#
DQS0
DQM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
CS#
DQS
DQS1
DQM1
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
CS#
DQS
DQ16
DQS2
DQM2
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
CS#
DQS
DQ24
DQS3
DQM3
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
CS#
DQS
CB0
DQS8
DQM8
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
CS#
DQS
DQ32
DQS4
DQM4
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
CS#
DQS
DQ40
DQS5
DQM5
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
CS#
DQS
DQ48
DQS6
DQM6
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
CS#
DQS
DQ56
DQS7
DQM7
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
CS#
DQS
SERIAL PD
SDA
SCL
WP
A0
A2
A1
SA0
SA2
SA1
V
CCSPD
V
CCQ
V
CC
V
REF
V
SS
SPD
DDR SDRAMs
DDR SDRAMs
DDR SDRAMs
DDR SDRAMs
CLOCK INPUT
CK0, CK0#
CK1, CK1#
CK2, CK2#
3 SDRAMS
3 SDRAMS
3 SDRAMS
RAS#
CAS#
BA0-BA1
WE#
A0-A12
CKE0
RAS#: DDR SDRAMs
CAS#: DDR SDRAMs
BA0-BA1: DDR SDRAMs
WE#: DDR SDRAMs
A0-A12: DDR SDRAMs
CKE0: DDR SDRAMs
NOTE: All resistor values are 22 ohms unless otherwise specifi ed
4
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED3EG7218S-JD3
June 2006
Rev. 2
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Units
Voltage on any pin relative to V
SS
V
IN
, V
OUT
-0.5 ~ 3.6
V
Voltage on V
CC
supply relative to V
SS
V
CC
, V
CCQ
-1.0 ~ 3.6
V
Storage Temperature
T
STG
-55 ~ +150
C
Power Dissipation
P
D
9
W
Short Circuit Current
I
0S
50
mA
Notes:
Permanent device damage may occur if `ABSOLUTE MAXIMUM RATINGS' are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability
DC CHARACTERISTICS
(0C T
A
70C, V
CC
= 2.5V O.2V)
Parameter
Symbol
Min
Max
Unit
Supply Voltage
V
CC
2.3
2.7
V
Supply Voltage
V
CCQ
2.3
2.7
V
Reference Voltage
V
REF
1.15
1.35
V
Termination Voltage
V
TT
1.15
1.35
V
Input High Voltage
V
IH
V
REF
+0.15
V
CCQ
+0.3
V
Input Low Voltage
V
IL
-0.3
V
REF
+0.15
V
Output High Voltage
V
OH
V
TT
+0.76
--
V
Output Low Voltage
V
OL
--
V
TT
-0.76
V
Parameter
Symbol
Max
Unit
Input Capacitance (A0-A12)
C
IN1
45
pF
Input Capacitance (RAS#,CAS#,WE#)
C
IN2
45
pF
Input Capacitance (CKE0, CKE1)
C
IN3
45
pF
Input Capacitance (CK0,CK0#)
C
IN4
40
pF
Input Capacitance (CS0#, CS1#)
C
IN5
44
pF
Input Capacitance (DQM0-DQM8)
C
IN6
15
pF
Input Capacitance (BA0-BA1)
C
IN7
45
pF
Data Input/Output capacitance (DQ0-DQ63)(DQS)
C
OUT
15
pF
Data Input/Output Capacitance (CB0-CB7)
C
OUT
15
pF
CAPACITANCE
(TA = 25C. f = 1MHz, V
CC
= 2.5V)
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED3EG7218S-JD3
June 2006
Rev. 2
PRELIMINARY
Parameter
Symbol Conditions
DDR400@
CL=3
Max
DDR333@
CL=2.5
Max
DDR266@
CL=2
Max
DDR266@
CL=2.5
Max
DDR200@
CL=2
Max
Units
Operating
Current
I
CC0
One device bank; Active =
Precharge; T
RC
=T
RC
(MIN);
T
CK
=T
CK
(MIN); DQ,DM and DQS
inputs changing once per clock cycle;
Address and control inputs changing
once every two cycles
990
990
810
mA
Operating
Current
I
CC1
One device bank; Active-read-
Precharge; Burst = 2; T
RC
=T
RC
(MIN);
T
CK
=T
CK
(MIN); lout=0mA; Address
and control inputs changing once per
clock cycle
1260
1260
1035
mA
Precharge
Power-Down
Standby
Current
I
CC2P
All device banks idle; Power-down
mode; T
CK
=T
CK
(MIN); CKE=(low)
270
270
255
mA
Idle Standby
Current
I
CC2F
CS# = High; All device banks idle;
T
CK
=T
CK
(MIN); CKE=high; Address
and other control inputs changing
once per clock cycle. V
IN
= V
REF
for
DQ, DQS and DM.
495
495
405
mA
Active Power-
Down Standby
Current
I
CC3P
One device bank active; Power-down
mode; T
CK
(MIN); CKE=(low)
315
315
270
mA
Active Standby
Current
I
CC3N
CS# = High; CKE = High; One
device bank; Active-Precharge; T
RC
= T
RAS
(MAX); T
CK
= T
CK
(MIN); DQ,
DM and DQS inputs changing twice
per clock cycle; Address and other
control inputs changing once per
clock cycle.
540
540
450
mA
Operating
Current
I
CC4R
Burst = 2; Reads; Continous burst;
One device bank active; Address
and control inputs changing once per
clock cycle;
T
CK
= T
CK
(MIN); lout = 0mA
1800
1800
1485
mA
Operating
Current
I
CC4W
Burst = 2; Writes; Continous burst;
One device bank active; Address
and control inputs changing once per
clock cycle; T
CK
= T
CK
(MIN); DQ, DM
and DQS inputs changing twice per
clock cycle.
1935
1935
1530
mA
Auto Refresh
Current
I
CC5
T
RC
= T
RC
(MIN)
1935
1935
1530
mA
Self Refresh
Current
I
CC6
CKE 0.2V
Standard
18
18
18
mA
Low Power
9
9
9
I
CC
SPECIFICATIONS AND TEST CONDITIONS
DDR400: V
CC =
V
CCQ
= +2.6V 0.1V; DDR333, 266, 200: V
CC =
V
CCQ
= +2.5V 0.2V includes DDR SDRAM component only
6
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED3EG7218S-JD3
June 2006
Rev. 2
PRELIMINARY
I
DD1
: OPERATING CURRENT : ONE BANK
1. Typical Case : V
CC
=2.5V, T=25C
2. Worst Case : V
CC
=2.7V, T=10C
3. Only one bank is accessed with t
RC
(min), Burst
Mode, Address and Control inputs on NOP edge
are changing once per clock cycle. I
OUT
= 0mA
4. Timing Patterns :
DDR200 (100 MHz, CL=2) : t
CK=
10ns, CL2,
BL=4, t
RCD=
2*t
CK
, t
RAS=
5*t
CK
Read : A0 N R0 N N P0 N A0 N - repeat the
same timing with random address changing;
50% of data changing at every burst
DDR266 (133MHz, CL=2.5) : t
CK=
7.5ns,
CL=2.5, BL=4, t
RCD=
3*t
CK
, t
RC=
9*t
CK
, t
RAS=
5*t
CK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
DDR266 (133MHz, CL=2) : t
CK
=7.5ns, CL=2,
BL=4, t
RCD
=3*t
CK
, t
RC
=9*t
CK
, t
RAS
=5*t
CK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
DDR333 (166MHz, CL=2.5) : t
CK
=6ns, BL=4,
t
RCD
=10*t
CK
, t
RAS
=7*t
CK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
DDR400 (200MHz, CL=3) : t
CK
=5ns, BL=4,
t
RCD
=15*t
CK
, t
RAS
=7*t
CK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
I
DD7A
: OPERATING CURRENT : FOUR BANKS
1. Typical Case : V
CC
=2.5V, T=25C
2. Worst Case : V
CC
=2.7V, T=10C
3. Four banks are being interleaved with t
RC
(min),
Burst Mode, Address and Control inputs on NOP
edge are not changing. Iout=0mA
4. Timing Patterns :
DDR200 (100 MHz, CL=2) : t
CK
=10ns, CL2,
BL=4, t
RRD
=2*t
CK
, t
RCD
=3*t
CK
, Read with
Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0
repeat the same timing with random address
changing; 100% of data changing at every
burst
DDR266 (133MHz, CL=2.5) : t
CK
=7.5ns,
CL=2.5, BL=4, t
RRD
=3*t
CK
, t
RCD
=3*t
CK
Read with Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
DDR266 (133MHz, CL=2) : t
CK
=7.5ns, CL2=2,
BL=4, t
RRD
=2*t
CK
, t
RCD
=2*t
CK
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
DDR333 (166MHz, CL=2.5) : t
CK
=6ns,
BL=4, t
RRD
=3*t
CK
, t
RCD
=3*t
CK
, Read with
Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
DDR400 (200MHz, CL=3) : t
CK
=5ns,
BL=4, t
RRD
=10*t
CK
, t
RCD
=15*t
CK
, Read with
Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
DETAILED TEST CONDITIONS FOR DDR SDRAM I
DD1
& I
DD7A
Legend:
A = Activate, R = Read, W = Write, P = Precharge, N = NOP
A (0-3) = Activate Bank 0-3
R (0-3) = Read Bank 0-3
7
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED3EG7218S-JD3
June 2006
Rev. 2
PRELIMINARY
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS
DDR400: V
CC
= V
CCQ
= +2.6V 0.1V; DDR333, 266, 200: V
CC
= V
CCQ
= +2.5V 0.2V
AC Characteristics
403
335
262/265
202
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Units
Notes
Access window of DQs from CK, CK#
t
AC
-0.70
+0.70
-0.70
+0.70
-0.75
+0.75
-0.75
+0.75
ns
CK high-level width
t
CH
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
t
CK
16
CK low-level width
t
CL
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
t
CK
16
Clock cycle time
CL=3
t
CK
(3)
5
7.5
ns
22
CL=2.5 t
CK
(2.5)
6
13
6
13
7.5
13
7.5
13
ns
22
CL=2
t
CK
(2)
7.5
13
7.5
13
7.5
13
10
13
ns
22
DQ and DM input hold time relative to DQS
t
DH
0.40
0.45
0.5
0.5
ns
14,17
DQ and DM input setup time relative to DQS
t
DS
0.40
0.45
0.5
0.5
ns
14,17
DQ and DM input pulse width (for each input)
t
DIPW
1.75
1.75
1.75
1.75
ns
17
Access window of DQS from CK, CK#
t
DQSCK
-0.60
+0.60
-0.60
+0.60
-0.75
+0.75
-0.75
+0.75
ns
DQS input high pulse width
t
DQSH
0.35
0.35
0.35
0.35
t
CK
DQS input low pulse width
t
DQSL
0.35
0.35
0.35
0.35
t
CK
DQS-DQ skew, DQS to last DQ valid, per group,
per access
t
DQSQ
0.40
0.45
0.5
0.5
ns
13,14
Write command to fi rst DQS latching transition
t
DQSS
0.72
1.28
0.75
1.25
0.75
1.25
0.75
1.25
t
CK
DQS falling edge to CK rising - setup time
t
DSS
0.2
0.2
0.2
0.2
t
CK
DQS falling edge from CK rising - hold time
t
DSH
0.2
0.2
0.2
0.2
t
CK
Half clock period
t
HP
t
CH
, t
CL
t
CH
, t
CL
t
CH
, t
CL
t
CH
, t
CL
ns
18
Data-out high-impedance window from CK, CK#
t
HZ
+0.70
+0.70
+0.75
+0.75
ns
8,19
Data-out low-impedance window from CK, CK#
t
LZ
-0.70
-0.70
-0.75
-0.75
ns
8,20
Address and control input hold time (fast slew rate)
t
IHf
0.60
0.75
0.90
0.90
ns
6
Address and control input set-up time (fast slew rate)
t
ISf
0.60
0.75
0.90
0.90
ns
6
Address and control input hold time (slow slew rate)
t
IHs
0.60
0.80
1
1
ns
6
Address and control input setup time (slow slew rate)
t
ISs
0.60
0.80
1
1
ns
6
Address and control input pulse width (for each input)
t
IPW
2.2
2.2
2.2
2.2
ns
LOAD MODE REGISTER command cycle time
t
MRD
10
12
15
15
ns
DQ-DQS hold, DQS to fi rst DQ to go non-valid, per
access
t
QH
t
HP
-t
QHS
t
HP
-t
QHS
t
HP
-t
QHS
t
HP
-t
QHS
ns
13,14
Data hold skew factor
t
QHS
0.50
0.55
0.75
0.75
ns
ACTIVE to PRECHARGE command
t
RAS
40
70,000
42
70,000
40
120,000
45
120,000
ns
15
ACTIVE to READ with Auto precharge command
t
RAP
15
15
15
20
ns
ACTIVE to ACTIVE/AUTO REFRESH command period
t
RC
55
60
60
65
ns
AUTO REFRESH command period
t
RFC
70
72
75
75
ns
21
8
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED3EG7218S-JD3
June 2006
Rev. 2
PRELIMINARY
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS (continued)
DDR400: V
CC
= V
CCQ
= +2.6V 0.1V; DDR333, 266, 200: V
CC
= V
CCQ
= +2.5V 0.2V
AC Characteristics
403
335
262/265
202
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Units
Notes
ACTIVE to READ or WRITE delay
t
RCD
15
15
15
20
ns
PRECHARGE command period
t
RP
15
15
15
20
ns
DQS read preamble
t
RPRE
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
t
CK
DQS read postamble
t
RPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
t
CK
ACTIVE bank a to ACTIVE bank b command
t
RRD
10
12
15
15
ns
DQS write preamble
t
WPRE
0.25
0.25
0.25
0.25
t
CK
DQS write preamble setup time
t
WPRES
0
0
0
0
ns
10,11
DQS write postamble
t
WPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
t
CK
9
Write recovery time
t
WR
15
15
15
15
ns
Internal WRITE to READ command delay
t
WTR
2
1
1
1
t
CK
Data valid output window
NA
t
QH
-t
DQSQ
t
QH
-t
DQSQ
t
QH
-t
DQSQ
t
QH
-t
DQSQ
ns
13
REFRESH to REFRESH command interval
t
REFC
70.3
70.3
70.3
70.3
s
12
Average periodic refresh interval
t
REFI
7.8
7.8
7.8
7.8
s
12
Terminating voltage delay to V
CC
t
VTD
0
0
0
0
ns
Exit SELF REFRESH to non-READ command
t
XSNR
70
75
75
75
ns
Exit SELF REFRESH to READ command
t
XSRD
200
200
200
200
t
CK
9
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White Electronic Designs
WED3EG7218S-JD3
June 2006
Rev. 2
PRELIMINARY
11. It is recommended that DQS be valid (HIGH or LOW) on or before
the WRITE command. The case shown (DQS going from High-Z to
logic LOW) applies when no WRITEs were previously in progress
on the bus. If a previous WRITE was in progress, DQS could be
high during this time, depending on t
DQSS
.
12. The refresh period is 64ms. This equates to an average refresh
rate of 7.8125s. However, an AUTO REFRESH command must
be asserted at least once every 70.3s; burst refreshing or posting
by the DRAM controller greater than eight refresh cycles is not
allowed.
13. The valid data window is derived by achieving other specifi cations
- t
HP
(t
CK/2
), t
DQSQ
, and t
QH
(t
QH
= t
HP
- t
QHS
). The data valid
window derates directly proportional with the clock duty cycle
and a practical data valid window can be derived. The clock is
allowed a maximum duty cycled variation of 45/55. Functionality
is uncertain when operating beyond a 45/55 ratio. The data valid
window derating curves are provided below for duty cycles ranging
between 50/50 and 45/55.
14. Referenced to each output group: x8 = DQS with DQ0-DQ7.
15. READs and WRITEs with auto precharge are not allowed to be
issued until t
RAS
(MIN) can be satisfi ed prior to the internal precharge
command being issued.
16. JEDEC
specifi es CK and CK# input slew rate must be > 1V/ns
(2V/ns differentially).
17. DQ and DM input slew rates must not deviate from DQS by more
than 10%. If the DQ/DM/DQS slew rate is less than 0.5V/ns,
timing must be derated: 50ps must be added to t
DS
and t
DH
for
each 100mV/ns reduction in slew rate. If slew rates exceed 4V/ns,
functionality is uncertain.
18. t
HP
min is the lesser of t
CL
min and t
CH
min actually applied to the
device CK and CK# inputs, collectively during bank active.
19. t
HZ
(MAX) will prevail over the t
DQSCK
(MAX) + t
RPST
(MAX)
condition. t
LZ
(MIN) will prevail over t
DQSCK
(MIN) + PRE (MAX)
condition.
20. For slew rates greater than 1V/ns the (LZ) transition will start about
310ps earlier.
21. CKE must be active (High) during the entire time a refresh
command is executed. That is, from the time the AUTO REFRESH
command is registered, CKE must be active at each rising clock
edge, until t
RFC
has been satisfi ed.
22. Whenever the operating frequency is altered, not including jitter,
the DLL is required to be reset. This is followed by 200 clock cycles
(before READ commands).
Notes
1.
All voltages referenced to V
SS
2.
Tests for AC timing, I
DD
, and electrical AC and DC characteristics
may be conducted at normal reference / supply voltage levels, but
the related specifi cations and device operations are guaranteed for
the full voltage range specifi ed.
3.
Outputs are measured with equivalent load:
Output
Output
(V
(V
OUT
OUT
)
Reference
Reference
Point
Point
50
50
V
TT
TT
30pF
30pF
4.
AC timing and I
DD
tests may use a V
IL
-to-V
IH
swing of up to 1.5V
in the test environment, but input timing is still referenced to V
REF
(or to the crossing point for CK/CK#), and parameter specifi cations
are guaranteed for the specifi ed AC input levels under normal use
conditions. The minimum slew rate for the input signals used to
test the device is 1V/ns in the range between V
IL
(AC) and V
IH
(AC).
5.
The AC and DC input level specifi cations are defi ned in the SSTL_
2 standard (i.e., the receiver will effectively switch as a result of the
signal crossing the AC input level, and will remain in that state as
long as the signal does not ring back above [below] the DC input
LOW [high] level).
6.
For slew rates less than 1V/ns and greater than or equal to 0.5V/
ns. If the slew rate is less than 0.5V/ns, timing must be derated: t
IS
has an additional 50ps per each 100mV/ns reduction in slew rate
from the 500mV/ns. t
IH
has 0ps added, that is, it remains constant.
If the slew rate exceeds 4.5V/ns, functionality is uncertain. For 403
and 335, slew rates must be greater than or equal to 0.5V/ns.
7.
Inputs are not recognized as valid until V
REF
stabilizes. Exception:
during the period before V
REF
stabilizes, CKE
0.3 x V
CCQ
is
recognized as LOW.
8. t
HZ
and t
LZ
transitions occur in the same access time windows as
valid data transitions. These parameters are not referenced to a
specifi c voltage level, but specify when the device output is no
longer driving (HZ) and begins driving (LZ).
9.
The intent of the "Don't Care" state after completion of the
postamble is the DQS-driven signal should either be HIGH, LOW,
or high-Z, and that any signal transition within the input switching
region must follow valid input requirements. That is, if DQS
transitions HIGH (above V
IHDC
(MIN) then it must not transition
LOW (below V
IHDC
) prior to t
DQSH
(MIN).
10. This is not a device limit. The device will operate with a negative
value, but system performance could be degraded due to bus
turnaround.
10
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED3EG7218S-JD3
June 2006
Rev. 2
PRELIMINARY
133.48
(5.255" MAX.)
3.99
(0.157 (2x))
17.78
(0.700)
10.01
(0.394)
6.35
(0.250)
64.77
(2.550)
1.78
(0.070)
49.53
(1.950)
3.00
(0.118)
(4x)
30.48
(1.20)
MAX
2.31
(0.091)
(2x)
1.27
(0.050 TYP.)
6.35
(0.250)
128.95
(5.077")
131.34
(5.171")
2.54
(0.100)
3.99
(0.157)
(MIN)
1.27 0.10
(0.050 0.004)
ORDERING INFORMATION FOR JD3
Part Number
Speed/Data Rate
Frequency
CAS Latency
t
RCD
t
RP
Height*
WED3EG7218S403JD3xxx
200MHz/400Mb/s
3
3
3
30.48mm (1.20")
WED3EG7218S335JD3xxx
166MHz/333Mb/s
2.5
3
3
30.48mm (1.20")
WED3EG7218S262JD3xxx
133MHz/266Mb/s
2
2
2
30.48mm (1.20")
WED3EG7218S265JD3xxx
133MHz/266Mb/s
2.5
3
3
30.48mm (1.20")
WED3EG7218S202JD3xxx
100MHz/200Mb/s
2
2
2
30.48mm (1.20")
NOTES:
Consult Factory for availability of RoHS products. (G = RoHS Compliant)
Vendor
specifi c part numbers are used to provide memory components source control. The place holder for this is shown as lower case "x" in the part numbers above and is to
be replaced with the respective vendors code. Consult factory for qualifi ed sourcing options. (M = Micron, S = Samsung & consult factory for others)
Consult factory for availability of industrial temperature (-40C to 85C) option
PACKAGE DIMENSIONS FOR JD3
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
11
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED3EG7218S-JD3
June 2006
Rev. 2
PRELIMINARY
PART NUMBERING GUIDE
WED 3 E G 72M 18 S xxx JD3 x x G
WEDC
MEMORY (SDRAM)
DDR
GOLD
DEPTH
BUS WIDTH
2.5V
SPEED (Mb/s)
PACKAGE 184 PIN
INDUSTRIAL TEMP OPTION
(For commercial leave "blank"
for industrial add "I")
COMPONENT VENDOR NAME
(M = Micron)
(S = Samsung)
G = RoHS COMPLIANT
12
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED3EG7218S-JD3
June 2006
Rev. 2
PRELIMINARY
Document Title
128MB 16Mx72 DDR SDRAM UNBUFFERED
DRAM DIE OPTIONS:
SAMSUNG: H-Die
MICRON: T26Z: G-Die
Revision History
Rev #
History
Release Date Status
Rev A
Created Datasheet
3-6-02
Advanced
Rev 0
0.1 Updated I
DD
and CAP specs
0.2 Updated AC specs
0.3 Moved from Advanced to Preliminary
0.4 Added Lead-Free and RoHS note
11-04
Preliminary
Rev 1
1.0 Added JEDEC PCB option (JD3)
1.1 D3 PCB option "NOT RECOMMENDED FOR NEW
DESIGNS"
11-05
Preliminary
Rev 2
2.1 Removed "D3" package option
2.2 Added "Part Numbering Guide"
2.3 Added DRAM die options
2.4 Added DDR400 and DDR333 I
CC
& AC specifi cations
6-06
Preliminary
PDF 
ZIP