1
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
White Electronic Designs
WED3DL328V
June 2002, Rev. 1
ECO #15237
8Mx32 SDRAM
n
53% Space Savings vs. Monolithic Solution
n
Reduced System Inductance and Capacitance
n
Pinout and Footprint Compatible to SSRAM 119 BGA
n
3.3V Operating Supply Voltage
n
Fully Synchronous to Positive Clock Edge
n
Clock Frequencies of 133MHz, 125MHz and 100MHz
n
Burst Operation
Sequential or Interleave
Burst Length = Programmable 1, 2, 4, 8 or Full Page
Burst Read and Write
Multiple Burst Read and Single Write
n
Data Mask Control Per Byte
n
Auto and Self Refresh
n
Automatic and Controlled Precharge Commands
n
Suspend Mode and Power Down Mode
n
119 Pin BGA, JEDEC MO-163
The WED3DL328V is an 8Mx32 Synchronous DRAM
configured as 4x2Mx32. The SDRAM BGA is con-
structed with two 8Mx16 SDRAM die mounted on a
multi-layer laminate substrate and packaged in a 119
lead, 14mm by 22mm, BGA.
The WED3DL328V is an ideal SDRAM wide I/O memory
solution for all high performance, computer applica-
tions which include Network Processors, DSPs and
Functional ASICs.
The WED3DL328V is available in clock speeds of
133MHz, 125MHz and 100MHz. The range of operat-
ing frequencies, programmable burst lengths and
programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
The package and design provides performance en-
hancements via a 50% reduction in capacitance vs.
two monolithic devices. The design includes internal
ground and power planes which reduces inductance
on the ground and power pins allowing for improved
decoupling and a reduction in system noise.
FIG. 1
*NOTE: Pin B
3
is designated as NC/A
12
. This pin is used for future density upgrades as address pin A
12
.
P
IN
D
ESCRIPTION
P
IN
C
ONFIGURATION
(T
OP
VIEW
)
DESCRIPTION
A
0
A
11
Address Bus
BA
0-1
Bank Select Addresses
DQ
Data Bus
CLK
Clock
CKE
Clock Enable
DQM
Data Input/Output Mask
RAS
Row Address Strobe
CAS
Column Address Strobe
CE
Chip Enable
V
DD
Power Supply pins, 3.3V
V
DDQ
Data Bus Power Supply pins,3.3V
V
SS
Ground pins
1
2
3
4
5
6
7
A
V
DDQ
NC
BA
0
NC
A
10
A
7
V
DDQ
A
B
NC
NC
NC/A
12
*
CAS
A
11
NC
NC
B
C
NC
NC
BA
1
V
DD
A
9
A
8
NC
C
D
DQ
C
NC
V
SS
NC
V
SS
NC
DQ
B
D
E
DQ
C
DQ
C
V
SS
CE
V
SS
DQ
B
DQ
B
E
F
V
DDQ
DQ
C
V
SS
RAS
V
SS
DQ
B
V
DDQ
F
G
DQ
C
DQ
C
DQMC
NC
DQMB
DQ
B
DQ
B
G
H
DQ
C
DQ
C
V
SS
CKE
V
SS
DQ
B
DQ
B
H
J
V
DDQ
V
DD
NC
V
DD
NC
V
DD
V
DDQ
J
K
DQ
D
DQ
D
V
SS
CLK
V
SS
DQ
A
DQ
A
K
L
DQ
D
DQ
D
DQMD
NC
DQMA
DQ
A
DQ
A
L
M
V
DDQ
DQ
D
V
SS
WE
V
SS
DQ
A
V
DDQ
M
N
DQ
D
DQ
D
V
SS
A
1
V
SS
DQ
A
DQ
A
N
P
DQ
D
NC
V
SS
A
0
V
SS
NC
DQ
A
P
R
NC
A
6
NC
V
DD
NC
A
2
NC
R
T
NC
NC
A
5
A
4
A
3
NC
NC
T
U
V
DDQ
NC
NC
NC
NC
NC
V
DDQ
U
1
2
3
4
5
6
7
FEATURES
2
White Electronic Designs Corporation Westborough, MA (508) 366-5151
White Electronic Designs
WED3DL328V
FIG. 2 8MX32 SDRAM BLOCK DIAGRAM
DQMC
DQMD
DQ
B
DQ
A
DQ
8-15
DQ
0-7
DQ
8-15
DQ
0-7
ADDR
0-11
BA
0
BA
1
DQMA
DQMB
CE
RAS
CAS
WE
CLK
CKE
BA
0
BA
1
LDQM
UDQM
CS
RAS
CAS
WE
CLK
CKE
BA
0
BA
1
LDQM
UDQM
CS
RAS
CAS
WE
CLK
CKE
DQ
D
DQ
C
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
/AP
A
11
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
/AP
A
11
DQ
0-31
3
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
White Electronic Designs
WED3DL328V
I
NPUT
/O
UTPUT
F
UNCTIONAL
D
ESCRIPTION
RECOMMENDED DC OPERATING CONDITIONS
(Voltage Referenced to: V
SS
= 0V, T
A
= 0C to +70C)
ABSOLUTE MAXIMUM RATINGS*
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage
V
DD
/V
DDQ
3.0
3.3
3.6
V
Input High Voltage
V
IH
2.0
3.0
V
DD
+0.3
V
Input Low Voltage
V
IL
-0.3
0.8
V
Output High Voltage (I
OH
= -2mA)
V
OH
2.4
V
Output Low Voltage (I
OL
= 2mA)
V
OL
0.4
V
Input Leakage Voltage
I
IL
-5
5
A
Output Leakage Voltage
I
OL
-5
5
A
CAPACITANCE
(T
A
= 25C, f = 1MHz, V
DD
= 3.3V)
Parameter
Symbol
Min
Max
Units
Power Supply Voltage
V
DD
/V
DDQ
-1.0
+4.6
V
Input Voltage
V
IN
-1.0
+4.6
V
Output Voltage
V
OUT
-1.0
+4.6
V
Operating Temperature
T
OPR
-0
+70
C
Storage Temperature
T
STG
-55
+125
C
Power Dissipation
P
D
1.5
W
Short Circuit Output Current
I
OS
50
mA
*Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions greater than those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
Parameter
Symbol
Max
Unit
Input Capacitance
C
I1
4
pF
Input/Output Capacitance (DQ)
C
Out
5
pF
Symbol
Type
Signal
Polarity
Function
CLK
Input
Pulse
Positive Edge
The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock.
CKE
Input
Level
Active High
Activates the CLK signal when high and deactivates the CLK signal when low. By deactivating the clock, CKE low
initiates the Power Down mode, Suspend mode, or the Self Refresh mode.
CE
Input
Pulse
Active Low
CE disable or enable device operation by masking or enabling all inputs except CLK, CKE and DQM.
RAS, CAS
Input
Pulse
Active Low
When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be
WE
executed by the SDRAM.
BA
0
,BA
1
Input
Level
Selects which SDRAM bank is to be active.
During a Bank Activate command cycle, A
0-11
defines the row address (RA
0-11
) when sampled at the rising clock
edge.
During a Read or Write command cycle, A
0-8
defines the column address (CA
0-8
) when sampled at the rising
A
0-11
,
clock edge. In addition to the row address, A
10
/AP is used to invoke Autoprecharge operation at the end of the
A
10
/AP
Input
Level
Burst Read or Write cycle. If A
10
/AP is high, autoprecharge is selected and BA
0
, BA
1
defines the bank to be
precharged . If A
10
/AP is low, autoprecharge is disabled.
During a Precharge command cycle, A
10
/AP is used in conjunction with BA
0
, BA
1
to control which
bank(s) to precharge. If A
10
/AP is high, all banks will be precharged regardless of the state of BA
0
,
BA
1
. If A
10
/AP is low, then BA
0
, BA
1
is used to define which bank to precharge.
DQ
Input/Output
Level
Data Input/Output are multiplexed on the same pins
The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In
Read
DQM
Input
Pulse
Mask
mode, DQM has a latency of two clock cycles and controls the output buffers like an output enable. In Write
Active High
mode, DQM has a latency of zero and operates as a word mask by allowing input data to be written if it is low
but blocks the Write operation if DQM is high.
V
DD
, V
SS
Supply
Power and ground for the input buffers and the core logic.
V
DDQ
Supply
Isolated power and ground for the output buffers to improve noise immunity.
4
White Electronic Designs Corporation Westborough, MA (508) 366-5151
White Electronic Designs
WED3DL328V
Parameter
Symbol
Conditions
7
8
10
Units
Operating Current (One Bank Active) (1)
I
CC
1
Burst Length = 1, t
RC
t
RC
(min), I
OL
= 0mA
300
280
225
mA
Operating Current (Burst Mode) (1)
I
CC
4
Page Burst, 4 banks active, t
CCD
= 2 clocks
340
290
240
mA
Precharge Standby Current in Power Down Mode
I
CC
2
P
CKE V
IL
(max), t
CC
= 15ns
2
2
2
mA
I
CC
2
PS
CKE, CLK V
IL
(max), t
CC
= , Inputs Stable
2
2
2
mA
I
CC
1N
CKE = V
IH
, t
CC
= 15ns
100
100
100
mA
Precharge Standby Current in Non-Power Down Mode
Input Change one time every 30ns
I
CC
1
NS
CKE V
IH
(min), t
CC
=
70
70
70
mA
No Input Change
Precharge Standby Current in Power Down Mode
I
CC
3
P
CKE V
IL
(max), t
CC
= 15ns
12
12
12
mA
I
CC
3
PS
CKE V
IL
(max), t
CC
=
12
12
12
mA
Active Standby Current in Non-Power Down Mode
I
CC
3
N
CKE = V
IH
, t
CC
= 15ns
60
60
60
mA
(One Bank Active)
Input Change one time every 30ns
I
CC
3
NS
CKE V
IH
(min), t
CC
= , No Input Change
40
40
40
mA
Refresh Current (2)
I
CC
5
t
RC
t
RC
(min)
440
420
420
mA
Self Refresh Current
I
CC
6
CKE 0.2V
3
3
3
mA
NOTES:
1. Measured with outputs open.
2. Refresh period is 64ms.
O
PERATING
C
URRENT
C
HARACTERISTICS
(V
CC
= 3.6V)
5
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
White Electronic Designs
WED3DL328V
Burst Starting Column Order of Accesses Within a Burst
Length
Address
A0
2
0
0-1
0-1
1
1-0
1-0
A1A0
0
0
0-1-2-3
0-1-2-3
4
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
2-3-0-1
1
1
3-0-1-2
3-2-1-0
A2
A1A0
0
0
0
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7
0
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
8
0
1
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
0
4-5-6-7-0-1-2-3
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1
1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
Full
n = A0-A11/9/8 Cn, Cn + 1, Cn + 2
Page
Cn + 3, Cn + 4...
Not Supported
(y)
(location 0-y)
...Cn - 1,
Cn...
Type = Sequential
Type = Interleaved
NOTES:
1. For full-page accesses: y = 2,048 (x4), y = 1,024 (x8), y = 512
(x16).
2. For a burst length of two, A1-A9, A11 (x4), A1-A9 (x8) or A1-A8
(x16) select the block-of-two burst; A0 selects the starting column
within the block.
3. For a burst length of four, A2-A9, A11 (x4), A2-A9 (x8) or A2-A8
(x16) select the block-of-four burst; A0-A1 select the starting column
within the block.
4. For a burst length of eight, A3-A9, A11 (x4), A3-A9 (x8) or A3-A8
(x16) select the block-of-eight burst; A0-A2 select the starting
column within the block.
5. For a full-page burst, the full row is selected and A0-A9, A11 (x4),
A0-A9 (x8) or A0-A8 (x16) select the starting column.
6. Whenever a boundary of the block is reached within a given
sequence above, the following access wraps within the block.
7. For a burst length of one, A0-A9, A11 (x4), A0-A9 (x8) or A0-A8
(x16) select the unique column to be accessed, and mode register
bit M3 is ignored.
B
URST
D
EFINITION
MODE REGISTER DEFINITION
M3 = 0
1
2
4
8
Reserved
Reserved
Reserved
Full Page
M3 = 1
1
2
4
8
Reserved
Reserved
Reserved
Reserved
Operating Mode
Standard Operation
All other states reserved
0
-
0
-
Defined
-
0
1
Burst Type
Sequential
Interleaved
CAS Latency
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
Burst Length
M0
0
1
0
1
0
1
0
1
Burst Length
CAS Latency
BT
A
9
A
7
A
6
A
5
A
4
A
3
A
8
A
2
A
1
A
0
Mode Register (Mx)
Address Bus
M1
0
0
1
1
0
0
1
1
M2
0
0
0
0
1
1
1
1
M3
M4
0
1
0
1
0
1
0
1
M5
0
0
1
1
0
0
1
1
M6
0
0
0
0
1
1
1
1
M6-M0
M8
M7
Op Mode
A
10
A
11
Reserved* WB
0
1
Write Burst Mode
Programmed Burst Length
Single Location Access
M9
*Should program
M11, M10 = "0, 0"
to ensure compatibility
with future devices.
6
White Electronic Designs Corporation Westborough, MA (508) 366-5151
White Electronic Designs
WED3DL328V
Symbol
133MHz
125MHz
100MHz
Parameter
Min
Max
Min
Max
Min
Max
Units
Clock Cycle Time (1)
CL = 3
t
CC
7
1000
8
1000
10
1000
ns
CL = 2
t
CC
7.5
1000
10
1000
12
1000
Clock to valid Output delay (1,2)
t
SAC
5.4
6
7
ns
Output Data Hold Time (2)
t
OH
3
3
3
ns
Clock HIGH Pulse Width (3)
t
CH
2.5
3
3
ns
Clock LOW Pulse Width (3)
t
CL
3
3
3
ns
Input Setup Time (3)
t
S S
2
2
2
ns
Input Hold Time (3)
t
SH
1
1
1
ns
CLK to Output Low-Z (2)
t
SLZ
1.0
1.0
1.0
ns
CLK to Output High-Z
t
SHZ
7
7
8
ns
Row Active to Row Active Delay (4)
t
RRD
15
20
20
ns
RAS to CAS Delay (4)
t
RCD
15
20
20
ns
Row Precharge Time (4)
t
RP
20
20
24
ns
Row Active Time (4)
t
RAS
50
120,000
50
120,000
60
120,000
ns
Row Cycle Time - Operation (4)
t
RC
60
70
80
ns
Row Cycle Time - Auto Refresh (4,8)
t
RFC
70
70
80
ns
Last Data in to New Column Address Delay (5)
t
CDL
1
1
1
CLK
Last Data in to Row Precharge (5)
t
RDL
1
1
1
CLK
Last Data in to Burst Stop (5)
t
BDL
1
1
1
CLK
Column Address to Column Address Delay (6)
t
CCD
1.5
1.5
1.5
CLK
Number of Valid OutputData (7)
2
2
2
1
2
1
ea
NOTES:
1. Parameters depend on programmed CAS latency.
2. If clock rise time is longer than 1ns (t
rise
/2 -0.5)ns should be added to the parameter.
3. Assumed input rise and fall time = 1ns. If trise of tfall are longer than 1ns. [(t
rise
= t
fall
)/2] - 1ns should be added to the parameter.
4. The minimum number of clock cycles required is detemined by dividing the minimum time required by the clock cycle time and then
rounding up to the next higher integer.
5. Minimum delay is required to complete write.
6. All devices allow every cycle column address changes.
7. In case of row precharge interrupt, auto precharge and read burst stop.
8. A new command may be given t
RFC
after self-refresh exit.
SDRAM AC C
HARACTERISTICS
7
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
White Electronic Designs
WED3DL328V
CKE
CE
RAS
CAS
WE
DQM
BA
A
10
/AP
A
11
Notes
Function
Previous Current
A
9-0
Cycle
Cycle
Register
Mode Register Set
H
X
L
L
L
L
X
OP CODE
Refresh
Auto Refresh (CBR)
H
H
L
L
L
H
X
X
X
X
Entry Self Refresh
H
L
L
L
L
H
X
X
X
X
Precharge
Single Bank Precharge
H
X
L
L
H
L
X
BA
L
X
2
Precharge all Banks
H
X
L
L
H
L
X
X
H
X
Bank Activate
H
X
L
L
H
H
X
BA Row Address
2
Write
H
X
L
H
L
L
X
BA
L
Column
2
Write with Auto Precharge
H
X
L
H
L
L
X
BA
H
Column
2
Read
H
X
L
H
L
L
X
BA
L
Column
2
Read with Auto Precharge
H
X
L
H
L
H
X
BA
H
Column
2
Burst Termination
H
X
L
H
H
L
X
X
X
X
3
No Operation
H
X
L
H
H
H
X
X
X
X
Device Deselect
H
X
H
X
X
X
X
X
X
X
Clock Suspend/Standby Mode
L
X
X
X
X
X
X
X
X
X
4
Data Write/Output Disable
H
X
X
X
X
X
L
X
X
X
5
Data Mask/Output Disable
H
X
X
X
X
X
H
X
X
X
5
Power Down Mode Entry
X
L
H
X
X
X
X
X
X
X
6
Exit
X
H
H
X
X
X
X
X
X
X
6
C
OMMAND
T
RUTH
T
ABLE
NOTES:
1.All of the SDRAM operations are defined by states of CE, WE, RAS, CAS, and DQM at the positive rising edge of the clock.
2.Bank Select (BA), if BA = 0 then bank A is selected, if BA = 1 then bank B is selected.
3.During a Burst Write cycle there is a zero clock delay, for a Burst Read cycle the delay is equal to the CAS latency.
4.During normal access mode, CKE is held high and CLK is enabled. When it is low, it freezes the internal clock and extends data Read and
Write operations. One clock delay is required for mode entry and exit.
5.The DQM has two functions for the data DQ Read and Write operations. During a Read cycle, when DQM goes high at a clock timing the
data outputs are disabled and become high impedance after a two clock delay. DQM also provides a data mask function for Write cycles.
When it activates, the Write operation at the clock is prohibited (zero clock latency).
All banks must be precharged before entering the Power Down Mode. The Power Down Mode does not preform any Refresh operations,
therefore the device cant remain in this mode longer than the Refresh period (t
REF
) of the device. One clock delay is required for mode
entry and exit.
8
White Electronic Designs Corporation Westborough, MA (508) 366-5151
White Electronic Designs
WED3DL328V
Current State
CKE
Command
Action
Notes
Previous Current
CE
RAS
CAS
WE
BA
0-1
A
10-11
Cycle
Cycle
H
X
X
X
X
X
X
X
INVALID
1
L
H
H
X
X
X
X
X
Exit Self Refresh with Device Deselect
2
L
H
L
H
H
H
X
X
Exit Self Refresh with No Operation
2
Self Refresh
L
H
L
H
H
L
X
X
ILLEGAL
2
L
H
L
H
L
X
X
X
ILLEGAL
2
L
H
L
L
X
X
X
X
ILLEGAL
2
L
L
X
X
X
X
X
X
Maintain Self Refresh
H
X
X
X
X
X
X
X
INVALID
1
Power Down
L
H
H
X
X
X
X
X
Power Down Mode exit, all banks idle
2
L
H
L
X
X
X
X
X
ILLEGAL
2
H
X
L
H
L
L
X
Maintain Power Down Mode
2
H
H
H
X
X
X
H
H
L
H
X
X
Refer to the Idle State section of the
3
H
H
L
L
H
X
Current State Truth Table
H
H
L
L
L
H
X
X
CBR Refresh
H
H
L
L
L
L OP Code
Mode Register Set
4
All Banks Idle
H
L
H
X
X
X
Refer to the Idle State section of the
H
L
L
H
X
X
3
H
L
L
L
H
X
Current State Truth Table
H
L
L
L
L
H
X
X
Entry Self Refresh
4
H
H
L
L
L
L OP Code
Mode Register Set
L
X
X
X
X
X
X
X
Power Down
4
H
H
X
X
X
X
X
X
Refer to the Operations in the Current
State Truth Table
Any State other
H
L
X
X
X
X
X
X
Begin Clock Suspend next cycle
5
than listed above
L
H
X
X
X
X
X
X
Exit Clock Suspend next cycle
L
L
X
X
X
X
X
X
Maintain Clock Suspend
NOTES:
1.For the given Current State CKE must be low in the previous cycle.
2.When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. The minimum setup time for CKE (t
CKS
)
must be satisfied before any command other than Exit is issued.
3.The address inputs (A
11-0
) depend on the command that is issued. See the Idle State section of the Current State Truth Table for more
information.
4.The Power Down Mode, Self Refresh Mode, and the Mode Register Set can only be entered from the all banks idle state.
Must be a legal command as defined in the Current State Truth Table.
C
LOCK
E
NABLE
(CKE) T
RUTH
T
ABLE
9
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White Electronic Designs
WED3DL328V
C
URRENT
S
TATE
T
RUTH
T
ABLE
Current State
Command
Action
Notes
CE
RAS CAS WE BA0-1
A
11
,
Description
A
10
/AP-A
0
L
L
L
L OP Code
Mode Register Set
Set the Mode Register
2
L
L
L
H
X
X
Auto orSelf Refresh
Start Auto orSelf Refresh
2,3
L
L
H
L
X
X
Precharge
No Operation
L
L
H
H
BA
Row Address
Bank Activate
Activate the specified bank and row
Idle
L
H
L
L
BA
Column
Write w/o Precharge
ILLEGAL
4
L
H
L
H
BA
Column
Read w/o Precharge
ILLEGAL
2
L
H
H
L
X
X
Burst Termination
No Operation
2
L
H
H
H
X
X
No Operation
No Operation
H
X
X
X
X
X
Device Deselect
No Operation or Power Down
5
L
L
L
L OP Code
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto orSelf Refresh
ILLEGAL
L
L
H
L
X
X
Precharge
Precharge
6
L
L
H
H
BA
Row Address
Bank Activate
ILLEGAL
2
Row Active
L
H
L
L
BA
Column
Write
Start Write; Determine if Auto Precharge
7,8
L
H
L
H
BA
Column
Read
Start Read; Determine if Auto Precharge
7,8
L
H
H
L
X
X
Burst Termination
No Operation
L
H
H
H
X
X
No Operation
No Operation
H
X
X
X
X
X
Device Deselect
No Operation
L
L
L
L OP Code
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto orSelf Refresh
ILLEGAL
L
L
H
L
X
X
Precharge
Terminate Burst; Start the Precharge
L
L
H
H
BA
Row Address
Bank Activate
ILLEGAL
4
Read
L
H
L
L
BA
Column
Write
Terminate Burst; Start the Write cycle
8,9
L
H
L
H
BA
Column
Read
Terminate Burst; Start a new Read cycle
8,9
L
H
H
L
X
X
Burst Termination
Terminate the Burst
L
H
H
H
X
X
No Operation
Continue the Burst
H
X
X
X
X
X
Device Deselect
Continue the Burst
L
L
L
L OP Code
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto orSelf Refresh
ILLEGAL
L
L
H
L
X
X
Precharge
Terminate Burst; Start the Precharge
L
L
H
H
BA
Row Address
Bank Activate
ILLEGAL
4
Write
L
H
L
L
BA
Column
Write
Terminate Burst; Start a new Write cycle
8,9
L
H
L
H
BA
Column
Read
Terminate Burst; Start the Read cycle
8,9
L
H
H
L
X
X
Burst Termination
Terminate the Burst
L
H
H
H
X
X
No Operation
Continue the Burst
H
X
X
X
X
X
Device Deselect
Continue the Burst
L
L
L
L OP Code
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto orSelf Refresh
ILLEGAL
L
L
H
L
X
X
Precharge
ILLEGAL
4
Read with
L
L
H
H
BA
Row Address
Bank Activate
ILLEGAL
4
Auto Precharge
L
H
L
L
BA
Column
Write
ILLEGAL
L
H
L
H
BA
Column
Read
ILLEGAL
L
H
H
L
X
X
Burst Termination
ILLEGAL
L
H
H
H
X
X
No Operation
Continue the Burst
H
X
X
X
X
X
Device Deselect
Continue the Burst
10
White Electronic Designs Corporation Westborough, MA (508) 366-5151
White Electronic Designs
WED3DL328V
Current State
Command
Action
Notes
CE RAS CAS WE BA
0-1
A
11
,
Description
A
10
/AP-A
0
L
L
L
L OP Code
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto orSelf Refresh
ILLEGAL
L
L
H
L
X
X
Precharge
ILLEGAL
4
Write with
L
L
H
H
BA
Row Address
Bank Activate
ILLEGAL
4
Auto Precharge
L
H
L
L
BA
Column
Write
ILLEGAL
L
H
L
H
BA
Column
Read
ILLEGAL
L
H
H
L
X
X
Burst Termination
ILLEGAL
L
H
H
H
X
X
No Operation
Continue the Burst
H
X
X
X
X
X
Device Deselect
Continue the Burst
L
L
L
L OP Code
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto orSelf Refresh
ILLEGAL
L
L
H
L
X
X
Precharge
No Operation; Bank(s) idle after t
RP
L
L
H
H
BA
Row Address
Bank Activate
ILLEGAL
4
Precharging
L
H
L
L
BA
Column
Write w/o Precharge
ILLEGAL
4
L
H
L
H
BA
Column
Read w/o Precharge
ILLEGAL
4
L
H
H
L
X
X
Burst Termination
No Operation; Bank(s) idle after t
RP
L
H
H
H
X
X
No Operation
No Operation; Bank(s) idle after t
RP
H
X
X
X
X
X
Device Deselect
No Operation; Bank(s) idle after t
RP
L
L
L
L OP Code
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto orSelf Refresh
ILLEGAL
L
L
H
L
X
X
Precharge
ILLEGAL
4
L
L
H
H
BA
Row Address
Bank Activate
ILLEGAL
4,10
Row Activating
L
H
L
L
BA
Column
Write
ILLEGAL
4
L
H
L
H
BA
Column
Read
ILLEGAL
4
L
H
H
L
X
X
Burst Termination
No Operation; Row active after t
RCD
L
H
H
H
X
X
No Operation
No Operation; Row active after t
RCD
H
X
X
X
X
X
Device Deselect
No Operation; Row active after t
RCD
L
L
L
L OP Code
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto orSelf Refresh
ILLEGAL
L
L
H
L
X
X
Precharge
ILLEGAL
4
L
L
H
H
BA
Row Address
Bank Activate
ILLEGAL
4
Write Recovering
L
H
L
L
BA
Column
Write
Start Write; Determine if Auto Precharge
9
L
H
L
H
BA
Column
Read
Start Read; Determine if Auto Precharge
9
L
H
H
L
X
X
Burst Termination
No Operation; Row active after t
DPL
L
H
H
H
X
X
No Operation
No Operation; Row active after t
DPL
H
X
X
X
X
X
Device Deselect
No Operation; Row active after t
DPL
L
L
L
L OP Code
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto orSelf Refresh
ILLEGAL
L
L
H
L
X
X
Precharge
ILLEGAL
4
Write Recovering
L
L
H
H
BA
Row Address
Bank Activate
ILLEGAL
4
with Auto
L
H
L
L
BA
Column
Write
ILLEGAL
4,9
Precharge
L
H
L
H
BA
Column
Read
ILLEGAL
4,9
L
H
H
L
X
X
Burst Termination
No Operation; Precharge after t
DPL
L
H
H
H
X
X
No Operation
No Operation; Precharge after t
DPL
H
X
X
X
X
X
Device Deselect
No Operation; Precharge after t
DPL
C
URRENT
S
TATE
T
RUTH
T
ABLE
(
CONT
.)
11
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
White Electronic Designs
WED3DL328V
NOTES:
1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the command is being
applied to.
2. Both Banks must be idle otherwise it is an illegal action.
3. If CKE is active (high) the SDRAM starts the Auto (CBR) Refresh operation, if CKE is inactive (low) then the Self Refresh mode is entered.
4. The Current State only refers to one of the banks, if BA selects this bank then the action is illegal. If BA selects the bank not being
referenced by the Current Sate then the action may be legal depending on the state of that bank.
5. If CKE is inactive (low) then the Power Down mode is entered, otherwise there is a No Operation.
6. The minimum and maximum Active time (t
RAS
) must be satisfied.
7. The RAS to CAS Delay (t
RCD
) must occur before the command is given.
8. Address A10 is used to determine if the Auto Precharge function is activated.
9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.
The command is illegal if the minimum bank to bank delay time (t
RRD
) is not satified.
Current State
Command
Action
Notes
CE
RAS
CAS
WE
BA
0-1
A
11
,
Description
A
10
/AP-A
0
L
L
L
L OP Code
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto orSelf Refresh
ILLEGAL
L
L
H
L
X
X
Precharge
ILLEGAL
L
L
H
H
BA Row Address
Bank Activate
ILLEGAL
Refreshing
L
H
L
L
BA
Column
Write
ILLEGAL
L
H
L
H
BA
Column
Read
ILLEGAL
L
H
H
L
X
X
Burst Termination
No Operation; Idle after tRC
L
H
H
H
X
X
No Operation
No Operation; Idle after tRC
H
X
X
X
X
X
Device Deselect
No Operation; Idle after tRC
L
L
L
L OP Code
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto orSelf Refresh
ILLEGAL
L
L
H
L
X
X
Precharge
ILLEGAL
Mode Register
L
L
H
H
BA Row Address
Bank Activate
ILLEGAL
Accessing
L
H
L
L
BA
Column
Write
ILLEGAL
L
H
L
H
BA
Column
Read
ILLEGAL
L
H
H
L
X
X
Burst Termination
ILLEGAL
L
H
H
H
X
X
No Operation
No Operation; Idle after two clock cycles
H
X
X
X
X
X
Device Deselect
No Operation; Idle after two clock cycles
C
URRENT
S
TATE
T
RUTH
T
ABLE
(
CONT
.)
12
White Electronic Designs Corporation Westborough, MA (508) 366-5151
White Electronic Designs
WED3DL328V
FIG. 3 SINGLE BIT READ-WRITE CYCLE (SAME PAGE) @CAS
LATENCY=3, BURST LENGTH=1
3. Enable and disable auto precharge function are controlled by A
10
/AP in
read/write command.
4. A
10
/AP and BA
0
~BA
1
control bank precharge when
precharge command is asserted.
BA0 BA1
Active & Read/Write
0
0
Bank A
0
1
Bank B
1
0
Bank C
1
1
Bank D
NOTES:
1. All input except CKE & DQM can be don't care when CE
is high at the CLK high going edge.
2. Bank active & read/write are controlled by BA0~BA1.
A10/AP BA0
BA1
Precharge
0
0
0
Bank A
0
0
1
Bank B
0
1
0
Bank C
0
1
1
Bank D
1
x
x
All Banks
BA
0
BA
1
Operation
0
0 Distribute auto precharge, leave bank A active at end of burst.
0
1
Disable auto precharge, leave bank B active at end of burst.
1
0
Disable auto precharge, leave bank C active at end of burst.
1
1
Disable auto precharge, leave bank D active at end of burst.
0
0
Enable auto precharge, precharge bank A at end of burst.
0
1
Enable auto precharge, precharge bank B at end of burst.
1
0
Enable auto precharge, precharge bank C at end of burst.
1
1
Enable auto precharge, precharge bank D at end of burst.
A
10
/AP
0
1
RAS
CAS
ADDR
BA
DQM
t
SS
t
SH
A
10
/AP
CKE
CLOCK
CE
Cb
Cc
Rb
Ca
Ra
t
SH
DQ
Row Active
Precharge
Read
Write
Read
Row Active
Db
Qc
WE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
HIGH
t
SS
t
SH
t
RCD
t
RP
t
RAS
t
RCD
t
SS
t
SH
t
SS
BS
BS
BS
BS
BS
Note 3
Note 3
Note 4
Rb
Note 3
Note 2, 3
Note 2, 3
Note 2
Note 4
Note 2, 3
Ra
BS
Qa
t
SH
t
SS
t
OH
t
SAC
t
SLZ
t
SS
t
SH
t
SS
t
SH
t
RAC
t
SS
t
SH
t
CCD
t
CH
t
CL
t
CC
DON'T CARE
Note 2
13
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
White Electronic Designs
WED3DL328V
FIG. 4 POWER UP SEQUENCE
RAS
CAS
ADDR
BA
DQM
A
10
/AP
CKE
CLOCK
CE
Key
RAa
DQ
Mode Register Set
Row Active
(A-Bank)
Auto Refresh
Auto Refresh
Precharge
(All Banks)
WE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
t
RP
RAa
HIGH-Z
t
RFC
t
RFC
High level is necessary
High level is necessary
DON'T CARE
14
White Electronic Designs Corporation Westborough, MA (508) 366-5151
White Electronic Designs
WED3DL328V
FIG. 5 READ & WRITE CYCLE AT SAME BANK @BURST LENGTH=4
NOTES:
1. Minimum row cycle times are required to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. (CAS Latency - 1) number of valid output
data is available after Row precharge. Last valid output will be Hi-Z(t
SHZ
) after the clock.
3. Access time from Row active command. t
CC
*(t
RCD
+ CAS latency - 1) + t
SAC
.
4. Output will be Hi-Z after the end of burst (1, 2, 4, 8 & full page bit burst).
RAS
CAS
ADDR
BA
DQM
A
10
/AP
CKE
CLOCK
CE
Rb
Cb0
Ca0
Ra
CL = 2
DQ
Row Active
(A-Bank)
Write
(A-Bank)
Precharge
(A-Bank)
Precharge
(A-Bank)
Read
(A-Bank)
Row Active
(A-Bank)
WE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
HIGH
t
RCD
t
RC
Rb
Note 1
Ra
Qa0
t
SHZ
t
SHZ
t
RDL
t
RDL
t
RAC
t
RAC
Qa1
Qa2
Qa3
Db0
Db1
Db2
Db3
CL = 3
Qa0
Qa1
Qa2
Qa3
Db0
Db1
Db2
Db3
t
SAC
t
SAC
t
OH
t
OH
Note 3
Note 4
Note 4
Note 3
DON'T CARE
Note 2
15
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
White Electronic Designs
WED3DL328V
FIG. 6 PAGE READ & WRITE CYCLE AT SAME BANK @BURST LENGTH=4
NOTES:
1. To write data before burst read ends, DQM should be asserted three cycles prior to
write command to avoid bus contention.
2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written.
3. DQM should mask invalid input data on precharge command cycle when asserting precharge
before end of burst. Input data after Row precharge cycle will be masked internally.
RAS
CAS
ADDR
BA
DQM
A
10
/AP
CKE
CLOCK
CE
Cc0
Cd0
Ca0
Ra
CL = 2
DQ
Write
(A-Bank)
Write
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Read
(A-Bank)
Row Active
(A-Bank)
WE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
HIGH
t
RCD
Ra
Qa0
t
RDL
t
CDL
Qa1
Qb0
Qb1
Qb2
Dc0
Dc1
Dd0
Dd1
CL = 3
Qa0
Qa1
Qb0
Qb1
Dc0
Dc1
Dd0
Dd1
DON'T CARE
Cb0
Note 2
Note 3
Note 1
16
White Electronic Designs Corporation Westborough, MA (508) 366-5151
White Electronic Designs
WED3DL328V
FIG. 7 PAGE READ CYCLE AT DIFFERENT BANK @BURST LENGTH=4
NOTES:
1. CE can be don't cared when RAS, CAS and WE are high at the clock high going edge.
2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
RAS
CAS
ADDR
BA
DQM
A
10
/AP
CKE
CLOCK
CE
CAc
CBd
CAe
RBb
CAa
RAa
CL = 2
DQ
Read
(A-Bank)
Read
(A-Bank)
Read
(B-Bank)
Row Active
(B-Bank)
Read
(B-Bank)
Precharge
(A-Bank)
Read
(A-Bank)
Row Active
(A-Bank)
WE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
HIGH
RAa
QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0
QAe1
CL = 3
QAa2 QAa3
QAa0 QAa1
QAa0 QAa1
QBb0 QBb1
QBb3
QBb2
QAc0 QAc1 QBd0 QBd1 QAe0
QAe1
DON'T CARE
CBb
Note 2
Note 1
RBb
17
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
White Electronic Designs
WED3DL328V
FIG. 8 PAGE WRITE CYCLE AT DIFFERENT BANK @BURST LENGTH=4
NOTES:
1. To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data.
2. To interrupt burst write by Row precharge, both the write and the precharge banks must be the same.
RAS
CAS
ADDR
BA
DQM
A
10
/AP
CKE
CLOCK
CE
CAc
CBd
RBb
CAa
RAa
DQ
Write
(A-Bank)
Write
(B-Bank)
Row Active
(B-Bank)
Write
(B-Bank)
Precharge
(Both Banks)
Write
(A-Bank)
Row Active
(A-Bank)
WE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
HIGH
RAa
DAa3 DBb0
DBb1 DBb2 DBb3 DAc0
DAc1 DBd0 DBd1
DAa1
DAa0
DAa2
DON'T CARE
CBb
Note 2
Note 1
RBb
t
RDL
t
CDL
18
White Electronic Designs Corporation Westborough, MA (508) 366-5151
White Electronic Designs
WED3DL328V
FIG. 9 READ & WRITE CYCLE AT DIFFERENT BANK @BURST LENGTH=4
NOTE:
1. t
CDL
should be met to complete write.
RAS
CAS
ADDR
BA
DQM
A
10
/AP
CKE
CLOCK
CE
RAc
CAc
CAa
RBb
RAa
CL = 2
Read
(A-Bank)
Row Active
(A-Bank)
Read
(A-Bank)
Write
(B-Bank)
Precharge
(A-Bank)
Row Active
(B-Bank)
Row Active
(A-Bank)
WE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
HIGH
RAa
QAa3
DBb0 DBb1 DBb2 DBb3
QAc0 QAc1
QAa1
QAa0
QAa2
DON'T CARE
CBb
Note 1
RAc
RBb
t
CDL
QAc2
CL = 3
DQ
QAa3
DBb0 DBb1 DBb2 DBb3
QAc0 QAc1
QAa1
QAa0
QAa2
19
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WED3DL328V
FIG. 10 READ & WRITE CYCLE WITH AUTO PRECHARGE @BURST
LENGTH=4
NOTE:
1. t
CDL
should be controlled to meet minimum t
RAS
before internal precharge start.
(in the case of Burst Length=1 & 2 and BRSW mode)
RAS
CAS
ADDR
BA
DQM
A
10
/AP
CKE
CLOCK
CE
Cb
Ca
Rb
Ra
CL = 2
Auto Precharge
Start Point
(B-Bank)
Auto Precharge
Start Point
(A-Bank)
Write with
Auto Precharge
(B-Bank)
Read with
Auto Precharge
(A-Bank)
Row Active
(B-Bank)
Row Active
(A-Bank)
WE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
HIGH
Ra
Qa3
Db0
Db1
Db2
Db3
Qa1
Qa0
Qa2
DON'T CARE
Rb
CL = 3
DQ
Qa3
Db0
Db1
Db2
Db3
Qa1
Qa0
Qa2
20
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FIG. 11 CLOCK SUSPENSION & DQM OPERATION CYCLE @CAS
LATENCY=2, BURST LENGTH=4
NOTE:
1. DQM is needed to prevent bus contention.
RAS
CAS
ADDR
BA
DQM
A
10
/AP
CKE
CLOCK
CE
Cb
Cc
Ca
DQ
Read
Read DQM
Write
Write
DQM
Write
DQM
Clock
Suspension
Clock
Suspension
Read
Row Active
WE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Ra
Qa0
t
SHZ
t
SHZ
Qa1
Qa2
Qa3
Dc0
Dc2
DON'T CARE
Qb1
Qb1
Ra
Note 1
21
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WED3DL328V
FIG. 12 READ INTERRUPTED BY PRECHARGE COMMAND & READ
BURST STOP @BURST LENGTH=FULL PAGE
NOTES:
1. At full page mode, burst is end at the end of burst. So auto precharge is possible.
2. About the valid DQs after burst stop, it is same as the case of RAS interrupt.
Both cases are illustrated in above timing diagram. See the label 1, 2.
But at burst write, Burst stop and RAS interrupt should be compared carefully.
Refer to the timing diagram of "Full page write burst stop cycle."
3. Burst stop is valid at every burst length.
RAS
CAS
ADDR
BA
DQM
A
10
/AP
CKE
CLOCK
CE
CAb
CAa
RAa
CL = 2
Precharge
(A-Bank)
Read
(A-Bank)
Burst Stop
Read
(A-Bank)
Row Active
(A-Bank)
WE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
HIGH
DON'T CARE
RAa
QAa0 QAa1 QAa2 QAa3 QAa4
QAb1
QAb0
QAb3
QAb2
QAb5
QAb4
CL = 3
DQ
QAa0 QAa1 QAa2 QAa3 QAa4
QAb1
QAb0
QAb3
QAb2
QAb5
QAb4
Note 3
1
1
2
2
22
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FIG. 13 WRITE INTERRUPTED BY PRECHARGE COMMAND &
WRITE BURST STOP CYCLE @BURST LENGTH=FULL PAGE
NOTES:
1. At full page mode, burst is end at the end of burst. So auto precharge is possible.
2. Data-in at the cycle of interrupted by precharge cannot be written into the corresponding
memory cell. It is defined by AC parameter of t
RDL
.
DQM at write interrupted by precharge command is needed to prevent invalid write.
DQM should mask invalid input data on precharge command cycle when asserting
precharge before end of burst. Input data after Row precharge cycle will be masked internally.
3. Burst stop is valid at every burst length.
RAS
CAS
ADDR
BA
DQM
A
10
/AP
CKE
CLOCK
CE
CAb
CAa
RAa
DQ
Precharge
(A-Bank)
Write
(A-Bank)
Burst Stop
Write
(A-Bank)
Row Active
(A-Bank)
WE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
HIGH
DON'T CARE
RAa
DAa0 DAa1 DAa2 DAa3 DAa4
DAb1
DAb0
DAb3
DAb2
DAb5
DAb4
Note 2
t
RDL
t
BDL
23
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FIG. 14 BURST READ SINGLE BIT WRITE CYCLE @BURST LENGTH=2
NOTES:
1. BRSW mode is enabled by setting As "High" at MRS (Mode Register Set). At the
BRSW Mode, the burst length at write is fixed to "1" regardless of programmed burst length.
2. When BRSW write command with auto precharge is executed, keep it in mind that t
RAS
should not be violated. Auto precharge is executed at the burst-end cycle, so in the case
of BRSW write command, the next cycle starts the precharge.
RAS
CAS
ADDR
BA
DQM
A
10
/AP
CKE
CLOCK
CE
CBc
CAd
RBb
CAa
RAa
CL = 2
Row Active
(A-Bank)
Read
(A-Bank)
Row Active
(B-Bank)
Write with
Auto Precharge
(B-Bank)
Precharge
(Both Banks)
Write
(A-Bank)
Read with
Auto Precharge
(A-Bank)
Row Active
(A-Bank)
WE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
HIGH
RAa
QAb0 QAb1
DBc0
QAd0 QAd1
DAa0
DON'T CARE
CAb
Note 2
RBb
RAc
RAc
CL = 3
DQ
QAb0 QAb1
DBc0
QAd0 QAd1
DAa0
Note 1
24
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FIG. 15 ACTIVE/PRECHARGE POWER DOWN MODE @CAS
LATENCY=2, BURST LENGTH=4
NOTES:
1. Both banks should be in idle state prior to entering precharge power down mode.
2. CKE should be set high at least 1 CLK + t
SS
prior to Row active command.
3. Cannot violate minimum refresh specification (64ms).
RAS
CAS
ADDR
BA
DQM
A
10
/AP
CKE
CLOCK
CE
Ra
Ca
DQ
Precharge
Read
Row Active
Precharge
Power-Down
Entry
Precharge
Power-Down
Exit
Active
Power-Down
Entry
Active
Power-Down
Exit
WE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Note 3
Note 2
t
SS
DON'T CARE
t
SS
t
SS
t
SHZ
Note 1
Ra
Qa1
Qa0
Qa2
25
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FIG. 16 SELF REFRESH ENTRY & EXIT CYCLE
NOTES:
TO ENTER SELF REFRESH MODE
1. CE, RAS & CAS with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE.
3. The device remains in self refresh mode as long as CKE stays "Low."
Once the device enters self refresh mode, minimum t
RAS
is required before exit from self refresh.
TO EXIT SELF REFRESH MODE
4. System clock restart and be stable before returning CKE high.
5. CE starts from high.
6. Minimum t
RFC
is required after CKE going high to complete self refresh exit.
7. 4K cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst refresh.
RAS
CAS
ADDR
BA
DQM
A
10
/AP
CKE
CLOCK
CE
DQ
Auto Refresh
Self Refresh Entry
Self Refresh Exit
WE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
t
SS
DON'T CARE
Note 1
Note 3
Note 4
t
RFC
min
Note 6
Note 5
Note 7
HI-Z
HI-Z
Note 2
26
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WED3DL328V
FIG. 18 AUTO REFRESH CYCLE
FIG. 17 MODE REGISTER
SET CYCLE
NOTES:
Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.
MODE REGISTER SET CYCLE
1. CE, RAS, CAS, & WE activation at the same clock cycle with address key will set internal mode register.
2. Minimum 2 clock cycles should be met before new RAS activation.
3. Please refer to Mode Register Set table.
RAS
CAS
ADDR
DQM
CKE
CLOCK
CE
Ra
Key
DQ
New Command
New
Command
Auto Refresh
MRS
WE
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
9
10
DON'T CARE
t
RFC
HI-Z
HI-Z
Note 2
Note 1
Note 3
HIGH
HIGH
27
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PACKAGE DESCRIPTION 119 PIN BGA
JEDEC MO-163
ALL DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
O
RDERING
I
NFORMATION
Part Number
Clock Frequency
Package
Operating Range
WED3DL328V7BC
133MHz
119 BGA
Commercial
WED3DL328V8BC
125MHz
119 BGA
Commercial
WED3DL328V10BC
100MHz
119 BGA
Commercial
WED3DL328V7BI
133MHz
119 BGA
Industrial
WED3DL328V8BI
125MHz
119 BGA
Industrial
WED3DL328V10BI
100MHz
119 BGA
Industrial
2.79 (0.110)
MAX
0.711 (0.028)
MAX
1.27 (0.050)
TYP
1.27 (0.050) TYP
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
14.00 (0.551) TYP
A1
CORNER
20.32 (0.800)
TYP
22.00 (0.866)
TYP
7.62 (0.300)
TYP
R 1.52 (0.060)
MAX (4x)
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