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Электронный компонент: WED3DG644V100D1-M

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WED3DG644V-D1
White Electronic Designs
1
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
June 2006
Rev. 3
Pin
Front
Pin
Back
Pin
Front
Pin
Back
Pin
Back
Pin
Back
1
V
SS
2
V
SS
51
DQ14
52
DQ46
95
DQ21
96
DQ53
3
DQ0
4
DQ32
53
DQ15
54
DQ47
97
DQ22
98
DQ54
5
DQ1
6
DQ33
55
V
SS
56
V
SSv
99
DQ23 100 DQ55
7
DQ2
8
DQ34
57
NC
58
NC
101
V
CC
102
V
CC
9
DQ3
10
DQ35
59
NC
60
NC
103
A6
104
A7
11
V
CC
12
V
CC
VOLTAGE KEY
105
A8
106
BA0
13
DQ4
14
DQ36
107
V
SS
108
V
SS
15
DQ5
16
DQ37
109
A9
110
BA1
17
DQ6
18
DQ38
61
CLK0
62
CKE0 111 A10/AP 112
A11
19
DQ7
20
DQ39
63
V
CC
64
V
CC
113
V
CC
114
V
CC
21
V
SS
22
V
SS
65
RAS#
66
CAS# 115 DQM2 116 DQM6
23 DQM0 24 DQM4 67
WE#
68 *CKE1 117 DQM3 118 DQM7
25 DQM1 26 DQM5 69
CS0#
70
*A12
119
V
SS
120
VSS
27
V
CC
28
V
CC
71 *CS1# 72
*A13
121 DQ24 122 DQ56
29
A0
30
A3
73
DNU
74
*CK1 123 DQ25 124 DQ57
31
A1
32
A4
75
V
SS
76
V
SS
125 DQ26 126 DQ58
33
A2
34
A5
77
NC
78
NC
127 DQ27 128 DQ59
35
V
SS
36
V
SS
79
NC
80
NC
129
V
CC
130
V
CC
37
DQ8
38
DQ40
81
V
CC
82
V
CC
131 DQ28 132 DQ60
39
DQ9
40
DQ41
83
DQ16
84
DQ48 133 DQ29 134 DQ61
41
DQ10
42
DQ42
85
DQ17
86
DQ49 135 DQ30 136 DQ62
43
DQ11
44
DQ43
87
DQ18
88
DQ50 137 DQ31 138 DQ63
45
V
CC
46
V
CC
89
DQ19
90
DQ51 139
V
SS
140
V
SS
47
DQ12
48
DQ44
91
V
SS
92
V
SS
141 **SDA 142 **SCL
49
DQ13
50
DQ45
93
DQ20
94
DQ52 143
V
CC
144
V
CC
32MB 4Mx64 SDRAM, UNBUFFERED
DESCRIPTION
The WED3DG644V is a 4Mx64 synchronous DRAM
module which consists of four 4Mx16 SDRAM components
in TSOP II package, and one 2Kb EEPROM in an 8
pin TSOP package for Serial Presence Detect which
are mounted on a 144 pin SO-DIMM multilayer FR4
Substrate.
* This product is subject to change without notice.
NOTE: Consult factory for availability of:
RoHS compliant products
Vendor source control options
Industrial temperature option
FEATURES
PC100 and PC133 compatible
Burst Mode Operation
Auto and Self Refresh capability
LVTTL compatible inputs and outputs
Serial Presence Detect with EEPROM
Fully synchronous: All signals are registered on the
positive edge of the system clock
Programmable Burst Lengths: 1, 2, 4, 8 or Full
Page
3.3V 0.3V Power Supply
144 Pin SO-DIMM JEDEC
D1: 27.94 (1.10")
PIN CONFIGURATIONS (FRONT SIDE/BACK SIDE)
PIN NAMES
* These pins are not used in this module.
** These pins should be NC in the system
which does not support SPD.
A0 A11
Address input (Multiplexed)
BA0-1
Select Bank
DQ0-63
Data Input/Output
CLK0
Clock input
CKE0
Clock Enable input
CS0#
Chip select Input
RAS#
Row Address Strobe
CAS#
Column Address Strobe
WE#
Write Enable
DQM0-7
DQM
V
CC
Power Supply (3.3V)
V
SS
Ground
*V
REF
Power supply for reference
SDA
Serial data I/O
SCL
Serial clock
DNU
Do not use
NC
No Connect
WED3DG644V-D1
White Electronic Designs
2
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
June 2006
Rev. 3
FUNCTIONAL BLOCK DIAGRAM
DQM4
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQM1
UDQM
LDQM
LDQM
CS#
CS#
CS#
CS0#
DQM0
DQM4
DQM2
DQM3
UDQM
DQM6
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQM5
UDQM
LDQM
DQ48
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
LDQM
CS#
DQM7
UDQM
SERIAL PD
SCL
BA0
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
RAS#
CAS#
WE#
CKE0
DQn
Every DQpin of SDRAM
10
V
CC
V
CC
TWO 0.1 uF CAPACITORS
PER EACH SDRAM
To all SDRAMS
47
SDA
WP
SA0
SA1
SA2
CLK1
10
10pF
A0-A11
SDRAM
SDRAM
SDRAM
CLK0
SDRAM
SDRAM
10
10
Notes: 1. All resistor values are 10 ohms unless otherwise specifi ed.
2. D1 option does not have series resistors.
WED3DG644V-D1
White Electronic Designs
3
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
June 2006
Rev. 3
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Units
Voltage on any pin relative to V
SS
V
IN
, V
OUT
-1.0 ~ 4.6
V
Voltage on V
CC
supply relative to V
SS
V
CC
, V
CCQ
-1.0 ~ 4.6
V
Storage Temperature
T
STG
-55 ~ +150
C
Power Dissipation
P
D
4 W
Short Circuit Current
I
OS
50
mA
Note: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Parameter
Symbol
Min
Typ
Max
Unit
Note
Supply Voltage
V
CC
3.0
3.3 3.6
V
Input High Voltage
V
IH
2.0
3.0
V
CCQ+0.3
V
1
Input Low Voltage
V
IL
-0.3
--
0.8
V
2
Output High Voltage
V
OH
2.4
--
--
V
I
OH
= -2mA
Output Low Voltage
V
OL
--
--
0.4
V
I
OL
= -2mA
Input Leakage Current
I
LI
-10
--
10
A
3
Note: 1. V
IH
(max)= 5.6V AC. The overshoot voltage duration is 3ns.
2.
V
IL
(min)= -2.0V AC. The undershoot voltage duration is 3ns.
3. Any input 0V V
IN
V
CCQ
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
T
A
= 25C, f = 1MHz, V
CC
= 3.3V, V
REF
= 1.4V 200mV
Parameter
Symbol
Max
Unit
Input Capacitance (A0-A12)
C
IN1
25
pF
Input Capacitance (RAS#,CAS#,WE#)
C
IN2
25
pF
Input Capacitance (CKE0)
C
IN3
25
pF
Input Capacitance (CLK0)
C
IN4
19
pF
Input Capacitance (CS0#)
C
IN5
25
pF
Input Capacitance (DQM0-DQM7)
C
IN6
8
pF
Input Capacitance (BA0-BA1)
C
IN7
25
pF
Data Input/Output Capacitance (DQ0-DQ63)
C
OUT
10
pF
RECOMMENDED DC OPERATING CONDITIONS
Voltage Referenced to: V
SS
= 0V, T
A
= 0C to +70C
WED3DG644V-D1
White Electronic Designs
4
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
June 2006
Rev. 3
OPERATING CURRENT CHARACTERISTICS
(V
CC
= 3.3V, T
A
= 0C to +70C)
Version
Parameter
Symbol
Conditions
133/100
Units
Note
Operating Current
(One bank active)
I
CC1
Burst Length = 1
t
RC
t
RC
(min)
I
OL
= 0mA
300
mA
1
Precharge Standby Current
in Power Down Mode
I
CC2P
CKE V
IL
(max), t
CC
= 10ns
4
mA
I
CC2PS
CKE & CLK V
IL
(max), t
CC
=
4
Precharge Standby Current
in Non-Power Down Mode
I
CC2N
CKE V
IH
(min), CS V
IH
(min), tcc =10ns
Input signals are charged one time during 20
48
mA
I
CC2NS
CKE V
IH
(min), CLK V
IL
(max), t
CC
=
Input signals are stable
24
Active Standby Current in
Power-Down Mode
I
CC3P
CKE V
IL
(max), t
CC
= 10ns
8
mA
I
CC3PS
CKE & CLK V
IL
(max), t
CC
=
8
Active Standby Current in
Non-Power Down Mode
I
CC3N
CKE V
IH
(min), CS V
IH
(min), tcc = 10ns
Input signals are changed one time during 20ns
80
mA
I
CC3NS
CKE V
IH
(min), CLK V
IL
(max), tcc =
Input signals are stable
40
mA
Operating Current (Burst mode)
I
CC4
Io = mA
Page burst
4 Banks activated
t
CCD
= 2CLK
460
mA
1
Refresh Current
I
CC5
t
RC
t
RC
(min)
360
mA
2
Self Refresh Current
I
CC6
CKE 0.2V
4
mA
Notes:
1.
Measured with outputs open.
2.
Refresh period is 64ms.
WED3DG644V-D1
White Electronic Designs
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
June 2006
Rev. 3
AC OPERATING TEST CONDITIONS
V
CC
= 3.3V 0.3V, 0 T
A
70C
Parameter
Value
Unit
AC input levels (V
IH
/V
IL
)
2.4/0.4
V
Input timing measurement reference level
1.4
V
Input rise and fall time
t
R
/t
F
= 1/1
ns
Output timing measurement reference level
1.4
V
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Symbol
Version
Unit
Note
7.5, 10
Row active to row active delay
t
RRD
(min)
15
ns
1
RAS# to CAS# delay
t
RCD
(min)
20
ns
1
Row precharge time
t
RP
(min)
20
ns
1
Row active time
t
RAS
(min)
45
ns
1
t
RAS
(max)
100
us
Row cycle time
t
RC
(min)
65
ns
1
Last data in to row precharge
t
RDL
(min)
2
CLK
2
Last data in to Active delay
t
DAL
(min)
2 CLK + t
RP
--
Last data in to new col. address delay
t
CDL
(min)
1
CLK
2
Last data in to burst stop
t
BDL
(min)
1
CLK
2
Col. address to col. address delay
t
CCD
(min)
1
CLK
3
Number of valid output data
CAS latency=3
2
ea
4
CAS latency=2
1
Notes :
1.
The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer.
2.
Minimum delay is required to complete write.
3.
All parts allow every cycle column address change.
4.
In case of row precharge interrupt, auto precharge and read burst stop.