1
White Electronic Designs Corporation Phoenix, AZ (602) 437-1520
HI-RELIABILITY PRODUCT
512Kx16 CMOS EEPROM MODULE
WE512K16-XG4X
FEATURES
s Access Time of 140, 150, 200ns
s Packaging:
68 lead, 40mm Hermetic CQFP (Package 501)
s Organized as 4 banks of 128Kx16
s Write Endurance 10,000 Cycles
s Data Retention Ten Years Minimum
s Military Temperature Range
s Low Power CMOS
s Automatic Page Write Operation
s Page Write Cycle Time: 10ms Max
s Data Polling for End of Write Detection
s Hardware and Software Data Protection
s TTL Compatible Inputs and Outputs
s 5 Volt Power Supply
s 8 Built-in Decoupling Caps and Multiple Ground Pins for Low
Noise Operation
s Weight - 20 grams typical
April 1999 Rev. 2
FIG. 1
PIN CONFIGURATION
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
GND
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
V
CC
A
11
A
12
A
13
A
14
A
15
A
16
CS
2
OE
CS
4
NC
NC
NC
NC
NC
NC
NC
NC
NC
INC
NC
NC
NC
NC
NC
GND
NC
NC
NC
NC
NC
NC
NC
NC
NC
A
0
A
1
A
2
A
3
A
4
A
5
CS
1
GN
D
CS
3
WE
A
6
A
7
A
8
A
9
A
10
V
CC
PIN DESCRIPTION
BLOCK DIAGRAM
TOP VIEW
128K x 8
I / O
0 - 7
CS
1
128K x 8
I / O
8 - 1 5
C S
2
CS
3
128K x 8
128K x 8
CS
4
A
0 - 1 6
O E
W E
128K x 8
128K x 8
128K x 8
128K x 8
I/O
0-15
Data Inputs/Outputs
A
0-16
Address Inputs
WE
Write Enable
CS
1-4
Chip Selects
OE
Output Enable
V
CC
Power Supply
GND
Ground
NC
Not Connected
NOTE:
CS
1-4
are used as bank selects. During reads, only one CSx can be
active at one time.
2
White Electronic Designs Corporation Phoenix, AZ (602) 437-1520
WE512K16-XG4X
ABSOLUTE MAXIMUM RATINGS
TRUTH TABLE
FIG. 2
AC TEST CIRCUIT
AC TEST CONDITIONS
I
Current Source
D.U.T.
C = 50 pf
eff
I
OL
V
1.5V
(Bipolar Supply)
Z
Current Source
OH
NOTES:
V
Z
is programmable from -2V to +7V.
I
OL
& I
OH
programmable from 0 to 16mA.
Tester Impedance Z
0
= 75
.
V
Z
is typically the midpoint of V
OH
and V
OL
.
I
OL
& I
OH
are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
RECOMMENDED OPERATING CONDITIONS
DC CHARACTERISTICS
(V
CC
= 5.0V, GND = 0V, T
A
= -55
C to +125
C)
Parameter
Typ
Unit
Input Pulse Levels
V
IL
= 0, V
IH
= 3.0
V
Input Rise and Fall
5
ns
Input and Output Reference Level
1.5
V
Output Timing Reference Level
1.5
V
Parameter
Symbol
Unit
Operating Temperature
T
A
-55 to +125
C
Storage Temperature
T
STG
-65 to +150
C
Signal Voltage Relative to GND
V
G
-0.6 to +6.25
V
Voltage on OE and A9
-0.6 to +13.5
V
NOTE:
Stresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability.
CS
OE
WE
Mode
Data I/O
H
X
X
Standby
High Z
L
L
H
Read
Data Out
L
H
L
Write
Data In
X
H
X
Out Disable
High Z/Data Out
X
X
H
Write
X
L
X
Inhibit
Parameter
Symbol
Min
Max
Unit
Supply Voltage
V
CC
4.5
5.5
V
Input High Voltage
V
IH
2.0
Vcc + 0.3
V
Input Low Voltage
V
IL
-0.3
+0.8
V
Operating Temp. (Mil.)
T
A
-55
+125
C
Parameter
Symbol
Conditions
Min
Max
Unit
Input Leakage Current
I
LI
V
CC
= 5.5, V
IN
= GND to V
CC
10
A
Output Leakage Current
I
LO
CS = V
IH
, OE = V
IH
, V
OUT
= GND to V
CC
10
A
Operating Supply Current (x16)
I
CCx16
CS
1
= V
IL
, OE = CS
2-4
= V
IH
, f = 5MHz, V
CC
= 5.5
160
mA
Chip Erase Current
I
CC1
CS = V
IL
, OE = V
IH
, f = 5MHz, V
CC
= 5.5
250
mA
Standby Current (CMOS)
I
SB
CS = V
IH
, OE = V
IH
, f = 5MHz, V
CC
= 5.5
5
mA
Output Low Voltage
V
OL
I
OL
= 2.1mA, V
CC
= 4.5V
0.45
V
Output High Voltage
V
OH
I
OH
= -400
A, V
CC
= 4.5V
2.4
V
NOTE: DC test conditions: V
IH
= V
CC
-0.3V, V
IL
= 0.3V
CAPACITANCE
(T
A
= +25
C)
Parameter
Symbol
Conditions
Max
Unit
OE capacitance
C
OE
V
IN
= 0 V, f = 1.0 MHz
50
pF
WE capacitance
C
WE
V
IN
= 0 V, f = 1.0 MHz
50
pF
CS
1-4
capacitance
C
CS
V
IN
= 0 V, f = 1.0 MHz
25
pF
Data I/O capacitance
C
I/O
V
I/O
= 0 V, f = 1.0 MHz
40
pF
Address input capacitance
C
AD
V
IN
= 0 V, f = 1.0 MHz
70
pF
This parameter is guaranteed by design but not tested.
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White Electronic Designs Corporation Phoenix, AZ (602) 437-1520
WE512K16-XG4X
WRITE
A write cycle is initiated when OE is high and a low pulse is on WE
or CS with CS or WE low. The address is latched on the falling
edge of CS or WE whichever occurs last. The data is latched by
the rising edge of CS or WE, whichever occurs first. A word write
operation will automatically continue to completion.
WRITE CYCLE TIMING
Figures 3 and 4 show the write cycle timing relationships. A
write cycle begins with address application, write enable and
chip select. Chip select is accomplished by placing the CS line
low. Write enable consists of setting the WE line low. The
write cycle begins when the last of either CS or WE goes low.
The WE line transition from high to low also initiates an
internal 150
sec delay timer to permit page mode operation.
Each subsequent WE transition from high to low that occurs
before the completion of the 150
sec time out will restart the
timer from zero. The operation of the timer is the same as a
retriggerable one-shot.
AC WRITE CHARACTERISTICS
(V
CC
= 5.0V, GND = 0V, T
A
= -55
C to +125
C)
Write Cycle Parameter
Symbol
Min
Max
Unit
Write Cycle Time, TYP = 6ms
t
WC
10
ms
Address Set-up Time
t
AS
10
ns
Write Pulse Width (WE or CS)
t
WP
120
ns
Chip Select Set-up Time
t
CS
0
ns
Address Hold Time
t
AH
100
ns
Data Hold Time
t
DH
10
ns
Chip Select Hold Time
t
CSH
0
ns
Data Set-up Time
t
DS
100
ns
Output Enable Set-up Time
t
OES
10
ns
Output Enable Hold Time
t
OEH
10
ns
Write Pulse Width High
t
WPH
50
ns
4
White Electronic Designs Corporation Phoenix, AZ (602) 437-1520
FIG. 3
WRITE WAVEFORM
WE CONTROLLED
FIG. 4
WRITE WAVEFORM
CS CONTROLLED
t
ADDRESS
CS
1-4
WE
DATA IN
DH
t
WPH
t
WP
t
CSH
t
OEH
t
AH
t
OES
t
AS
t
CS
OE
t
WC
t
DS
t
ADDRESS
WE
CS
1 - 4
DATA IN
DH
t
WPH
t
WP
t
CSH
t
OEH
t
AH
t
OES
t
AS
t
CS
OE
t
DS
t
WC
WE512K16-XG4X
5
White Electronic Designs Corporation Phoenix, AZ (602) 437-1520
AC READ CHARACTERISTICS
(V
CC
= 5.0V, GND = 0V, T
A
= -55
C to +125
C)
FIG. 5
READ WAVEFORM
t
ADDRESS
CS
1-4
OE
OUTPUT
OH
t
DF
t
ACC
t
RC
t
OE
t
ACS
OUTPUT
VALID
ADDRESS VALID
HIGH Z
READ
The module stores data at the memory location determined by
the address pins. When CS and OE are low and WE is high,
this data is present on the outputs. When CS and OE are high,
the outputs are in a high impedance state. This two line
control prevents bus contention.
NOTES:
OE may be delayed up to t
ACS
- t
OE
after the
falling edge of CS without impact on t
OE
or by
t
ACC
- t
OE
after an address change without
impact on t
ACC
.
CS
1-4
are used as bank selects.
During reads, only one CSx can be active at one
time.
Read Cycle Parameter
Symbol
-140
-150
-200
Unit
Min
Max
Min
Max
Min
Max
Read Cycle Time
t
RC
140
150
200
ns
Address Access Time
t
ACC
140
150
200
ns
Chip Select Access Time
t
ACS
140
150
200
ns
Output Hold from Add. Change, OE or CS
t
OH
0
0
0
ns
Output Enable to Output Valid
t
OE
0
50
0
55
0
55
ns
Chip Select or OE to High Z Output
t
DF
50
70
70
ns
WE512K16-XG4X
6
White Electronic Designs Corporation Phoenix, AZ (602) 437-1520
DATA POLLING
The module offers a data polling feature which allows a faster
method of writing to the device. Figure 6 shows the timing
diagram for this function. During a word or page write cycle,
an attempted read of the last word written will result in the
complement of the written data on I/O
7
and I/O
15
. Once the
write cycle has been completed, true data is valid on all
outputs and the next cycle may begin. Data polling may begin
at any time during the write cycle.
DATA POLLING CHARACTERISTICS
(V
CC
= 5.0V, GND = 0V, T
A
= -55
C to +125
C)
FIG. 6
DATA POLLING
WAVEFORM
Parameter
Symbol
Min
Max
Unit
Data Hold Time
t
DH
10
ns
OE Hold Time
t
OEH
10
ns
OE To Output Valid
t
OE
55
ns
Write Recovery Time
t
WR
0
ns
WE
t
OEH
t
DH
t
OE
t
WR
HIGH Z
CS
1-4
OE
I/O
7
I/O
15
ADDRESS
WE512K16-XG4X
7
White Electronic Designs Corporation Phoenix, AZ (602) 437-1520
PAGE WRITE OPERATION
The module has a page write operation that allows one to 128
words of data to be written into the device and consecutively loads
during the internal programming period. Successive words may be
loaded in the same manner after the first data word has been
loaded. An internal timer begins a time out operation at each
write cycle. If another write cycle is completed within 150
s or
less, a new time out period begins. Each write cycle restarts the
delay period. The write cycles can be continued as long as the
interval is less than the time out period.
The usual procedure is to increment the least significant
address lines from A
0
through A
6
at each write cycle. In this
manner a page of up to 128 words can be loaded in to the
EEPROM in a burst mode before beginning the relatively long
interval programming cycle.
After the 150
s time out is completed, the EEPROM begins an
internal write cycle. During this cycle the entire page of words
will be written at the same time. The internal programming
cycle is the same regardless of the number of words accessed.
PAGE WRITE CHARACTERISTICS
(V
CC
= 5.0V, GND = 0V, T
A
= -55
C to +125
C)
FIG. 7
PAGE MODE
WRITE WAVEFORM
1. Page address must remain valid for duration of write cycle.
Page Mode Write Characteristics
Symbol
Unit
Parameter
Min
Max
Write Cycle Time, TYP = 6ms
t
WC
10
ms
Address Set-up Time
t
AS
0
ns
Address Hold Time (1)
t
AH
50
ns
Data Set-up Time
t
DS
50
ns
Data Hold Time
t
DH
0
ns
Write Pulse Width
t
WP
100
ns
Word Load Cycle Time
t
BLC
150
s
Write Pulse Width High
t
WPH
50
ns
OE
WORD 1
WORD 2
WORD 3
WORD 126
WORD 0
VALID
ADDRESS
t
WC
t
BLC
t
WPH
t
WP
ADDRESS
DATA
CS
1-4
WE
WORD 127
t
DS
t
DH
t
AS
t
AH
WE512K16-XG4X
8
White Electronic Designs Corporation Phoenix, AZ (602) 437-1520
LOAD DATA AAAA
TO
ADDRESS 5555
LOAD DATA 5555
TO
ADDRESS 2AAA
LOAD DATA A0A0
TO
ADDRESS 5555
LOAD DATA XXXX
TO
ANY ADDRESS
(4)
LOAD LAST WORD
TO
LAST ADDRESS
FIG. 8
SOFTWARE DATA PROTECTION
ENABLE ALGORITHM
(1)
WRITES ENABLED
(2)
NOTES:
1. Data Format: I/O
15
-
0
(Hex);
Address Format: A
16
-
0
(Hex).
2. Write Protect state will be activated at end of write even if no other
data is loaded.
3. Write Protect state will be deactivated at end of write period even if
no other data is loaded.
4. 1 to 128 words of data may be loaded.
ENTER DATA
PROTECT STATE
WE512K16-XG4X
9
White Electronic Designs Corporation Phoenix, AZ (602) 437-1520
HARDWARE DATA PROTECTION
These features protect against inadvertent writes to the
module. These are included to improve reliability during
normal operation:
a) V
CC
power on delay
As V
CC
climbs past 3.8V typical the device will wait 5 msec
typical before allowing write cycles.
b) V
CC
sense
While below 3.8V typical write cycles are inhibited.
c) Write inhibiting
Holding OE low and either CS or WE high inhibits write
cycles.
d) Noise filter
Pulses of <8ns (typ) on WE or CS will not initiate a write
cycle.
SOFTWARE DATA PROTECTION
A software write protection feature may be enabled or disabled
by the user. When shipped by White Microelectronics, the
module has the feature disabled. Write access to the device is
unrestricted.
To enable software write protection, the user writes three
access code words to three special internal locations. Once
write protection has been enabled, each write to the EEPROM
must use the same three-word write sequence to permit
writing. After setting software data protection, any attempt to
write to the device without the three-word command sequence
will start the internal write timers. No data will be written to
the device, however, for the duration of t
WC
. The write
protection feature can be disabled by a six-word write
sequence of specific data to specific locations. Power
transitions will not reset the software write protection.
Each 128K-word block of the EEPROM has independent write
protection. One or more blocks may be enabled and the rest
disabled in any combination. The software write protection
guards against inadvertent writes during power transitions, or
unauthorized modification using a PROM programmer.
FIG. 9
SOFTWARE DATA PROTECTION
DISABLE ALGORITHM
(1)
EXIT DATA
PROTECT STATE
NOTES:
1. Data Format: I/O
15
-
0
(Hex);
Address Format: A
16
-
0
(Hex).
2. Write Protect state will be activated at end of write even if no other
data is loaded.
3. Write Protect state will be deactivated at end of write period even if
no other data is loaded.
4. 1 to 128 words of data may be loaded.
(3)
LOAD DATA AAAA
TO
ADDRESS 5555
LOAD DATA 5555
TO
ADDRESS 2AAA
LOAD DATA 8080
TO
ADDRESS 5555
LOAD DATA AAAA
TO
ADDRESS 5555
LOAD DATA 5555
TO
ADDRESS 2AAA
LOAD DATA 2020
TO
ADDRESS 5555
LOAD DATA XXXX
TO
ANY ADDRESS
(4)
LOAD LAST WORD
TO
LAST ADDRESS
WE512K16-XG4X
10
White Electronic Designs Corporation Phoenix, AZ (602) 437-1520
WE512K16-XG4X
PACKAGE 501:
68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G4)
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
0.38 (0.015)
0.08 (0.003)
68 PLACES
1.27 (0.050)
TYP
5.1 (0.200) MAX
39.6 (1.56)
0.38 (0.015) SQ
38 (1.50) TYP
4 PLACES
5.1 (0.200)
0.25 (0.010)
4 PLACES
12.7 (0.500)
0.5 (0.020)
4 PLACES
0.25 (0.010)
0.05 (0.002)
1.27 (0.050)
0.1 (0.005)
PIN 1 IDENTIFIER
Pin 1
ORDERING INFORMATION
LEAD FINISH:
Blank = Gold plated leads
A = Solder dip leads
PROCESSING:
Q = MIL-STD-883 Compliant
M = Military Screened
-55
C to +125
C
I = Industrial
-40
C to +85
C
C = Commercial
0
C to +70
C
PACKAGE:
G4 = 40mm Ceramic Quad Flat Pack, CQFP (Package 501)
ACCESS TIME (ns)
ORGANIZATION, 4 banks of 128Kx16
EEPROM
WHITE ELECTRONIC DESIGNS CORP.
W E 512K16 - XXX G4 X X
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