1
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
W72M64V-XBX
2Mx64 3.3V Simultaneous Operation Flash Multi-Chip Package
FEATURES
!
Access Times of 100, 120, 150ns
!
Packaging
159 PBGA, 13x22mm - 1.27mm pitch
!
1,000,000 Erase/Program Cycles
!
Sector Architecture
Bank 1 (8Mb): eight 4K word, fifteen 32K word
Bank 2 (24Mb): forty-eight 32K word
!
Bottom boot block
!
Zero Power Operation
!
Organized as 2Mx64 or 2x2Mx32
!
Commercial, Industrial and Military Temperature
Ranges
!
3.3 Volt for Read and Write Operations
!
Simultaneous Read/Write Operation:
Data can be continuously read from one bank
while executing erase/program functions in
another bank
Zero latency between read and write operations
!
Erase Suspend/Resume
Suspends erase operations to allow
programming in same bank
!
Data Polling and Toggle Bits
Provides a software method of detecting the
status of program or erase cycles
!
Unlock Bypass Program command
Reduces overall programming time when
issuing multiple program command sequences
!
Ready/Busy output (RY/BY)
Hardware method for detecting program or erase
cycle completion
!
Hardware reset pin (RESET)
Hardware method of resetting the internal state
machine to the read mode
!
WP/ACC input pin
Write protect (WP) function allows protection of
two outermost boot sectors, regardless of
sector protect status
Acceleration (ACC) function accelerates
program timing
!
Sector Protection
Hardware method of locking a sector, either
in-system or using programming equipment, to
prevent any program or erase operation within
that sector
Temporary Sector Unprotect allows changing
data in protected sectors in-system
Note: For programming information refer to Flash Programming
W72M64V-XBX Application Note.
November 2003 Rev. 1
* Preliminary datasheet. This datasheet describes a product that is not characterized or qualified and is subject to
change without notice.
*Preliminary
2
White Electronic Designs Corporation Phoenix AZ (602) 437-1520
W72M64V-XBX
1
2
3
4
5
6
7
8
9 10
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
GND
A
2
WP/A
CC
A
11
GND
V
CC
A
7
A
10
A
15
GND
GND
OE
A
0
DNU
V
CC
A
12
A
16
DNU*
A
20
GND
GND
CS
3
DQ
34
DQ
36
DQ
38
CS
4
DQ
50
DQ
52
DQ
54
GND
V
CC
DQ
32
DQ
42
DQ
44
DQ
46
DQ
48
DQ
58
DQ
60
DQ
62
V
CC
V
CC
DQ
40
DQ
35
DQ
37
DQ
39
DQ
56
DQ
51
DQ
53
DQ
55
V
CC
V
CC
DQ
33
DQ
43
DQ
45
DQ
47
DQ
49
DQ
59
DQ
61
DQ
63
V
CC
V
CC
GND
DQ
41
WE
3
V
CC
DQ
57
DNU
WE
4
V
CC
V
CC
GND
GND
GND
V
CC
V
CC
GND
GND
GND
V
CC
V
CC
GND
GND
GND
V
CC
V
CC
GND
GND
GND
V
CC
V
CC
V
CC
DQ
25
DQ
27
DQ
22
CS
1
DQ
2
DQ
12
GND
V
CC
V
CC
CS
2
DQ
18
DQ
20
DQ
30
DQ
0
DQ
10
DQ
5
DQ
14
V
CC
V
CC
DQ
16
DQ
26
DQ
28
DQ
23
DQ
8
DQ
3
DQ
13
DQ
7
V
CC
V
CC
DQ
24
DQ
19
DQ
21
DQ
31
DQ
1
DQ
11
DQ
6
DQ
15
V
CC
GND
DQ
17
WE
2
DQ
29
DNU
DQ
9
DQ
4
WE
1
A
19
GND
GND
A
4
A
17
RY/BY
GND
A
14
A
5
A
18
A
8
GND
GND
A
3
A
6
A
9
V
CC
GND
A
1
RESET
A
13
GND
FIG 1: PIN CONFIGURATION FOR W72M64V-XBX
PIN DESCRIPTION
DQ
0-63
Data Inputs/Outputs
A
0-20
Address Inputs
WE
1-4
Write Enables
CS
1-4
Chip Selects
OE
Output Enable
RESET
Hardware Reset
WP/ACC
Hardware Write
Protect/Acceleration
RY/BY
Ready/Busy Output
V
CC
Power Supply
GND
Ground
DNU
Do Not Use
BLOCK DIAGRAM
TOP VIEW
DQ
0-15
DQ
16-31
DQ
32-47
DQ
48-63
CS
1
CS
2
CS
3
CS
4
2M x 16
2M x 16
2M x 16
2M x 16
BYTE
BYTE
BYTE
BYTE
WE
4
WE
3
WE
2
WE
1
WP/ACC
V
CC
A
0-20
RY/BY
RESET
OE
* Ball G8 is DNU on this device and will become A
21
on the W74M64V-XBX
3
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
W72M64V-XBX
Parameter
Symbol
Conditions
Min
Max
Unit
Input Leakage Current
I
LI
V
CC
= 3.6V, V
IN
= GND to V
CC
-10
10
A
Output Leakage Current
I
LO
V
CC
= 3.6V, V
OUT
= GND to V
CC
-10
10
A
V
CC
Active Current for Read (1)
I
CC1
CS = V
IL
, OE = V
IH
, f = 5MHz
65
mA
V
CC
Active Current for Program or Erase (2,3)
I
CC2
CS = V
IL
, OE = V
IH,
WE = V
IL
120
mA
V
CC
Standby Current (2)
I
CC3
CS = RESET = V
CC
0.3V
20
A
V
CC
Reset Current (2)
I
CC4
RESET = V
SS
0.3V
20
A
Automatic Sleep Mode (2,4)
I
CC5
V
IH
= V
CC
0.3V;
V
IL
= V
SS
0.3V
20
A
V
CC
Active Read-While-Program Current (1,2)
I
CC6
CS = V
IL,
OE
=
V
IH
180
mA
V
CC
Active Program-While-Erase Current (1,2)
I
CC7
CS = V
IL,
OE
=
V
IH
180
mA
V
CC
Active Program-While-Erase-Suspended
I
CC8
Current (2,5)
CS = V
IL,
OE
=
V
IH
140
mA
A
CC
Accelerated Program Current
I
ACC
A
CC
Pin
40
CS = V
IL,
OE
=
V
IH
V
CC
Pin
120
mA
Input Low Voltage
V
IL
-0.5
0.8
V
Input High Voltage
V
IH
0.7 x Vcc
Vcc + 0.3
V
Voltage for WP/ACC Sector
Protect/Unprotect and Program Acceleration
V
HH
Vcc = 3.0V + 0.3V
8.5
9.5
V
Voltage for Autoselect and Temporary
Sector Unprotect
V
ID
Vcc = 3.0V + 0.3V
8.5
12.5
V
Output Low Voltage
V
OL
I
OL
= 4.0 mA, V
CC
= 3.0V
0.45
V
Output High Voltage
V
OH1
I
OH
= -2.0 mA, V
CC
= 3.0V
0.85
X
V
CC
V
Low V
CC
Lock-Out Voltage (5)
V
LKO
2.3
2.5
V
ABSOLUTE MAXIMUM RATINGS
NOTES:
1.
Stresses above the absolute maximum rating may cause
permanent damage to the device. Extended operation at the maximum
levels may degrade performance and affect reliability.
Parameter
Unit
Operating Temperature
-55 to +125
C
Supply Voltage Range (V
CC
)
-0.5 to +4.0
V
Signal Voltage Range
-0.5 to Vcc +0.5
V
Storage Temperature Range
-55 to +150
C
Endurance (write/erase cycles)
1,000,000 min.
cycles
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min
Max
Unit
Supply Voltage
V
CC
3.0
3.6
V
Operating Temp. (Mil.)
T
A
-55
+125
C
Operating Temp. (Ind.)
T
A
-40
+85
C
CAPACITANCE
(T
A
= +25C)
DC CHARACTERISTICS - CMOS COMPATIBLE
(V
CC
= 3.3V 0.3V, T
A
= -55C to +125C)
NOTES:
1.
The I
CC
current listed includes both the DC operating current and the frequency dependent component (at 5 MHz). The frequency
component typically is less than 8 mA/MHz, with OE at V
IH
.
2.
Maximum I
CC
specifications are tested with V
CC
= V
CC
MAX
3.
I
CC
active while Embedded Algorithm (program or erase) is in progress.
4.
Automatic sleep mode enables the low power mode when addresses remain stable for t
ACC
+ 30ns.
5.
Not 100% tested.
DATA RETENTION
Parameter
Test Conditions
Min
Unit
Pattern Data
150C
10
Years
Retention Time
125C
20
Years
Parameter
Symbol
Conditions
Max
Unit
WE
1-4
capacitance
C
W E
V
IN
= 0 V, f = 1.0 MHz
25
pF
CS
1-4
capacitance
C
CS
V
IN
= 0 V, f = 1.0 MHz
25
pF
Data I/O capacitance
C
I/O
V
I/O
= 0 V, f = 1.0 MHz
12
pF
Address input capacitance
C
AD
V
IN
= 0 V, f = 1.0 MHz
25
pF
RESET capacitance
C
RS
V
IN
= 0 V, f = 1.0 MHz
20
pF
RY/BY capacitance
C
RB
V
IN
= 0 V, f = 1.0 MHz
20
pF
WP/A
CC
capacitance
C
W A
V
IN
= 0 V, f = 1.0 MHz
30
pF
This parameter is guaranteed by design but not tested.
4
White Electronic Designs Corporation Phoenix AZ (602) 437-1520
W72M64V-XBX
Parameter
Symbol
-100
-120
-150
Unit
Min Max Min Max Min Max
Write Cycle Time
t
A V A V
t
W C
100
120
150
ns
Write Enable Setup Time
t
W L E L
t
W S
0
0
0
ns
Chip Select Pulse Width
t
E L E H
t
C P
45
50
50
ns
Address Setup Time
t
A V W L
t
A S
0
0
0
ns
Data Setup Time
t
D V E H
t
D S
45
50
50
ns
Data Hold Time
t
E H D X
t
D H
0
0
0
ns
Address Hold Time
t
E L A X
t
A H
45
50
50
ns
Chip Select Pulse Width High
t
E H E L
t
C P H
30
30
30
ns
Duration of Byte Programming Operation (1)
t
W H W H 1
300
300
300
s
Sector Erase Time (2)
t
W H W H 2
15
15
15
sec
Read Recovery Time Before Write (3)
t
G H E L
0
0
0
ns
Chip Programming Time (4)
108
108
108
sec
1. Typical value for t
WHWH
1
is 7s.
2. Typical value for t
WHWH
2
is 0.7 sec.
3. Guaranteed by design, but not tested.
4. Typical value is 36 sec. The typical chip programming time is considerably less than the maximum chip programming time
listed, since most bytes program faster than the maximum program times listed.
AC CHARACTERISTICS WRITE/ERASE/PROGRAM OPERATIONS - CS CONTROLLED
(V
CC
= 3.3V 0.3V, T
A
= -55C to +125C)
FIG 2: AC TEST CIRCUIT
AC TEST CONDITIONS
NOTES:
V
Z
is programmable from -2V to +7V.
I
OL
& I
OH
programmable from 0 to 16mA.
Tester Impedance Z
0
= 75
.
V
Z
is typically the midpoint of V
OH
and V
OL
.
I
OL
& I
OH
are adjusted to simulate a typical resistive
load circuit.
ATE tester includes jig capacitance.
Parameter
Typ Unit
Input Pulse Levels
V
IL
= 0, V
IH
= 2.5 V
Input Rise and Fall
5 ns
Input and Output Reference Level 1.5 V
Output Timing Reference Level 1.5 V
Current Source
Current Source
I
OL
I
OH
C
EFF
= 50 pf
V
Z
1.5V
(Bipolar Supply
D.U.T.
5
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
W72M64V-XBX
Parameter
Symbol
-100 -120 -150
Unit
Min
Max
Min
Max
Min
Max
Write Cycle Time
t
AVAV
t
W C
100
120
150
ns
Chip Select Setup Time
t
ELWL
t
C S
0
0
0
ns
Write Enable Pulse Width
t
WLWH
t
W P
50
50
65
ns
Address Setup Time
t
AVWL
t
A S
0
0
0
ns
Data Setup Time
t
DVWH
t
D S
50
50
65
ns
Data Hold Time
t
WHDX
t
DH
0
0
0
ns
Address Hold Time
t
WLAX
t
A H
50
50
65
ns
Write Enable Pulse Width High
t
WHWL
t
W P H
30
30
35
ns
Duration of Byte Programming Operation (1)
t
WHWH
1
300
300
300
s
Sector Erase (2)
t
WHWH
2
15
15
15
sec
Read Recovery Time before Write (3)
t
GHWL
0
0
0
ns
VCC Setup Time
t
VCS
50
50
50
s
Chip Programming Time (4)
108
108
108
sec
Address Setup Time to OE low during toggle bit polling
t
A S O
15
15
15
n s
Address Hold Time From CS or OE high
during toggle
t
A H T
0
0
0
n s
Output Enable High during toggle bit polling
t
O E P H
20
20
20
n s
Latency Between Read and Write Operations
t
S R
/ W
0
0
0
n s
Write Recovery Time from RY/BY
t
R B
0
0
0
n s
Program/Erase Valid to RY/BY
t
B U S Y
90
90
90
n s
AC CHARACTERISTICS WRITE/ERASE/PROGRAM OPERATIONS - WE CONTROLLED
(V
CC
= 3.3V 0.3V, T
A
= -55C to +125C)
1.
Typical value for t
WHWH
1
is 7s.
2.
Typical value for t
WHWH
2
is 0.7 sec.
3.
Guaranteed by design, but not tested.
4.
Typical value is 36 sec. The typical chip programming time is considerably less than the maximum chip programming time listed, since most
bytes program faster than the maximum program times listed.
AC CHARACTERISTICS READ-ONLY OPERATIONS
(V
CC
= 3.3V 0.3V, T
A
= -55C to +125C)
Parameter
Symbol -100 -120 -150
Unit
Min Max Min Max
Min Max
Read Cycle Time
t
A V A V
t
RC
100
120
150
ns
Address Access Time
t
AVQV
t
ACC
100
120
150
ns
Chip Select Access Time
t
ELQV
t
C E
100
120
150
ns
Output Enable to Output Valid
t
GLQV
t
OE
40
50
55
ns
Chip Select High to Output High Z (1)
t
EHQZ
t
DF
20
20
20
ns
Output Enable High to Output High Z (1)
t
GHQZ
t
DF
20
20
20
ns
Output Hold from Addresses, CS or OE Change,
t
AXQX
t
OH
0
0
0
ns
Whichever occurs first
Read
t
OEH
0
0
0
Output Enable Hold Time (1)
Toggle and
Data Polling
10
10
10
1.
Guaranteed by design, not tested.
6
White Electronic Designs Corporation Phoenix AZ (602) 437-1520
W72M64V-XBX
FIG 3: AC WAVEFORMS FOR READ OPERATIONS
Addresses
CS
OE
WE
Outputs
High Z
Addresses Stable
t
OE
t
RC
Output Valid
t
CE
t
ACC
t
OH
High Z
t
DF
RESET
RY/BY
OV
t
OEH
7
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
W72M64V-XBX
RY/BY
CS, OE
RESET
tRP
tReady
tRH
tReady
tRB
tRP
RY/BY
CS, OE
RESET
AC CHARACTERISTICS HARDWARE RESET (RESET)
Parameter
Symbol
-100
-120
-150
Unit
Min
Max
Min
Max
Min
Max
RESET Pin Low (During Embedded Algorithms)
to Read Mode (See Note)
t
r e a d y
20
20
20
s
RESET Pin Low (NOT During Embedded Algorithms)
to Read Mode (See Note)
t
r e a d y
500
500
500
ns
RESET Pulse Width
t
R P
500
500
500
ns
RESET High Time Before Read (See Note)
t
R H
50
50
50
n s
RESET Low to Standby Mode
t
R P D
20
20
20
s
RY/BY Recovery Time
t
R B
0
0
0
ns
Note: Not tested.
FIG 4: RESET TIMINGS NOT DURING EMBEDDED ALGORITHMS
FIG 5: RESET TIMINGS DURING EMBEDDED ALGORITHMS
8
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W72M64V-XBX
NOTES:
1.
PA is the address of the memory location to be programmed.
2.
PD is the data to be programmed at byte address.
3.
D
OUT
is the output of the data written to the device.
4.
Figure indicates last two bus cycles of four bus cycle sequence.
FIG 6: PROGRAM OPERATION
Addresses
CS
OE
WE
Data
RY/BY
V
CC
555h
PA
PA
t
WC
t
AS
t
WHWH1
PD
Status
D
OUT
A0h
t
BUSY
PA
t
AS
t
CH
t
WP
t
CS
t
WPH
t
DS
t
DH
t
VCS
t
RB
9
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W72M64V-XBX
FIG 8: CHIP/SECTOR ERASE OPERATION TIMINGS
Notes:
1.
SA = Sector Address (for Sector Erase), VA = Valid Address for reading status data
FIG 7: ACCELERATED PROGRAM TIMING DIAGRAM
V
HH
t
VHH
t
VHH
V
IL
or V
IH
WP/A
CC
V
IL
or V
IH
Addresses
CS
OE
WE
Data
RY/BY
V
CC
2AAh
SA
VA
t
WC
t
AH
t
WHWH2
30h
In
Progress
Complete
55h
t
BUSY
VA
t
AS
t
CH
t
WP
t
CS
t
WPH
t
DS
t
DH
t
VCS
t
RB
10 for Chip Erase
555h for
chip erase
10
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W72M64V-XBX
FIG 9: BACK TO BACK READ/WRITE CYCLE TIMINGS
NOTE: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
FIG. 10: DATA POLLING TIMINGS (DURING EMBEDDED ALGORITHMS)
Addresses
CS
OE
WE
Data
t
AH
Valid RA
Valid PA
Valid PA
Valid PA
t
WC
t
RC
t
ACC
t
WP
t
DH
t
WC
t
WC
t
CE
t
CPH
t
CP
t
OE
t
WPH
t
OEH
t
GHWL
t
DF
Valid In
Valid In
t
DS
t
OH
t
SR/W
Valid Out
Valid In
WE Controlled Write Cycle Read Cycle CS Controlled Write Cycle
Addresses
VA
VA
VA
t
RC
CS
Complement
Complement
True
DQ
0
-DQ
6
t
CE
t
CH
t
OE
OE
WE
t
OEH
t
DF
t
OH
Valid Data
High Z
RY/BY
t
BUSY
DQ
7
t
ACC
Status Data
Status Data
True
Valid Data
High Z
11
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W72M64V-XBX
WE
DQ
6
DQ
2
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase Suspend
Read
Erase
Erase
Complete
FIG 11: TOGGLE BIT TIMINGS (DURING EMBEDDED ALGORITHMS)
NOTE: VA = Valid address, not required for DQ
6
. Illustration shows first two status cycle after command sequence, last status read
cycle, and array data read cycle.
FIG 12: DQ2 VS. DQ6
NOTE: DQ
2
toggles only when read at an address within an erase-suspended sector. The system may use OE or CS to toggle DQ
2
and DQ
6
.
RY/BY
DQ
6
/DQ
2
OE
CS
Addresses
WE
t
AS
t
AHT
t
AHT
t
ASO
t
CEPH
t
OEH
t
OEPH
t
DH
Valid Data
Valid
Status
Valid
Data
t
OE
(First Read)
(Second Read)
(Stops Toggling)
Valid
Status
Valid
Status
12
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W72M64V-XBX
Parameter
Speed Options
JEDEC
Std
Description
100
120
150
Unit
t
A V A V
t
W C
Write Cycle Time (1)
Min
90
120
150
ns
t
A V W L
t
A S
Address Setup Time
Min
0
0
0
ns
t
E L A X
t
A H
Address Hold Time
Min
45
50
50
ns
t
D V E H
t
D S
Data Setup Time
Min
45
50
50
ns
t
E H D X
t
DH
Data Hold Time
Min
0
0
0
ns
t
G H E L
t
G H E L
Read Recovery Time Before Write (OE High to WE Low)
Min
0
0
0
ns
t
W L E L
t
W S
WE Setup Time
Min
0
0
0
ns
t
E H W H
t
W H
WE Hold Time
Min
0
0
0
ns
t
E L E H
t
C P
CS Pulse Width
Min
45
50
50
ns
t
E H E L
t
C P H
CS Pulse Width High
Min
30
30
30
ns
t
W H W H
1
t
W H W H
1
Programming Operation Byte
Typ
9
9
9
s
t
W H W H
1
t
W H W H
1
Accelerated Programming Operation, Word or Byte
Typ
7
7
7
s
t
W H W H
2
t
W H W H
2
Sector Erase Operation
Typ
0.7
0.7
0.7
sec
OE
CS
RESET
WE
SA, A
6
,
A
1
, A
0
Data
1 s
V
ID
V
IH
Valid*
Valid*
Valid*
Sector/Sector Block Protect or Unprotect
60h
60h
40h
Status
Verify
Sector/Sector Block Protect: 150 s
Sector/Sector Block Unprotect: 15 ms
FIG 13: SECTOR/SECTOR BLOCK PROTECT AND UNPROTECT TIMING DIAGRAM
NOTES:
For sector protect, A
6
= 0, A
1
= 1, A
0
= 0. For sector unprotect, A
6
= 1, A
1
= 1, A
0
= 0.
AC CHARACTERISTICS ALTERNATE CS CONTROLLED ERASE AND PROGRAM OPERATIONS
NOTE:
1. Not tested.
13
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
W72M64V-XBX
FIG 14: ALTERNATE CS CONTROLLED WRITE (ERASE/PROGRAM)
OPERATION TIMINGS
NOTES:
1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ
7
is the complement of the data written to the device. D
OUT
is the data written to the device.
Addresses
555 for Program
2AA for Erase
PA
t
WC
WE
OE
CS
Data
t
AS
t
AH
t
CPH
t
WS
DQ
7
RESET
t
DH
t
DS
PD for Program
30 for Sector Erase
10 for Chip Erase
PA for Program
SA for Sector Erase
555 for Chip Erase
Data Polling
t
WH
t
GHEL
t
WHWH1 OR 2
t
BUSY
t
HR
A0 for Program
55 for Erase
RY/BY
t
CP
D
OUT
14
White Electronic Designs Corporation Phoenix AZ (602) 437-1520
W72M64V-XBX
W 7 2M64 V XXX B X
ORDERING INFORMATION
PACKAGE: 159 PBGA
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES.
BOTTOM VIEW
13.1 (0.516) MAX
11.43 (0.450) NOM
1.27 (0.050) NOM
1.27 (0.050) NOM
19.05 (0.750) NOM
22.1 (0.870) MAX
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
10 9 8 7 6 5 4 3 2 1
159 Y 0.762 (0.030) NOM
2.03 (0.080) MAX
0.61 (0.024)
NOM
WHITE ELECTRONIC DESIGNS CORP.
Flash
ORGANIZATION, 2M x 64
User configurable as 2 x 2M x 32
3.3V Power supply
ACCESS TIME (ns)
100 = 100ns
120 = 120ns
150 = 150ns
PACKAGE TYPE:
B = 159 Plastic BGA, 13mm x 22mm
DEVICE GRADE:
M = Military Screened
-55C to +125C
I
= Industrial
-40C to +85C
C = Commercial
0C to +70C
15
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
W72M64V-XBX
Document Title
2M x 64 Simultaneous Operation Flash Multi-Chip Package
Revision History
Rev #
History
Release Date
Status
Rev 0
Initial Release
November 2002
Advanced
Rev 1
Update (pg 1, 14, 15)
November 2003
Preliminary
1.1 Change status to preliminary
1.2 Change mechanical drawing to new style
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