White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

W3EG7232S-AD4

-BD4

August 2005
Rev. 4

PRELIMINARY*

256MB 32Mx72 DDR SDRAM UNBUFFERED w/PLL

DESCRIPTION

The W3EG7232S is a 32Mx72 Double Data Rate
SDRAM memory module based on 256Mb DDR SDRAM
components. The module consists of nine 32Mx8 DDR
SDRAMs in 66 pin TSOP packages mounted on a 200
pin FR4 substrate.

Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system ap pli ca tions.

* This product is under development, is not qualifi ed or characterized and is subject to

change without notice.

FEATURES

Double-data-rate

architecture

DDR200, DDR266 and DDR300

· JEDEC design specifi cations

Bi-directional data strobes (DQS)

Differential clock inputs (CK & CK#)

Programmable Read Latency 2,2.5 (clock)

Programmable Burst Length (2,4,8)

Programmable Burst type (sequential & interleave)

Edge aligned data output, center aligned data input

Auto and self refresh

Serial presence detect

Power supply: 2.5V ± 0.2V

JEDEC standard 200 pin SO-DIMM package

· Package height options:

AD4: 35.5 mm (1.38") and
BD4: 31.75 mm (1.25")

NOTE: Consult factory for availability of:

· RoHS compliant products
· Vendor source control options
· Industrial temperature option

OPERATING FREQUENCIES

DDR333 @CL=2.5

DDR266 @CL=2

DDR266 @CL=2.5

DDR200 @CL=2

Clock Speed

166MHz

133MHz

100MHz

CL-t

RCD

-t

2.5-3-3

2-2-2

2.5-3-3

2-2-2

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White Electronic Designs

W3EG7232S-AD4

-BD4

August 2005
Rev. 4

PRELIMINARY

PIN NAMES

PIN CONFIGURATION

A0 A12

Address input (Multiplexed)

BA0-BA1

Bank Select Address

DQ0-DQ63

Data Input/Output

CB0-CB7

Check bits

DQS0-DQS8

Data Strobe Input/Output

CK0

Clock Input

CK0#

Clock Input

CKE0

Clock Enable Input

CS0#

Chip Select Input

RAS#

Row Address Strobe

CAS#

Column Address Strobe

WE#

Write Enable

DQM0-DQM8

Data-In Mask

Power Supply

CCQ

Power Supply for DQS

Ground

REF

Power Supply for Reference

CCSPD

Serial EEPROM Power Supply

SDA

Serial Data I/O

SCL

Serial Clock

SA0-SA2

Address in EEPROM

CCID

Identifi cation Flag

No Connect

Pin

Symbol

Pin

Symbol

Pin

Symbol

Pin

Symbol

REF

101

151

DQ42

REF

102

152

DQ46

DQ19

103

153

DQ43

DQ23

104

154

DQ47

DQ0

DQ24

105

155

DQ4

DQ28

106

156

DQ1

107

157

DQ5

108

158

DQ25

109

159

DQ29

110

160

DQS0

DQS3

111

161

DQM0

DQM3

112

162

DQ2

113

163

DQ48

DQ6

114

164

DQ52

DQ26

115

A10/AP

165

DQ49

DQ30

116

BA1

166

DQ53

DQ3

DQ27

117

BA0

167

DQ7

DQ31

118

RAS#

168

DQ8

119

WE#

169

DQS6

DQ12

120

CAS#

170

DQM6

CB0

121

CS0#

171

DQ50

CB4

122

172

DQ54

DQ9

CB1

123

173

DQ13

CB5

124

174

DQS1

125

175

DQ51

DQM1

126

176

DQ55

DQS8

127

DQ32

177

DQ56

DQM8

128

DQ36

178

DQ60

DQ10

CB2

129

DQ33

179

DQ14

CB6

130

DQ37

180

DQ11

131

181

DQ57

DQ15

132

182

DQ61

CB3

133

DQS4

183

DQS7

CB7

134

DQM4

184

DQM7

CK0

135

DQ34

185

136

DQ38

186

CK0#

137

187

DQ58

138

188

DQ62

139

DQ35

189

DQ59

140

DQ39

190

DQ63

DQ16

141

DQ40

191

DQ20

142

DQ44

192

DQ17

143

193

SDA

DQ21

144

194

SA0

145

DQ41

195

SCL

CKE0

146

DQ45

196

SA1

DQS2

147

DQS5

197

CCSPD

DQM2

148

DQM5

198

SA2

DQ18

A12

149

199

CCID

DQ22

100

A11

150

200

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White Electronic Designs

W3EG7232S-AD4

-BD4

August 2005
Rev. 4

PRELIMINARY

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Value

Units

Voltage on any pin relative to V

, V

OUT

0.5 ~ 3.6

Voltage on V

supply relative to V

, V

CCQ

1.0 ~ 3.6

Storage Temperature

STG

55 ~ +150

°C

Power Dissipation

Short Circuit Current

Note:
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

DC CHARACTERISTICS

0°C T

70°C, V

= 2.5V ± 0.2V

CAPACITANCE

= 25°C, f = 1MHz, V

= 2.5V ± 0.2V

Parameter

Symbol

Min

Max

Unit

Supply Voltage

2.3

2.7

Supply Voltage

CCQ

2.3

2.7

Reference Voltage

REF

1.15

1.35

Termination Voltage

1.15

1.35

Input High Voltage

REF

+ 0.15

CCQ

+ 0.3

Input Low Voltage

0.3

REF

0.15

Output High Voltage

+ 0.76

Output Low Voltage

0.76

Parameter

Symbol

Max

Unit

Input Capacitance (A0-A12)

IN1

Input Capacitance (RAS#,CAS#,WE#)

IN2

Input Capacitance (CKE0,CKE1)

IN3

Input Capacitance (CK0,CK0#)

IN4

5.5

Input Capacitance (CS0#,CS1#)

IN5

Input Capacitance (DQM0-DQM8)

IN6

Input Capacitance (BA0-BA1)

IN7

Data input/output Capacitance (DQ0-DQ63)(DQS)

OUT

Data input/output Capacitance (CB0-CB7)

OUT

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White Electronic Designs

W3EG7232S-AD4

-BD4

August 2005
Rev. 4

PRELIMINARY

SPECIFICATIONS AND TEST CONDITIONS

0°C

70°C, V

CCQ

= 2.5V ± 0.2V, V

= 2.5V ± 0.2V

Parameter

Symbol Conditions

DDR333@

CL=2.5

DDR266@

CL=2, 2.5

DDR200@

CL=2

Units

Max

Operating Current

DD0

One device bank; Active - Precharge; (MIN); DQ,DM and
DQS inputs changing once per clock cycle; Address and
control inputs changing once every two cycles. T

(MIN);

1400

Operating Current

DD1

One device bank; Active-Read-Precharge; Burst = 2;
T

(MIN);T

(MIN); Iout = 0mA; Address and

control inputs changing once per clock cycle.

1805

1715

Precharge Power-Down
Standby Current

DD2P

All device banks idle; Power-down mode; T

(MIN);

CKE=(low)

Idle Standby Current

DD2F

CS# = High; All device banks idle; T

(MIN); CKE = high;

Address and other control inputs changing once per clock
cycle. V

= V

REF

for DQ, DQS and DM.

725

680

Active Power-Down
Standby Current

DD3P

One device bank active; Power-down mode; T

(MIN);

CKE=(low)

270

225

Active Standby Current

DD3N

CS# = High; CKE = High; One device bank; Active-Precharge;
T

RAS

(MAX); T

(MIN); DQ, DM and DQS inputs

changing twice per clock cycle; Address and other control
inputs changing once per clock cycle.

815

725

Operating Current

DD4R

Burst = 2; Reads; Continous burst; One device bank
active;Address andcontrol inputs changing once per clock
cycle; T

(MIN); I

OUT

= 0mA.

1850

1625

Operating Current

DD4W

Burst = 2; Writes; Continous burst; One device bank active;
Address and control inputs changing once per clock cycle;
T

(MIN); DQ,DM and DQS inputs changing twice per

clock cycle.

1850

1625

Auto Refresh Current

DD5

(MIN)

2570

2390

Self Refresh Current

DD6

CKE 0.2V

311

Operating Current

DD7A

Four bank interleaving Reads (BL=4) with auto precharge with
T

(MIN); T

(MIN); Address and control inputs

change only during Active Read or Write commands

3965

3425

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White Electronic Designs

W3EG7232S-AD4

-BD4

August 2005
Rev. 4

PRELIMINARY

DD1

: OPERATING CURRENT : ONE BANK

1. Typical

Case

=2.5V, T=25°C

2. Worst

Case

=2.7V, T=10°C

3. Only one bank is accessed with t

(min), Burst

Mode, Address and Control inputs on NOP edge
are changing once per clock cycle. I

OUT

= 0mA

4. Timing

Patterns

DDR200 (100 MHz, CL=2) : t

CK=

10ns, CL2,

BL=4, t

RCD=

2*t

, t

RAS=

5*t

Read : A0 N R0 N N P0 N A0 N - repeat the
same timing with random address changing;
50% of data changing at every burst

DDR266 (133MHz, CL=2.5) : t

CK=

7.5ns,

CL=2.5, BL=4, t

RCD=

3*t

, t

RC=

9*t

, t

RAS=

5*t

Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst

DDR266 (133MHz, CL=2) : t

=7.5ns, CL=2,

BL=4, t

RCD

=3*t

, t

=9*t

, t

RAS

=5*t

Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst

DDR333 (166MHz, CL=2.5) : t

=6ns, BL=4,

RCD

=10*t

, t

RAS

=7*t

Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst

DD7A

: OPERATING CURRENT : FOUR BANKS

1. Typical

Case

=2.5V, T=25°C

2. Worst

Case

=2.7V, T=10°C

3. Four banks are being interleaved with t

(min),

Burst Mode, Address and Control inputs on NOP
edge are not changing. Iout=0mA

4. Timing

Patterns

DDR200 (100 MHz, CL=2) : t

=10ns, CL2,

BL=4, t

RRD

=2*t

, t

RCD

=3*t

, Read with

Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0
- repeat the same timing with random address
changing; 100% of data changing at every
burst

DDR266 (133MHz, CL=2.5) : t

=7.5ns,

CL=2.5, BL=4, t

RRD

=3*t

, t

RCD

=3*t

Read with Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst

DDR266 (133MHz, CL=2) : t

=7.5ns, CL2=2,

BL=4, t

RRD

=2*t

, t

RCD

=2*t

Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst

DDR333 (166MHz, CL=2.5) : t

=6ns,

BL=4, t

RRD

=3*t

, t

RCD

=3*t

, Read with

Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst

DETAILED TEST CONDITIONS FOR DDR SDRAM I

DD1

& I

DD7A

Legend : A = Activate, R = Read, W = Write, P = Precharge, N = NOP

A (0-3) = Activate Bank 0-3
R (0-3) = Read Bank 0-3

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

W3EG7232S-AD4

-BD4

August 2005
Rev. 4

PRELIMINARY

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS

AC CHARACTERISTICS

SYMBOL

335

262

265

202

UNITS NOTES

PARAMETER

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

Access window of DQs from CK/CK#

-0.7

+0.7

-0.75

+0.75

-0.75

+0.75

-0.75

+0.75

CK high-level width

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

CK low-level width

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

Clock cycle time

CL = 2.5

CK (2.5)

7.5

39, 44

CL = 2

CK (2)

7.5

39, 44

DQ and DM input hold time relative to DQS

0.45

0.5

23, 27

DQ and DM input setup time relative to DQS

0.45

0.5

23, 27

DQ and DM input pulse width (for each input)

DIPW

1.75

Access window of DQS from CK/CK#

DQSCK

-0.6

+0.6

-0.75

+0.75

-0.75

+0.75

-0.75

+0.75

DQS input high pulse width

DQSH

0.35

DQS input low pulse width

DQSL

0.35

DQS-DQ skew, DQS to last DQ valid, per group, per
access

DQSQ

0.45

0.5

0.6

22, 23

Write command to fi rst DQS latching transition

DQSS

0.75

1.25

0.75

1.25

0.75

1.25

0.75

1.25

DQS falling edge to CK rising - setup time

DSS

0.2

DQS falling edge from CK rising - hold time

DSH

0.2

Half clock period

CH,

Data-out high-impedance window from CK/CK#

+0.7

+0.75

16, 36

Data-out low-impedance window from CK/CK#

-0.7

-0.75

16, 36

Address and control input hold time (slow slew rate)

IHS

0.80

0.90

1.1

Address and control input setup time (slow slew rate)

ISS

0.80

0.90

1.1

Address and Control input pulse width (for each input)

IPW

2.2

LOAD MODE REGISTER command cycle time

MRD

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White Electronic Designs

W3EG7232S-AD4

-BD4

August 2005
Rev. 4

PRELIMINARY

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Continued)

AC CHARACTERISTICS

SYMBOL

335

262

265

202

UNITS NOTES

PARAMETER

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

DQ-DQS hold, DQS to fi rst DQ to go nonvalid, per
access

HP -

QHS

HP -

QHS

HP -

QHS

HP -

QHS

22, 23

Data Hold Skew Factor

QHS

0.5

0.75

ACTIVE to PRECHARGE command

RAS

70,000

120,000

31, 47

ACTIVE to READ with Auto precharge command

RAP

ACTIVE to ACTIVE/AUTO REFRESH command
period

AUTO REFRESH command period

RFC

ACTIVE to READ or WRITE delay

RCD

PRECHARGE command period

DQS read preamble

RPRE

0.9

1.1

0.9

1.1

0.9

1.1

0.9

1.1

DQS read postamble

RPST

0.4

0.6

0.4

0.6

0.4

0.6

0.4

0.6

ACTIVE bank a to ACTIVE bank b command

RRD

DQS write preamble

WPRE

0.25

DQS write preamble setup time

WPRES

18, 19

DQS write postamble

WPST

0.4

0.6

0.4

0.6

0.4

0.6

0.4

0.6

Write recovery time

Internal WRITE to READ command delay

WTR

Data valid output window (DVW)

QH -

DQSQ

QH -

DQSQ

REFRESH to REFRESH command interval

REFC

70.3

µs

Average periodic refresh interval

REFI

7.8

µs

Terminating voltage delay to V

VTD

Exit SELF REFRESH to non-READ command

XSNR

Exit SELF REFRESH to READ command

XSRD

200

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White Electronic Designs

W3EG7232S-AD4

-BD4

August 2005
Rev. 4

PRELIMINARY

Notes
1.

All voltages referenced to V

2. Tests

for

timing,

, and electrical AC and DC characteristics may be

conducted at nominal reference/supply voltage levels, but the related specifi cations
and device operation are guaranteed for the full voltage range specifi ed.

Outputs measured with equivalent load:

Output

Output
(V

OUT

)

Reference

Point

30pF

AC timing and I

tests may use a V

-to-V

swing of up to 1.5V in the test

environment, but input timing is still referenced to V

REF

(or to the crossing point for

CK/CK#), and parameter specifi cations are guaranteed for the specifi ed AC input
levels under normal use conditions. The mini-mum slew rate for the input signals
used to test the device is 1V/ns in the range between V

(AC) and V

(AC).

The AC and DC input level specifi cations are as defi ned in the SSTL_2 Standard
(i.e., the receiver will effectively switch as a result of the signal crossing the AC
input level, and will remain in that state as long as the signal does not ring back
above [below] the DC input LOW [HIGH] level).

6. V

REF

is expected to equal V

CCQ/2

of the transmitting device and to track variations

in the DC level of the same. Peak-to-peak noise (non-common mode) on Vref may
not exceed ±2 percent of the DC value. Thus, from V

CCQ/2

, Vref is allowed ±25mV

for DC error and an additional ±25mV for AC noise. This measurement is to be
taken at the nearest V

REF

bypass capacitor.

7. V

is not applied directly to the device. V

is a system supply for signal

termination resistors, is expected to be set equal to V

REF

and must track variations

in the DC level of V

REF

8. I

is dependent on output loading and cycle rates. Specifi ed values are obtained

with mini-mum cycle time at CL = 2 for 262 and 202, CL = 2.5 for 335 and 265 with
the outputs open.

Enables on-chip refresh and address counters.

10. I

specifi cations are tested after the device is properly initialized, and is averaged

at the defi ned cycle rate.

11. This parameter is sampled. V

= +2.5V ±0.2V, V

Q = +2.5V ±0.2V, V

REF

= V

f = 100 MHz, TA = 25°C, V

OUT

(DC) = V

CCQ

/2, V

OUT

(peak to peak) = 0.2V. DM input

is grouped with I/O pins, refl ecting the fact that they are matched in loading.

12. For slew rates < 1 V/ns and to 0.5 Vns. If the slew rate is < 0.5V/ns, timing must

be derated: tIS has an additional 50ps per each 100 mV/ns reduction in slew
rate from 500 mV/ns, while t

is unaffected. If the slew rate exceeds 4.5 V/ns,

functionality is uncertain. For 335, slew rates must be 0.5 V/ns.

13. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at

which CK and CK# cross; the input reference level for signals other than CK/CK# is
V

REF

14. Inputs are not recognized as valid until V

REF

stabilizes. Exception: during the period

before V

REF

stabilizes, CKE < 0.3 x V

CCQ

is recognized as LOW.

15. The output timing reference level, as measured at the timing reference point

indicated in Note 3, is V

16. t

and t

transitions occur in the same access time windows as data valid

transitions. These parameters are not referenced to a specifi c voltage level, but
specify when the device output is no longer driving (HZ) or begins driving (LZ).

17. The intent of the Don't Care state after completion of the postamble is the DQS-

driven signal should either be high, low, or high-Z and that any signal transition
within the input switching region must follow valid input requirements. That is, if
DQS transitions high [above V

IHDC

(MIN)] then it must not transition low (below

IHDC

) prior to t

DQSH

(MIN).

18. This is not a device limit. The device will operate with a negative value, but system

performance could be degraded due to bus turnaround.

19. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE

command. The case shown (DQS going from High-Z to logic LOW) applies when
no WRITEs were previously in progress on the bus. If a previous WRITE was in
progress, DQS could be HIGH during this time, depending on t

DQSS

20. MIN

or t

RFC

) for I

measurements is the smallest multiple of t

that meets

the minimum absolute value for the respective parameter. t

RAS

(MAX) for I

measurements is the largest multiple of t

that meets the maximum absolute value

for t

RAS

21. The refresh period 64ms. This equates to an average refresh rate of 7.8251µs.

However, an AUTO REFRESH command must be asserted at least once every
70.3µs; burst refreshing or posting by the DRAM controller greater than eight
refresh cycles is not allowed.

22. The valid data window is derived by achieving other specifi cations: t

CK/2

), t

DQSQ

and t

= t

- t

QHS

). The data valid window derates in direct porportion with

the clock duty cycle and a practical data valid window can be derived, as shown in
Figure 7, Derating Data Valid Window. The clock is allowed a maximum duty cycle
variation of 45/55, beyond which functionality is uncertain. The data valid window
derating curves are provided below for duty cycles ranging between 50/50 and
45/55.

23. Each byte lane has a corresponding DQS.
24. This limit is actually a nominal value and does not result in a fail value. CKE is

HIGH during REFRESH command period (t

RFC

[MIN]) else CKE is LOW (i.e., during

standby).

25. To maintain a valid level, the transitioning edge of the input must:

a. Sustain a constant slew rate from the current AC level through to the target AC

level, V

(AC) or V

(AC).

b. Reach at least the target AC level.

c. After the AC target level is reached, continue to maintain at least the target DC

level, V

(DC) or V

(DC).

26. JEDEC specifi es CK and CK# input slew rate must be 1V/ns (2V/ns

differentially).

27. DQ and DM input slew rates must not deviate from DQS by more than 10 percent.

If the DQ/DM/DQS slew rate is less than 0.5 V/ns, timing must be derated: 50ps
must be added to t

and t

for each 100 mv/ns reduction in slew rate. If slew rate

exceeds 4 V/ns, functionality is uncertain. For 335, slew rates must be 0.5 V/ns.

28. V

must not vary more than 4 percent if CKE is not active while any bank is active.

29. The clock is allowed up to ±150ps of jitter. Each timing parameter is allowed to vary

by the same amount.

30. t

min is the lesser of t

minimum and t

minimum actually applied to the device

CK and CK# inputs, collectively during bank active.

31. READs and WRITEs with auto precharge are not allowed to be issued until

RAS

(min) can be satisfi ed prior to the internal precharge command being issued.

32. Any positive glitch must be less than 1/3 of the clock and not more than +400mV or

2.9V, whichever is less. Any negative glitch must be less than 1/3 of the clock cycle
and not exceed either - 300mV or 2.2V, whichever is more positive.

33. The voltage levels used are derived from a mini-mum V

level and the referenced

test load. In practice, the voltage levels obtained from a properly terminated bus will
provide signifi cantly different voltage values.

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

W3EG7232S-AD4

-BD4

August 2005
Rev. 4

PRELIMINARY

34. V

overshoot: V

(MAX) = V

CCQ

+ 1.5V for a pulse width 3ns and the pulse width

can not be greater than 1/3 of the cycle rate. V

undershoot: V

(MIN) = -1.5V for a

pulse width 3ns and the pulse width can not be greater than 1/3 of the cycle rate.

35. V

and V

CCQ

must track each other.

36. t

(MAX) will prevail over t

DQSCK

(MAX) + t

RPST

(MAX) condition. t

(MIN) will

prevail over t

DQSCK

(MIN) + t

RPRE

(MAX) condition.

37. t

RPST

end point and t

RPRE

begin point are not referenced to a specifi c voltage level

but specify when the device output is no longer driving (t

RPST

), or begins driving

RPRE

39. During

initialization,

CCQ

, V

, and V

REF

must be equal to or less than V

+ 0.3V.

Alternatively, V

may be 1.35V maximum during power up, even if V

CCQ

are

0Vs, provided a minimum of 42 0 of series resistance is used between the V

supply and the input pin.

40. The current part operates below the slowest JEDEC operating frequency of 83

MHz. As such, future die may not refl ect this option.

41. Random addressing changing and 50 percent of data changing at every transfer.

42. Random addressing changing and 100 percent of data changing at every transfer.
43. CKE must be active (high) during the entire time a refresh command is executed.

That is, from the time the AUTO REFRESH command is registered, CKE must be
active at each rising clock edge, until t

REF

later.

44. I

DD2N

specifi es the DQ, DQS, and DM to be driven to a valid high or low logic level.

DD2Q

is similar to I

DD2F

except I

DD2Q

specifi es the address and control inputs to

remain stable. Although I

DD2F

, I

DD2N

, and I

DD2Q

are similar, I

DD2F

is "worst case."

45. Whenever the operating frequency is altered, not including jitter, the DLL is required

to be reset. This is followed by 200 clock cycles.

46. Leakage number refl ects the worst case leakage possible through the module pin,

not what each memory device contributes.

47. When an input signal is HIGH or LOW, it is defi ned as a steady state logic HIGH or

LOW.

48. The 335 speed grade will operate with t

RAS

(MIN) = 40ns and t

RAS

(MAX) =

120,000ns at any slower frequency.

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