1
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
November 2000, Rev. 1
ECO #13417
EDI2DL32256V
DESCRIPTION
The EDI2DL32256VxxBC is a 3.3V, 256Kx32 Synchronous Pipeline
Burst SRAM constructed with two 256Kx16 die mounted on a
multi-layer laminate substrate. The device is packaged in a 119
lead, 14mm by 22mm, BGA. It is available with clock speeds of166,
150 and 133 MHz. The device is a Pipeline Burst SRAM, allowing
the user to develop a fast external memory for Texas Instruments'
"C6x". In Burst Mode data from the first memory location is
available in three clock cycles, while the subsequent data is
available in one clock cycle (3/1/1/1). Subsequent burst ad-
dresses are generated by the TMS320C6x DSP. Individual address
locations can also be read, allowing one memory access in 3 clock
cycles. All synchronous inputs are gated by registers controlled by
a positive-edge-triggered clock input (CLK). The synchronous in-
puts include all addresses, all data inputs, chip enable (CE\), burst
control input (ADSC\), byte write enables (BW0\ to BW3\) and
Write Enable (BWE\).
Asynchronous inputs include the output enable (OE\), burst mode
control (MODE), and sleep mode control (ZZ). The data outputs
(DQ), enabled by OE\, are also asynchronous.
Address lines and the chip enable are registered with the address
status controller (ADSC\) input pin.
256Kx32 Synchronous Pipline Burst SRAM 3.3V
FEATURES
s t
KHQV
times of 3.5, 3.8 and 4.0ns
s 166, 150 and 133 MHz clock speed
s DSP Memory Solution
Texas Instruments' TMS320C6201
Texas Instruments' TMS320C67x
s Package:
119 pin BGA, JEDEC MO-163
s 3.3V Operating Supply Voltage
s 3.5ns Output Enable access time
s Single Write Control and Output Enable Lines
s Single Chip Enable Line
s 56% space savings vs. monolithic TQFPs
s Multiple VCC and VSS pins
s Reduced inductance and capacitance
BLOCK DIAGRAM
FIG. 1
1
2
3
4
5
6
7
A
V
DD
A
A
NC
A
A
V
DD
A
B
NC
NC
A
ADSC\
A
A
NC
B
C
NC
A
A
V
DD
A
A
NC
C
D
DQ
16
NC
V
SS
NC
V
SS
NC
DQ
8
D
E
DQ
18
DQ
17
V
SS
CE\
V
SS
DQ
9
DQ
10
E
F
V
DD
DQ
19
V
SS
OE\
V
SS
DQ
11
V
DD
F
G
DQ
21
DQ
20
BE
2
\
NC
BE
1
\
DQ
12
DQ
13
G
H
DQ
23
DQ
22
V
SS
NC
V
SS
DQ
14
DQ
15
H
J
V
DD
V
DD
NC
V
DD
NC
V
DD
V
DD
J
K
DQ
31
DQ
30
V
SS
CLK
V
SS
DQ
6
DQ
7
K
L
DQ
29
DQ
28
BE
3
\
NC
BE
0
\
DQ
4
DQ
5
L
M
V
DD
DQ
27
V
SS
BWE\
V
SS
DQ
3
V
DD
M
N
DQ
26
DQ
25
V
SS
A
1
V
SS
DQ
1
DQ
2
N
P
DQ
24
NC
V
SS
A
0
V
SS
NC
DQ
0
P
R
NC
A
MODE
V
DD
NC
A
NC
R
T
NC
NC
A
A
A
NC
ZZ
T
U
V
DD
NC
NC
NC
NC
NC
V
DD
U
1
2
3
4
5
6
7
PIN CONFIGURATION
A
0
-
17
CLK
ADSC\
OE\
BWE\
CE\
MODE
ZZ
BE
0
\
BE
1
\
BE
2
\
BE
3
\
256K X 16
SSRAM
256K X 16
SSRAM
DQ
0
-
7
DQ
8
-
15
DQ
16
-
23
DQ
24
-
31
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White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
November 2000, Rev. 1
ECO #13417
EDI2DL32256V
PIN DESCRIPTIONS
Pin
Symbol
Type
Description
Various
A
0-17
Input
Addresses: These inputs are registered and must meet setup and hold times around the rising edge
Synchronous
of CLK.
L5,G5
BE0\,BE1\,
Input
Byte Write: A byte write is LOW for a WRITE cycle and HIGH for a READ BE2\, BE3\ cycle. BE0\ controls
G3,L3
BE2\,BE3\
Synchronous
DQ0-7. BE1\ controls DQ8-15. BE2\ controls DQ16-23. BE3\ controls DQ24-31
M4
BWE\
Input
Byte Write Enable: This active LOW input gates byte write operations and must meet the setup and hold
Synchronous
times around the rising edge of CLK.
K4
CLK
Input
Clock:This signal registers the addresses, data, chip enables, write control and burst control inputs on
Synchronous
its rising edge. All synchronous inputs must meet setup and hold times around the clocks rising edge.
E4
CE\
Input
Chip Enable: This active LOW inputs is used to enable the device.
Synchronous
F4
OE\
Input
Output Enable: This active LOW asynchronous input enables the data output drivers
B4
ADSC\
Input
Address Status Controller: This active LOW input causes device to be deselected or selected along with new
Synchronous
external address to be registered. A READ or WRITE cycle is initiated depending upon write control inputs.
R3
MODE
Input
Static Mode: This input selects the burst sequence. A LOW on this pin selects LINEAR BURST. A NC or
HIGH on this pin selects INTERLEAVED BURST.
T7
ZZ
Input
Snooze: This active HIGH input puts the device in low power consumption standby mode. For normal
Synchronous
operation, this input has to be either LOW or NC (no connect)
Various
DQ
0-31
Input/Output
Data Inputs/Outputs: First byte is DQ
0-7
, second byte is DQ
8-15
, third byte is DQ
16-23
, fourth byte is DQ
24-31
Various
Vcc
Supply
Core power supply: +3.3V -5%/+5%
Various
Vss
Ground
Ground
Operation
Address Used
CE\
ADSC\
WRITE\
OE\
DQ
Deselected Cycle, Power Down
None
H
L
X
X
High-Z
WRITE Cycle, Begin Burst
External
L
L
L
X
D
READ Cycle, Begin Burst
External
L
L
H
L
Q
READ Cycle, Begin Burst
External
L
L
H
H
High-Z
READ Cycle, Suspend Burst
Current
X
H
H
L
Q
READ Cycle, Suspend Burst
Current
X
H
H
H
High-Z
READ Cycle, Suspend Burst
Current
H
H
H
L
Q
READ Cycle, Suspend Burst
Current
H
H
H
H
High-Z
WRITE Cycle, Suspend Burst
Current
X
H
L
X
D
WRITE Cycle, Suspend Burst
Current
H
H
L
X
D
NOTE:
1. X means dont care, H means logic HIGH. L means logic LOW.
2a.WRITE\ = L, means [BE0\*BE1\*BE2\*BE3\]*BWE\ equals LOW
2b.WRITE\ = H, means [BE0\*BE1\*BE2\*BE3\]*BWE\ equals HIGH
3. All inputs except OE\ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
4. Suspending burst generates wait cycle
5. For a write operation following a read operation, OE\ must be HIGH before the input data required setup time plus High-Z time for OE\ and staying HIGH though
out the input data hold time.
6. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
TRUTH TABLE
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White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
November 2000, Rev. 1
ECO #13417
EDI2DL32256V
RECOMMENDED OPERATING CONDITIONS
Description
Symbol
Min
Max
Unit
Input High Voltage
V
IH
2
Vcc+0.3
V
Input Low Voltage
V
IL
-0.3
0.7
V
Supply Voltage
Vcc
3.135
3.465
V
CAPACITANCE
(f = 1MHz, V
IN
= V
CC
or V
SS
)
Voltage on Vcc Supply Relative to Vss
-0.5V to 4.6V
V
IN
-0.5V to Vcc+0.5V
Storage Temperature
-55
C to +110
C
Junction Temperature
+110
C
Power Dissipation
3 Watts
Short Circuit Output Current (per I/O)
20 mA
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions greater than those indi-
cated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Parameter
Symbol
Max
Unit
Address Lines
C
A
TBD
pF
Data Lines
C
D/Q
TBD
pF
Control Lines
C
C
TBD
pF
ABSOLUTE MAXIMUM RATINGS*
DC ELECTRICAL CHARACTERISTICS
(f = 1MHz, V
IN
= V
CC
or Vss)
Parameter
Symbol
Conditions
Min
Max
Units
Power Supply Current: Operating
I
CC1
Device Selected; all inputs
V
IL
or
V
IH
;
850
mA
cycle time
t
KC
MIN; V
CC
= MAX; outputs open
Device deselected; V
CC
= MAX; all inputs
CMOS Standby
I
SB2
V
SS
+0.2 or
V
CC
-0.2; all inputs static;
20
mA
CLK frequency = 0
TTL Standby
I
SB3
Device deselected; all inputs
V
IL
or
V
IH
;
40
mA
all inputs static; V
CC
= MAX; CLK frequency = 0
TTL Standby
I
SB4
Device deselected; all inputs
V
IL
or
V
IH
;
40
mA
V
CC
= MAX; CLK cycle time
t
CK
MIN
Input Leakage Current
IL
I
0V < V
IN
< V
CC
-2
2
A
Output Leakage Current
IL
O
Output(s) disabled, 0V
V
OUT
V
CC
-2
2
A
Output High Voltage
V
OH
I
OH
= -2.0mA
2.4
V
Output Low Voltage
V
OL
I
OL
= 2.0mA
0.7
V
AC TEST CIRCUIT
AC TEST CONDITIONS
50
Vt = 1.5V
Output
Z0 = 50
Z0 = 50
Parameter
I/O
Unit
Input Pulse Levels
V
SS
to 2.5
V
Input Rise and Fall Times (max)
1.8
ns
Input and Output Timing Levels
1.25
V
Output Load
See figure, at left
AC Output Load Equivalent
1.25V
PARTIAL TRUTH TABLE
Function
BWE\
BE0\
BE1\
BE2\
BE\3
READ
H
X
X
X
X
WRITE one Byte (DQ
0-7
)
L
L
H
H
H
WRITE all Bytes
L
L
L
L
L
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White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
November 2000, Rev. 1
ECO #13417
EDI2DL32256V
AC ELECTRICAL CHARACTERISTICS
Symbol
3.5ns
3.8ns
4.0ns
Description
Min
Max
Min
Max
Min
Max
Units
Clock
Clock cycle time
t
KHKH
6
6.7
7.5
Clock HIGH time
t
KHKL
2.4
2.6
2.8
Clock LOW time
t
KLKH
2.4
2.6
2.8
Output Times
Clock to output valid
t
KHQV
3.5
3.8
4.0
Clock to output in Low-Z
t
KHQX
0
0
0
Clock to output in High-Z
t
KHQZ
1.5
6
1.5
6.7
1.5
7.5
OE to output valid
t
OELQV
3.5
3.5
3.8
OE to output in Low-Z
t
OELQX
0
0
0
OE to output in High-Z
t
OEHQZ
3.5
3.5
3.8
Setup Times
Address Status Controller valid to Clock
t
SCVKH
1.5
1.5
1.5
Address valid to Clock
t
AVKH
1.5
1.5
1.5
Chip Enable valid to Clock
t
EVKH
1.5
1.5
1.5
Write Enable (BWE\) valid to Clock
t
WLKH
1.5
1.5
1.5
Data Valid to Clock
t
DVKH
1.5
1.5
1.5
Hold Times
Address Status Controller Hold time
t
KHSCX
0.5
0.5
0.5
Address Hold time
t
KHAX
0.5
0.5
0.5
Chip Enable Hold time
t
KHEX
0.5
0.5
0.5
Write Enable (BWE\) Hold time
t
KHWX
0.5
0.5
0.5
Data Hold time
t
KHDX
0.5
0.5
0.5
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White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
November 2000, Rev. 1
ECO #13417
EDI2DL32256V
FIG. 2
READ TIMING
CLK
WRITE\
t
KHKL
t
KLKH
t
KHKH
CE\
t
KHEX
ADSC\
t
EVKH
t
SC VKH
t
KHSC X
DQ
t
KHQ Z
t
KHQ X
Q(A1)
Q(A2)
Q(A3)
Q(A4)
t
KHQ V
Q(A5)
A5
ADDR
t
AVKH
t
KHAX
A1
A2
A3
A4
OE\
t
OELQ V
t
OELQ X
t
OEHQZ
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