VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC8121
2.488GHz SONET/SDH
Clock Generator
G52163-0, Rev 4.2
Page 1
04/16/01
VITESSE
SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Features
General Description
The VSC8121 is a monolithic Phase Locked Loop (PLL) based clock generator designed for telecommuni-
cations systems operating at 2.5Gb/s. The VSC8121 incorporates a reactance-based (LC) Voltage Controlled
Oscillator (VCO) with low phase noise. The PLL's loop filter is on-chip.
The device has a differential 2.488GHz CML clock output (CO/CON) signal, a single-ended TTL low-
speed clock (LSCLK) output equivalent in frequency to that of the reference clock, and a TTL reference clock
input selectable for 51.84MHz, 77.76MHz or 155.52MHz. TTL inputs REFSEL[0:1] are used to make this
selection.
A clean REFCLK signal is required since jitter below the PLL loop bandwidth, which is present on the
REFCLK input, will appear on the output. Jitter on REFCLK at frequencies above the loop bandwidth will be
attenuated by the PLL. The state of REFSEL[0:1] will select which frequency is expected on the REFCLK
input.
VSC8121 Functional Block Diagram
Monolithic Phase Locked Loop
On-Chip LC Oscillator
On-Chip Loop Filter
TTL/CMOS Reference Clock
Selectable Reference
Jitter Meets SONET OC-48 and
SDH STM-16 Requirements
High-Speed CML Clock Output
Single 3.3V Supply
Compact 10mm x 10mm 44 Pin PQFP Package
REFCLK
LSCLK
CO
CON
Ph.Freq.
Detector
Loop
Filter
CLOCK
OUT
VCO
Divider
REFSEL[0:1]
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC8121
2.488GHz SONET/SDH
Clock Generator
Page 2
G52163-0, Rev 4.2
04/16/01
VITESSE
SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Applications Information
High-Speed Clock Output
The differential clock output waveforms produced by the VSC8121 are sinusoidal in nature, by design. This
typically results in less noise generation than square pulses in most customer applications. Figure 1 shows a typ-
ical, single-ended clock output waveform produced by the device.
Figure 1: Typical Clock Output (CO) Waveform
CO and CON are high-speed CML outputs. As shown in Figure 2, the output driver consists of a differential
pair designed to drive a 50
transmission line environment. Note that the output driver is back terminated to
50
on-chip to prevent reflections.
Careful layout of these signals is required for optimal performance. Figure 3 demonstrates various termina-
tion methods that may be employed, depending on the particular application. Either DC-coupling (termination
#1 in Figure 3) or one of two AC coupling methods (terminations #2 and #3) may be used. As indicated, Vitesse
recommends termination #2 for AC-coupling.
100ps/div
75mV/div
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC8121
2.488GHz SONET/SDH
Clock Generator
G52163-0, Rev 4.2
Page 3
04/16/01
VITESSE
SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Figure 2: High-Speed Clock Output Diagram
Figure 3: Example High-Speed CML Clock Output Terminations
V
EE
V
CC
Pre-Driver
CON
CO
50
50
50
CO/CON
CO/CON
CO/CON
V
CC
50
V
TERM
0.01
f
50
V
TERM
0.01
f
1)
2)
3)
(Recommended for DC-Coupling)
(Recommended for AC-Coupling)
(Alternative for AC-Coupling)
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC8121
2.488GHz SONET/SDH
Clock Generator
Page 4
G52163-0, Rev 4.2
04/16/01
VITESSE
SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Reference Clock Input
The input stage at the REFCLK input pin consists of ESD protection, followed by a current limiting circuit
which precedes a driver responsible for providing the signal to the phase frequency detector. As pictured below
in Figure 4, the driver has a high impedance, FET gate input. The additional resistance contributed by the cur-
rent limiting circuit is relatively negligible.
Figure 4: Reference Clock Input Diagram
Care should be taken in selection of the reference clock. Time jitter on the reference clock which is within
the PLL's loop bandwidth will appear on the 2.5GHz output. Telecom quality crystal oscillators from vendors
such as Connor-Winfield or Vectron are suitable.
Table 1: Reference Clock Selection
Die Usage
Vitesse optionally provides this device in unpackaged, die-only format for multi-chip module and related
applications. For further informtion, please contact Vitesse.
REFSEL[1]
REFSEL[0]
Selected Reference
Frequency
Typical
Loop Bandwidth
0
0
51.84MHz
2500KHz
1
0
77.76MHz
3000KHz
Don't Care
1
155.52MHz
5500KHz
VTT
VEE
VCC
REFCLK
Current
Limiting
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC8121
2.488GHz SONET/SDH
Clock Generator
G52163-0, Rev 4.2
Page 5
04/16/01
VITESSE
SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com
Internet: www.vitesse.com
AC Characteristics
Table 2: AC Characteristics
NOTE: (1) ppm refers to "parts per million." 100ppm (100/1000000) is equivalent to 0.01%. Therefore, the equivalent reference
clock frequency range in MHz for +/-100ppm tolerance is as follows:
Note that +/-100ppm tolerance for reference clock frequency more than accommodates the SONET/SDH requirement that refer-
ence clock-supplying crystals function at +/-20ppm.)
Figure 5: RMS/Peak-to-Peak Jitter (12kHz - 20MHz), REF_CLK freq = 77.76MHz
Parameter
Description
Min
Typ
Max
Units
Conditions
T
CLK
High-speed output clock period
--
401.9
--
ps
RC
d
Reference clock duty cycle
45
--
55
%
RC
f
Reference clock frequency (selectable)
--
51.84,
77.76,
or
155.52
--
MHz
f
RC
Reference clock frequency tolerance
-100
--
+100
ppm
(1)
t
jitter
Jitter generation
--
1.75
3.6
ps RMS
12kHz to 20MHz.
See Figure 5.
RC
f
X 100ppm =
Acceptable Range
51.84MHz
5.184KHz
51.83MHz to 51.85MHz
77.76MHz
7.776KHz
77.75MHz to 77.78MHz
155.52MHz
15.552KHz
155.51MHz to 155.54MHz
0
20
40
60
80
100
3.0
2.5
2.0
1.5
1.0
0.5
0.0
Case Temperature (deg C)
ps
0
20
40
60
80
100
25
20
15
10
5
0
Case Temperature (deg C)
ps
RMS Jitter
Pk-Pk Jitter
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