VITESSE
SEMICONDUCTOR CORPORATION
G52293-0, Rev 2.3
Page 1
05/07/01
VITESSE
SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Advance Product Information
VSC7124
Quad Port Bypass Circuit
Features
General Description
The VSC7124 contains five cascaded Port Bypass Circuits (PBCs) used to steer serial signals. This part is typ-
ically used in distributing Fibre Channel signals to an array of disk drives in an FC-AL loop as illustrated in Fig-
ure 1. The VSC7124 can be used with any of the Vitesse JBOD circuits to implement FC-AL JBODs of
virtually any size. In Figure 1, the first VSC7127's CRU is configured as a Repeater to attenuate jitter. The
VSC7124 does not contain a CRU in order to reduce power and cost. The second VSC7127's CRU is config-
ured as a retimer so that the output of the device is a jitter compliance point.
Each PBC is a multiplexer that is controlled by the corresponding SELx line which, if HIGH, selects the exter-
nal input or, if LOW, selects the output of the previous PBC.
VSC7124 Block Diagram
ANSI X3T11 Fibre Channel Compliant at 1.0625Gb/s
IEEE 802.3z Gigabit Ethernet Compliant at 1.25Gb/s
Five Port Bypass Circuits (PBCs)
On-Chip Transmit Termination
3.3V, 0.25W Typical Power
0.35um CMOS, a Velocity Family Member
44-Pin, 10mm PQFP Package
I1+
I1-
O1-
SEL
1
1
0
PBC1
I2+
I2-
O2+
O2-
SEL
2
1
0
PBC2
I3+
I3-
O3+
O3-
SEL
3
1
0
PBC3
I4+
I4-
O4+
O4-
SEL
4
1
0
PBC4
O1
+
I0+
I0-
O0+
O0-
SEL0
1
0
PBC0
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7124
Quad Port Bypass Circuit
Page 2
G52293-0, Rev 2.3
5/7/01
VITESSE
SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Application Example
A 12-port JBOD is shown in Figure 1. This dual loop application uses one VSC7127R, one VSC7127T and one
VSC7124 on each loop in order to configure the FC-AL disk array. Functional drives are included in the FC-
AL loop while nonfunctional or missing drives (numbers 2, 7, 9) are excluded.
Figure 1: 12-Drive FC-AL JBOD Application
VS
C7
127
R #1
VSC7
12
7R #
2
VSC
712
4 #
3
VS
C71
24 #4
7125
V
S
C7
12
1
QUAD PORT
BY
P
A
SS
CIRC
U
I
T
Optics
or
Copper
SerDes
7125
SerDes
1
0
1
0
1
0
1
0
7125
SerDes
7125
SerDes
1
0
1
0
7125
SerDes
7125
SerDes
1
0
1
0
7125
SerDes
7125
SerDes
1
0
1
0
7125
SerDes
7125
SerDes
1
0
1
0
1
0
1
0
7125
SerDes
7125
SerDes
1
0
1
0
1
0
1
0
7125
SerDes
7125
SerDes
1
0
1
0
7125
SerDes
7125
SerDes
1
0
1
0
7125
SerDes
7125
SerDes
1
0
1
0
Repeater
Retimer
Retimer
Repeater
VSC
712
7T
#5
1
2
3
4
5
6
7
8
9
10
11
12
VSC
7
1
27T
#6
Optics
or
Copper
LOOP A
LOOP B
CONFIGURATION:
VSC7127R #1 & 2: Repeater Mode
SEL0=1, SEL5=1
VSC7127T #5 & 6: Retimer Mode
SEL1=1, SEL5=1
MODE=0
MODE=1
VSC7124 #3 & 4: No CRU
0
1
2
3
4
0
0
1
2
3
4
0
1
1
2
3
4
0
VITESSE
SEMICONDUCTOR CORPORATION
G52293-0, Rev 2.3
Page 3
05/07/01
VITESSE
SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Advance Product Information
VSC7124
Quad Port Bypass Circuit
Figure 2: Timing Waveforms
AC Characteristics
(Over Recommended Operating Conditions)
DC Characteristics
(Over Recommended Operating Conditions)
NOTE: (1) Refer to Application Note AN-37 for details regarding differential voltage measurements.
Parameters
Description
Min
Typ
Max
Units
Conditions
T
1
Propagation Delay
7.0
ns
Delay with all circuits
bypassed.
T
R
, T
F
Serial Data Rise and Fall Time
300
ps
At
V
IN
minimum levels
T
j(PBC)
Data Jitter Accummulation
120
ps
Peak-to-Peak on Ox+/-
Parameters
Description
Min
Typ
Max
Units
Conditions
V
OH
Output HIGH voltage (TTL)
2.4
V
I
OH
= -1.0 mA
V
OL
Output LOW voltage (TTL)
0.5
V
I
OL
= +1.0 mA
V
IH
Input HIGH voltage (TTL)
2.0
5.5
V
V
IL
Input LOW voltage (TTL)
0
0.8
V
I
IH
Input HIGH current (TTL)
50
500
A
V
IN
=2.4V
I
IL
Input LOW current (TTL)
-500
A
V
IN
=0.5V
V
OUT75
(1)
TX output differential peak-to-peak
voltage swing
1200
2200
mVp-p
75
to V
DD
2.0 V
V
OUT50
(1)
TX output differential peak-to-peak
voltage swing
1000
2200
mVp-p
50
to V
DD
2.0 V
V
IN
(1)
Receiver differential peak-to-peak
Input Sensitivity RX
400
2600
mVp-p
Internally biased to V
DD
/2
V
DD
Supply voltage
3.14
3.47
V
3.3V5%
P
D
Power dissipation
250
555
mW
Outputs open,
V
DD
= V
DD
max 2%
I
DD
Power Supply Current
76
160
mA
Outputs open,
V
DD
= V
DD
max
T
1
T
1
Ox+/-
Ix+/-
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7124
Quad Port Bypass Circuit
Page 4
G52293-0, Rev 2.3
5/7/01
VITESSE
SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Absolute Maximum Ratings
(1)
TTL Power Supply Voltage (V
DD
) ...................................................................................................... 0.5V to +4V
PECL DC Input Voltage (V
INP
) ............................................................................................. -0.5V to V
DD
+0.5V
TTL DC Input Voltage, (V
INT
).......................................................................................................... -0.5V to 5.5V
DC Voltage Applied to Outputs for High Output State (V
IN TTL
) ........................................ -0.5V to V
DD
+ 0.5V
TTL Output Current (I
OUT
), (DC, Output High)........................................................................................... 50mA
PECL Output Current (I
OUT
), (DC, Output High) ....................................................................................... -50mA
Case Temperature Under Bias, (T
C
)............................................................................................. -55
C to +125
C
Storage Temperature (T
STG
)........................................................................................................ -65
C to + 150
C
Recommended Operating Conditions
(2)
Power Supply Voltage (V
DD
) . ......................................................................................................+3.14V to 3.47V
Ambient Operating Temperature Range (T)....................................................................... 0
C to +85
C Ambient
NOTES: (1) CAUTION: Stresses listed under "Absolute Maximum Ratings" may be applied to devices one at a time without caus-
ing permanent damage. Functionality at or above the values listed is not implied. Exposure to these values for extended
periods may affect device reliability.
(2) Vitesse guarantees the functional and parametric operation of the part under "Recommended Operating Conditions"
except where specifically noted in the AC and DC Parametric tables.
VITESSE
SEMICONDUCTOR CORPORATION
G52293-0, Rev 2.3
Page 5
05/07/01
VITESSE
SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Advance Product Information
VSC7124
Quad Port Bypass Circuit
Package Pin Descriptions
Figure 3: Pin Diagram
Table 1: Pin Identifications
Pin #
Name
Description
4, 3, 41, 40
35, 34, 28, 27
10, 9
I1+, I1-, I2+, I2-
I3+, I3-, I4+, I4-
I0+, I 0-
INPUT - Differential, Internally Biased to V
DD
/2
Ix+/Ix- is the serial input to PBCx.
15, 16,
17, 18
14
SEL1, SEL2
SEL3, SEL4
SEL0
INPUT - TTL
Port Bypass Mux SELect lines. A HIGH selects Ix. A LOW selects the
output of the previous internal device.
7, 6, 44, 43
38, 37, 31, 30
24, 25
O1+, O1-, O2+, O2-
O3+, O3-, O4+, O4-
O0+, O0-
OUTPUT - Differential
Ox+/Ox- is the serial output from PBCx.
2, 21, 32
VDD
Digital Logic Power Supply.
5
42
36
29
26
VDDP1
VDDP2
VDDP3
VDDP4
VDDP0
Power Supply (3.3V) for O1+/-. If unused, connect to VSS.
Power Supply (3.3V) for O2+/-. If unused, connect to VSS.
Power Supply (3.3V) for O3+/-. If unused, connect to VSS.
Power Supply (3.3V) for O4+/-. If unused, connect to VSS.
Power Supply (3.3V) for O0+/-. If unused, connect to VSS
12, 13, 20, 22, 23
N/C
Not Connected
1, 8, 11, 19, 33, 39
VSS
Ground
VS
S
VSS
I0+
VSS
O2
+
O3
-
O2
-
VDDP2
I3
+
N/C
O0+
O4+
O0-
VDDP1
O1-
O1+
VDD
I4-
VDD
VSS
N/
C
SE
L4
SE
L0
I0-
N/C
SE
L3
SE
L1
SE
L2
N/C
VDDP0
I4+
VDDP4
O4-
VDD
I2
-
I2
+
I1+
I1-
VSS
O3
+
I3
-
VDDP3
VSC7124
VSS
1
3
5
7
9
11
33
31
29
27
25
23
13
15
17
19
21
43
41
39
37
35
N/
C
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