1999-12-15
Page 1
MDSN-0001-00
Vaishali Semiconductor
l
747 Camden Avenue
l
Campbell
l
CA 95008
l
Ph. 408.379.2900
l
Fax 408.379.2937
Applications
Gigabit Ethernet Up-links
High Speed Proprietary
interface
Backplane Serialization
Bus Extender
General Description
The VN16118 is a single chip,1.25 Gigabits per second Ethernet transceiver. It performs all the
functions of the Physical Medium Attachment (PMA) portion of the Physical layer, as specified
by the IEEE 802.3z Gigabit Ethernet standard. These functions include parallel-to-serial and
serial-to-parallel conversion, clock generation, clock data recovery, and word synchronization.
In addition, an internal loopback function is provided for system debugging.
The VN16118 is ideal for Gigabit Ethernet, serial backplane and proprietary point-to-point
applications. The device supports both 1000BASE-LX and 1000BASE-SX fiber-optic media,
and 1000BASE-CX copper media.
The transmitter section of the VN16118 accepts 10-bit wide parallel TTL data and converts it to
a high speed serial data stream. The parallel data is encoded in 8b/10b format. This
incoming parallel data is latched into an input register, and synchronized on the rising edge of
the 125 MHz reference clock supplied by the user. A phase locked loop (PLL) locks to the 125
MHz clock. The clock is then multiplied by 10 to produce a 1.25 GHz serial clock that is used
to provide the high speed serial data output. The output is sent through a Pseudo Emitter
Coupled Logic (PECL) driver. This output connects directly to a copper cable in the case of
1000BASE-CX medium, or to a fiber optic module in the case of 1000BASE-LX or 1000BASE
SX fiber optic medium.
The receiver section of the VN16118 accepts a serial PECL-compatible data stream at a 1.25
Gbps rate, recovers the original 10-bit wide parallel data format, and retimes the data. A Phase
Lock Loop (PLL) locks on to the incoming serial data stream, and recovers the 1.25 GHz high
speed serial clock and data. This is accomplished by continually frequency locking on to the
125 MHz reference clock, and by phase locking on to the incoming data stream. The serial
data is converted back to parallel data format. The `comma' character is used to establish byte
alignment. Two 62.5 MHz clocks, 180 degrees out of phase, are recovered. These clocks are
alternately used to clock out the parallel data on the rising edge. This parallel data is sent to
the user in TTL-compatible form.
Preliminary
VN16118
SERDES
Gigabit Ethernet Transceiver
Features
IEEE 802.3z Gigabit Ethernet
Compliant
Supports 1.25 Gbps Using NRZ Coding
over uncompensated twin-coax cable
Fully integrated CMOS IC
Low Power Consumption
ESD rating >2000V (Human Body
Model) or >200V (Machine Model)
5-Volt Input Tolerance
Fully Compatible with HP HDMP-
1636/HDMP-1646 and Vitesse
VCS7135 transceivers
Available in both 10 mm x 10 mm
and 14 mm x 14 mm LQFP
Packages
V N 1 6 1 1 8
Preliminary
1999-12-15
Page 2
MDSN-0001-00
Vaishali Semiconductor
l
747 Camden Avenue
l
Campbell
l
CA 95008
l
Ph. 408.379.2900
l
Fax 408.379.2937
Figure 1. Functional Block Diagram
Input Data Latch
DOUT+
DOUT-
EWRAP
10
10
DIN+
DIN-
10
10
125 MHz
62.5 MHz
62.5 MHz
Shift Registers
TX PLL Clock
Generator
TX<9:0>
TX_CLK
INPUT
SELECTOR
Shift
Registers
RX PLL Clock
Recovery
FRAME
ENABLE
Output Latch
10
2
RX_CLK<1>
RX_CLK<0>
RX<9:0>
EN_CDET
COM_DET
V N 1 6 1 1 8
Preliminary
1999-12-15
Page 3
MDSN-0001-00
Vaishali Semiconductor
l
747 Camden Avenue
l
Campbell
l
CA 95008
l
Ph. 408.379.2900
l
Fax 408.379.2937
Figure 2. Pin Configuration (Top View)
1
GND_ESD
2
TX<0>
3
TX<1>
4
TX<2>
5
VCC_ESD
6
TX<3>
7
TX<4>
8
TX<5>
9
TX<6>
10
VCC_ESD
11
TX<7>
12
TX<8>
13
TX<9>
14
GND_ESD
15
GND_TXA
16
NC
48
NC
47
COM_DET
46
GND_RXT
45
RX<0>
44
RX<1>
43
RX<2>
42
VCC_RXT
41
RX<3>
40
RX<4>
39
RX<5>
38
RX<6>
37
VCC_RXT
36
RX<7>
35
RX<8>
34
RX<9>
33
GND_RXT
17
NC
18
VCC_TXA
19
EWRAP
20
VCC_TXD
21
GND_TXD
22
TX_CLK
23
VCC_RXD
24
EN_CDET
25
GND_RXD
26
SIG_DET
27
NC
28
VCC_RXD
29
VCC_RX
30
RX_CLK<1>
31
RX_CLK<0>
32
GND_RX
64
GND_TX_HS
63
VCC_TX_HS
62
DOUT+
61
DOUT-
60
VCC_TX_ECL
59
VCC_RXA
58
GND_RXA
57
VCC_RXA
56
GND_RX_ESD
55
VCC_RX_ESD
54
DIN+
53
VCC_RX_ESD
52
DIN-
51
GND_RXF
50
VCC_RXF
49
NC
V N 1 6 1 1 8
Preliminary
1999-12-15
Page 4
MDSN-0001-00
Vaishali Semiconductor
l
747 Camden Avenue
l
Campbell
l
CA 95008
l
Ph. 408.379.2900
l
Fax 408.379.2937
Table 1. Pin Description
Name
Pin #
Type
Description
GND_ESD
VCC_ESD
1, 14
5, 10
Power
Power and ground pairs for pad ESD structure.
TX<0>
TX<1>
TX<2>
TX<3>
TX<4>
TX<5>
TX<6>
TX<7>
TX<8>
TX<9>
2
3
4
6
7
8
9
11
12
13
TTL
Input
10-bit parallel data input pins. This data should be 10b/8b
encoded. The least significant bit is TX<0> and is transmitted
first.
GND_TXA
VCC_TXA
15
18
Power
Power and ground pair for TX PLL analog circuits.
NC
16, 17,
27, 48,
49
No
Connect
These pins are bonded to isolated pads and have no connection
to internal circuits.
EWRAP
19
TTL
Input
Wrap Enable. This pin is active HIGH. When asserted, the
high-speed serial data are internally wrapped from the transmitter
serial data output back to the receiver data input. Also, when
asserted, DOUT
are held static at logic 1. When deasserted,
DOUT
and DIN
are active.
VCC_TXD
GND_TXD
20
21
Power
Power and ground pair for TX digital circuits.
TX_CLK
22
TTL
Input
Reference clock and transmit byte clock. This is a 125 MHz
system clock supplied by the host system. On the positive edge
of the clock, the input data, TX<9:0>, are latched into the
register. This clock is multiplied by 10 internally, to generate the
transmit serial bit clock.
VCC_RXD
GND_RXD
23 28,
25
Power
Power and ground pair for digital circuits in the receiver portion.
EN_CDET
24
TTL
Input
Comma Detect Enable. This pin is active HIGH. When
asserted, the internal byte alignment function is turned on, to
allow the clock to synchronize with the comma character
(0011111XXX). When de-asserted, the function is disabled and
will not align the clock and data. In this mode COM_DET is set to
LOW.
SIG_DET
26
TTL
Output
Signal Detect. This pin is active HIGH. It indicates the loss of
input signal on the high-speed serial inputs, DIN
. SIG_DET is
set to LOW when differential inputs are less than 50 mV.
VCC_RX
GND_RX
29
32
Power
Power and ground pair for the clock signal of the receiver portion.
RX_CLK<1>
RX_CLK<0>
30
31
TTL
Output
Receiver Byte Clocks. Two 180 degrees out-of-phase 62.5 MHz
clock signals that are recovered by the receiver section. The
received bytes are alternately clocked by the rising edges of
these signals. The rising edge of RX_CLK<1> aligns with a
comma character when detected.
V N 1 6 1 1 8
Preliminary
1999-12-15
Page 5
MDSN-0001-00
Vaishali Semiconductor
l
747 Camden Avenue
l
Campbell
l
CA 95008
l
Ph. 408.379.2900
l
Fax 408.379.2937
Table1. (Continued)
Name
Pin#
Type
Description
GND_RXT
VCC_RXT
33
46,
37,
42
Power
Power and ground pairs for ESD structure.
RX<9>
RX<8>
RX<7>
RX<6>
RX<5>
RX<4>
RX<3>
RX<2>
RX<1>
RX<0>
34
35
36
38
39
40
41
43
44
45
TTL
Output
Received Parallel Data Output. RX<0> is the least significant
bit and is received first. When DIN
lose input data, all RX
pins will be held HIGH.
COM_DET
47
TTL
Output
Comma detect. This pin is active HIGH. When asserted, it
indicates the detection of comma character (0011111XXX). It
is active only when EN_CEDT is enabled.
VCC_RXF
GND_RXF
50
51
Power
Power and ground pair for the front-end of the receiver section.
DIN+
DIN-
52
54
Input
High-speed serial data input. Serial data input is received when
EWRAP is disabled.
VCC_RXESD
GND_RXESD
53,55
56
Power
Power and ground pair for ESD structure.
VCC_RXA
GND_RXA
57,
59
58
Power
Power and ground pair for analog circuits of the receiver
section.
VCC_TX_ECL
60
Power
Power supply to line driver circuits. Ground supply is from pin
64.
DOUT-
DOUT+
61
62
Output
High-speed serial data output. These pins are active when
EWRAP is disabled and are held static at logic 1 when EWRAP
is enable.
VCC_TX_HS
GND_TX_HS
63
64
Power
Power and ground pair for high-speed transmit logic in the
parallel-to-serial section.
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