Vishay Siliconix
SPICE Device Model Si4569DY
N- and P-Channel 40-V (D-S) MOSFET
CHARACTERISTICS
N- and P-Channel Vertical DMOS
Macro Model (Subcircuit Model)
Level 3 MOS
Apply for both Linear and Switching Application
Accurate over the -55 to 125C Temperature Range
Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the n- and p-channel vertical DMOS. The
subcircuit model is extracted and optimized over the
-55 to 125C temperature ranges under the pulsed 0-V to 10-V gate
drive. The saturated output impedance is best fit at the gate bias
near the threshold voltage.
A novel gate-to-drain feedback capacitance network is used to model
the gate charge characteristics while avoiding convergence difficulties
of the switched C
gd
model. All model parameter values are optimized
to provide a best fit to the measured electrical data and are not
intended as an exact physical interpretation of the device.
SUBCIRCUIT MODEL SCHEMATIC
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
1
www.vishay.com
Document Number: 74183
S-60744
Rev. A, 08-May-06
Vishay Siliconix
SPICE Device Model Si4569DY
SPECIFICATIONS (T
J
= 25
C UNLESS OTHERWISE NOTED)
Parameter Symbol
Test
Condition
Simulated
Data
Measured
Data
Unit
Static
V
DS
= V
GS
, I
D
= 250
A
N-Ch 1.2
Gate Threshold Voltage
V
GS(th)
V
DS
= V
GS
, I
D
=
-250 A
P-Ch 1.8
V
V
DS
= 5 V, V
GS
= 10 V
N-Ch
224
On-State Drain Current
a
I
D(on)
V
DS
=
-5 V, V
GS
=
-10 V
P-Ch 205
A
V
GS
= 10 V, I
D
= 6 A
N-Ch
0.021
0.022
V
GS
=
-10 V, I
D
=
-6 A
P-Ch 0.023
0.026
V
GS
= 4.5 V, I
D
= 4.8 A
N-Ch
0.026
0.024
Drain-Source On-State Resistance
a
r
DS(on)
V
GS
=
-4.5 V, I
D
=
-4.9 A
P-Ch 0.031
0.031
V
DS
= 15 V, I
D
= 6 A
N-Ch
17
20
Forward Transconductance
a
g
fs
V
DS
=
-15 V, I
D
=
-6 A
P-Ch 37
17
S
I
S
= 1.5 A
N-Ch
0.80
0.73
Diode Forward Voltage
a
V
SD
I
S
=
-1.6 A
P-Ch 0.80
-0.73
V
Dynamic
b
V
DS
= 20 V, V
GS
= 10 V, I
D
= 5 A
N-Ch
17
21
V
DS
=
-20 V, V
GS
=
-10 V, I
D
=
-5 A
P-Ch 34
41
N-Ch 8.8
9.6
Total Gate Charge
Q
g
P-Ch
20
21
N-Ch 2.3
2.3
Gate-Source Charge
Q
gs
P-Ch 4.5
4.5
N-Ch 3.2
3.2
Gate-Source Charge
Q
gs
N-Channel
V
DS
= 20 V, V
GS
= 4.5 V, I
D
= 5 A
P-Channel
V
DS
=
-20 V, V
GS
=
-4.5 V, I
D
=
-5 A
P-Ch 9.2
9.2
nC
Notes
a. Pulse test; pulse width
300 s, duty cycle 2%.
b. Guaranteed by design, not subject to production testing.
2
www.vishay.com
Document Number: 74183
S-60744
Rev. A, 08-May-06
Vishay Siliconix
SPICE Device Model Si4569DY
COMPARISON OF MODEL WITH MEASURED DATA (T
J
=25
C UNLESS OTHERWISE NOTED)
N-Channel MOSFET
3
www.vishay.com
Document Number: 74183
S-60744
Rev. A, 08-May-06
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