UTRON
UT61L1024(E)
Rev 1.1
128K X 8 BIT HIGH SPEED CMOS SRAM
UTRON
TECHNOLOGY
INC. P80040
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
1
REVISION HISTORY
REVISION DESCRIPTION
Draft
Date
Rev. 1.0
Original.
Nov. 06 2002
Rev. 1.1
1.Add order information for lead free product
2.Revised timing read/write waveform
3.Add *V
IL
=-3.0V for pulse width less than 10ns into DC table
May. 22 2003
UTRON
UT61L1024(E)
Rev 1.1
128K X 8 BIT HIGH SPEED CMOS SRAM
UTRON
TECHNOLOGY
INC. P80040
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
2
FEATURES
Fast access time : 12/15ns (max.)
Low power operating : 60mA (typ.)
Single 3.0V~3.6V power supply
Operating temperature :
Extended : -20
~80
All inputs and outputs TTL compatible
Fully static operation
Three state outputs
Data retention voltage : 2V (min.)
Package : 32-pin 300 mil skinny PDIP
32-pin 300 mil SOJ
32-pin 450mil SOP
32-pin 8mm x 20mm TSOP-1
32-pin 8mm x 13.4mm STSOP
FUNCTIONAL BLOCK DIAGRAM
DECODER
I/O DATA
CIRCUIT
CONTROL
CIRCUIT
2048 X 512
MEMORY
ARRAY
COLUMN I/O
OE
WE
A0-A16
Vcc
Vss
I/O1-I/O8
CE
CE2
PIN DESCRIPTION
SYMBOL DESCRIPTION
A0 - A16
Address Inputs
I/O1 - I/O8
Data Inputs/Outputs
CE ,CE2
Chip enable 1,2 Inputs
WE
Write Enable Input
OE
Output Enable Input
V
CC
Power
Supply
V
SS
Ground
NC No
Connection
GENERAL DESCRIPTION
The UT61L1024(E) is a 1,048,576-bit high-speed
CMOS static random access memory organized
as 131,072 words by 8 bits. It is fabricated using
high performance, high reliability CMOS
technology.
The UT61L1024(E) is designed for high-speed
system applications. It is particularly suited for use
in high-density high-speed system applications.
The UT61L1024(E) operates from a single 3.3V
power supply and all inputs and outputs are fully
TTL compatible.
PIN CONFIGURATION
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
CE2
A8
A9
A11
A10
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
Vss
UT61L1024(E)
PDIP / SOJ/SOP
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
16
15
20
19
18
22
23
24
25
26
27
21
CE
WE
OE
A13
A14
NC
A16
Vcc
A15
29
30
31
32
TSOP-I/STSOP
I/O4
A11
A9
A8
A13
I/O3
A10
A14
A12
A7
A6
A5
Vcc
I/O8
I/O7
I/O6
I/O5
Vss
I/O2
I/O1
A0
A1
A2
A4
A3
UT61L1024(E)
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
16
15
20
19
18
22
23
24
25
26
27
21
CE2
NC
A15
A16
32
31
30
29
CE
WE
OE
UTRON
UT61L1024(E)
Rev 1.1
128K X 8 BIT HIGH SPEED CMOS SRAM
UTRON
TECHNOLOGY
INC. P80040
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
3
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
SYMBOL
RATING
UNIT
Terminal Voltage with Respect to Vss
V
TERM
-0.5 to 4.6
V
Operating Temperature
T
A
-20 to 80
Storage Temperature
T
STG
-65 to 150
Power Dissipation
P
D
1
W
DC Output Current
I
OUT
50
mA
Soldering Temperature (under 10 sec)
Tsolder
260
*Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect
device reliability.
TRUTH TABLE
MODE
CE
CE2
OE
WE
I/O OPERATION
SUPPLY CURRENT
Standby
H
X
X
X
High - Z
I
SB
,I
SB1
Standby
X
L
X
X
High -Z
I
SB
,I
SB1
Output Disable L
H
H
H
High - Z
I
CC
Read
L
H
L
H
D
OUT
I
CC
Write
L
H
X
L
D
IN
I
CC
Note: H = V
IH
, L=V
IL
, X = Don't care.
DC ELECTRICAL CHARACTERISTICS
(V
CC
= 3.0V
3.6V, T
A
= -20
to 80
)
PARAMETER
SYMBOL TEST CONDITION
MIN.
MAX.
UNIT
Power Voltage
Vcc
3.0
3.6
V
Input High Voltage
V
IH
2.0 V
CC
+0.5 V
Input Low Voltage
V
IL
*
-
0.5 0.6
V
Input Leakage Current
I
LI
V
SS
V
IN
V
CC
- 1
1
A
Output Leakage Current
I
LO
V
SS
V
I/O
V
CC
CE = V
IH
or CE2 = V
IL
or
OE
= V
IH
or
WE
= V
IL
- 1
1
A
Output High Voltage
V
OH
I
OH
= - 4mA
2.2
-
V
Output Low Voltage
V
OL
I
OL
= 8mA
-
0.4
V
- 12
-
100
mA
Operating Power
Supply Current
I
CC
Cycle time=Min, I
I/O
= 0mA
. CE = V
IL
, CE2 = V
IH
- 15
-
90
mA
I
SB
CE = V
IH
or CE2 = V
IL
- 20
mA
Standby Power
Supply Current
I
SB1
CE
V
CC
-0.2V ;or CE2
0.2V
- 3
mA
Notes:
1. Overshoot : Vcc+3.0v for pulse width less than 8ns.
2. Undershoot : Vss-3.0v for pulse width less than 8ns.
3. Overshoot and Undershoot are sampled, not 100% tested.
UTRON
UT61L1024(E)
Rev 1.1
128K X 8 BIT HIGH SPEED CMOS SRAM
UTRON
TECHNOLOGY
INC. P80040
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
4
CAPACITANCE
(T
A
=25
, f=1.0MHz)
PARAMETER
SYMBOL MIN. MAX.
UNIT
Input Capacitance
C
IN
-
8
pF
Input/Output Capacitance
C
I/O
-
10
pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
0V to 3.0V
Input Rise and Fall Times
3ns
Input and Output Timing Reference Levels
1.5V
Output Load
C
L
=30pF, I
OH
/I
OL
=-4mA/8mA
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 3.0V
3.6V , T
A
= -20
to 80
)
(1) READ CYCLE
UT61L1024-12 UT61L1024-15
PARAMETER
SYMBOL
MIN. MAX. MIN. MAX.
UNIT
Read Cycle Time
t
RC
12
-
15
-
ns
Address Access Time
t
AA
-
12
-
15
ns
Chip Enable Access Time
t
ACE1
, t
ACE1
-
12
-
15
ns
Output Enable Access Time
t
OE
-
6
-
7
ns
Chip Enable to Output in Low Z
t
CLZ1*
, t
CLZ2*
3
-
4
-
ns
Output Enable to Output in Low Z
t
OLZ*
0
-
0
-
ns
Chip Disable to Output in High Z
t
CHZ1*
, t
CHZ2*
-
6
-
7
ns
Output Disable to Output in High Z
t
OHZ*
-
6
-
7
ns
Output Hold from Address Change
t
OH
3
-
3
-
ns
(2) WRITE CYCLE
UT61L1024-12 UT61L1024-15
PARAMETER
SYMBOL
MIN. MAX. MIN. MAX.
UNIT
Write Cycle Time
t
WC
12
-
15
-
ns
Address Valid to End of Write
t
AW
10
-
12
-
ns
Chip Enable to End of Write
t
CW1
, t
CW2
10
-
12
-
ns
Address Set-up Time
t
AS
0
-
0
-
ns
Write Pulse Width
t
WP
9
-
10
-
ns
Write Recovery Time
t
WR
0
-
0
-
ns
Data to Write Time Overlap
t
DW
7
-
8
-
ns
Data Hold from End of Write Time
t
DH
0
-
0
-
ns
Output Active from End of Write
t
OW*
3
-
4
-
ns
Write to Output in High Z
t
WHZ*
-
7
-
8
ns
*These parameters are guaranteed by device characterization, but not production tested.
UTRON
UT61L1024(E)
Rev 1.1
128K X 8 BIT HIGH SPEED CMOS SRAM
UTRON
TECHNOLOGY
INC. P80040
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
5
TIMING WAVEFORMS
READ CYCLE 1
(Address Controlled)
(1,2)
t
RC
t
AA
Data Valid
Address
Dout
t
OH
t
OH
Previous data valid
READ CYCLE 2
(
CE
and
CE2
and
OE
Controlled)
(1,3,4,5)
t
RC
t
AA
t
ACE
t
OE
t
OHZ
t
CLZ
t
OH
t
OLZ
High-Z
Data Valid
High-Z
t
CHZ
Address
CE2
Dout
CE
OE
Notes :
1.
WE
is high for read cycle.
2.Device is continuously selected OE =low, CE =low
,
CE2=high
.
3.Address must be valid prior to or coincident with CE =low
,
CE2=high; otherwise t
AA
is the limiting parameter.
4.t
CLZ
, t
OLZ
, t
CHZ
and t
OHZ
are specified with C
L
=5pF. Transition is measured
500mV from steady state.
5.At any given temperature and voltage condition, t
CHZ
is less than t
CLZ
, t
OHZ
is less than t
OLZ
.
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