UTC NE555
LINEAR INTEGRATED CIRCUIT
UTC
UNISONIC TECHNOLOGIES CO., LTD.
1
QW-R106-001,B
SINGLE TIMER
DESCRIPTION
The UTC NE555 is a highly stable timer integrated
circuit. It can be operated in Astable mode and
Monostable mode. With monostable operation, the
time delay is controlled by one external and one
capacitor. With a stable operation, the frequency and
duty cycle are accurately controlled with two external
resistors and one capacitor.
FEATURES
*High current driver capability(=200mA)
*Adjustable duty cycle
*Timing from
Sec to Hours
*Turn off time less than 2
Sec.
APPLICATIONS
*Precision timing
*Pulse generation
*Time delay generation
DIP-8
SOP-8
BLOCK DIAGRAM
3
7
1
4
6
8
5
2
Vcc
Control
Voltage
Trigger
Output
Dischage
GND
Reset
Threshold
Thr.
Comp.
Tri.
Comp.
Flip Flop
Output
UTC NE555
LINEAR INTEGRATED CIRCUIT
UTC
UNISONIC TECHNOLOGIES CO., LTD.
2
QW-R106-001,B
ABSOLUTE MAXIMUM RATINGS
(Ta=25
C )
PARAMETER
SYMBOL
VALUE
UNIT
Supply Voltage
Vcc
16
V
Power Dissipation
Pd
600
mW
Lead Temperature
Tlead
300
C
Operating Temperature
Topr
0 to 70
C
Storage Temperature
Tstg
-65 to 150
C
ELECTRICAL CHARACTERISTICS
( Ta=25
C
,Vcc=5 ~ 15V)
PARAMETER SYMBOL
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
Supply voltage
Vcc
4.5
16
V
Supply Current
Icc
Vcc=5V,RL=
3 6 mA
(Note 1)
Vcc=15V,RL=
7.5 15 mA
Timing Error(monostable)
Initial Accurary(Note 2)
A
CCUR
R
A
=1k to 100k
1.0
3.0 %
Drift with Temperature
t/T C=0.1F
50
ppm/
C
Drift with Supply Voltage
t/Vcc
0.1
0.5
%/V
Timing Error(astable)
Initial Accurary(Note 2)
A
CCUR
R
A
=1k to 100k
2.25 %
Drift with Temperature
t/T C=0.1F
150 ppm/C
Drift with Supply Voltage
t/Vcc
0.3
%/V
Control Voltage
Vc
Vcc=15V
9.0
10.0
11.0
V
Vcc=5V
2.6
3.33
4.0
V
Threshold Voltage
V
TH
Vcc=15V
10.0
V
Vcc=5V
3.33
V
Threshold Current(Note 3)
I
TH
0.1
0.25
A
Trigger Voltage
Vtr
Vcc=5V
1.1
1.67
2.2
V
Vcc=15V
4.5
5
5.6
V
Trigger Current
Itr
Vtr=0
0.01
2.0
A
Reset Voltage
Vrst
0.4
0.7
1.0
V
Reset Current
Irst
0.1
0.4
mA
Vcc=15V
Isink=10mA
0.06
0.25 V
Low Output Voltage
V
OL
Isink=50mA
0.3
0.75
V
Vcc=5V
Isink=5mA
0.05
0.35 V
Vcc=15V
Isource=200mA
12.5
V
High Output Voltage
V
OH
Isource=100mA
12.75
13.3
V
Vcc=5V, Isource=100mA
2.75
3.3
V
Rise Time of Output
t
R
100
nSec
Fall Time of Output
t
F
100
nSec
Dischage Leakage Current
I
LKG
20
100
nA
Note 1:Supply current when output is high is typically 1mA less at Vcc=5V.
Note 2:Tested at Vcc=5.0V and Vcc=15V.
Note 3:this will determine the maximum value of RA+RB for 15V operation, The maximum total is R=20M
, and
for 5V operation the maximum total is R=6.7M
.
UTC NE555
LINEAR INTEGRATED CIRCUIT
UTC
UNISONIC TECHNOLOGIES CO., LTD.
3
QW-R106-001,B
APPLICATION CIRCUIT
6
2
7
8
4
3
1
5
R2
R1
R3
Q1
FLIP-FLOP
VCC
GND
C1
RB
RA
Reset
Discharge
Threshold
Trigger
UTC NE555
Upper
comparator
Lower
comparator
APPLICATION NOTES
The application circuit shows astable mode configuration.
Pin 6 (Threshold ) is tied to Pin 2 ( Trigger ) and Pin 4 ( reset ) is tied to Vcc ( Pin 8 ). The external capacitor C1 of
Pin 6 and Pin 2 charges through RA,RB and dischages through RB only. In the internal circuit of UTC NE555 , one
input of the upper comparator is at voltage of 2/3Vcc(R1=R2=R3),another input is connected to Pin 6.As soon
as C1 is charging to higher than 2/3Vcc, transistor Q1 is turned ON and discharge C1 to collector voltage of
transistor Q1. Therefore, the flip-flop circuit is reset and output is low. One input of lower comparator is at voltage of
1/3Vcc, discharge transistor Q1 turn off and C1 charges through RA and RB. Therefore, the flip-flop circuit is set
output high.
That is, when C1 charges through RA and RB , output is high and when C1 discharge through RB ,output is low. The
charge time(output is high) t1 is 0.6 9 3(RA+RB) C1 and the discharge time (output is low) T2 is 0.6 9 3 RB*C1.
ln
Vcc
1
3
Vcc
Vcc
2
3
Vcc
0.693
-
-
=
T1=0.693*(RA+RB)*C1
Thus the total period time T is given by T2=0.693*RB*C1
T=T1+T2=0.693(RA+2RB)*C1.
Then the frequency of astable mode is given by
C1
*
RB)
(RA
1.44
T
1
f
2
+
=
=
The duty cycle is given by
D. C.
T2
T
RB
RA
2RB
=
=
+
.
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