US3027

4-1

Rev. 1.3
12/8/00

TYPICAL APPLICATION

DESCRIPTION

The US3027 controller IC is specifically designed to meet
VRM 9.0 specification for next generation microproces-
sor applications requiring multiple on board regulators .
The US3027 provides a single chip controller IC for
the Vcore , 3LDO controllers, one with the auto-
matic select pin that connects to the TYPE DETECT
pin of the AGP slot for the AGP Vddq supply, one
for GTL+ and the other for the 1.8V chip set regula-
tor as required for the next generation PC applica-
tions. The US3027 is designed to use either Bipolar
transistors for Vout3(1.5V) and Vout4(1.8V) or if Vaux
pin is connected to 12V, then MOSFETs can also be
used as external pass elements. No external resis-
tor divider is necessary for any of the regulators.
The switching regulator feature a patented topology that
in combination with a few external components as shown
in the typical application circuit ,will provide well in ex-
cess of 20A of output current for an on- board DC/DC
converter while automatically providing the right output
voltage via the 5 bit internal DAC .The US3027 also fea-
tures, loss less current sensing for both switcher by
using the Rds-on of the high side Power MOSFET
as the sensing resistor, an output under voltage
shutdown that detects short circuit condition for the
linear outputs and latches the system off, and a
Power Good window comparator that switches its open
collector output low when any one of the outputs is out-
side of a pre programmed window.

Designed to meet VRM 9.0 specification for
next generation micrprocessors
On board 5 bit DAC programs the output
voltage from 1.075V to 1.850V in 25mV steps
Linear regulator controller on board for 1.8V
Provides Single Chip Solution for Vcore,
GTL+ ,AGP Bus, and 1.8V
Automatic Voltage Selection for AGP slot
Vddq supply
Linear regulator controller on board for 1.5V
GTL+ supply
Loss less Short Circuit Protection for all
outputs
Synchronous operation allows maximum
efficiency
Patented architecture allows fixed frequency
operation as well as 100% duty cycle during
dynamic load
Minimum part count
Soft Start
High current totem pole driver for direct
driving of the external Power MOSFET
Power Good function Monitors all Outputs
OVP Circuitry Protects the Switcher Output
and generates a Fault output

PACKAGE ORDER INFORMATION

PRELIMINARY DATASHEET

FEATURES

5 BIT PROGRAMMABLE SYNCHRONOUS BUCK

PLUS TRIPPLE LDO CONTROLLER

APPLICATIONS

Total Power Soloution for Next Generation Intel
Processor application
AMD K7 Low Cost Solution

Ta (

C) Device Package

0 TO 70 US3027CW 28 pin Plastic SOIC WB

3027app3-1.0

LINEAR

CONTROL

LINEAR

CONTROL

SWITCHER

CONTROL

US3027

Vout3

Vout1

Vout4

LINEAR

CONTROL

Vout2

3.3V

4-2

Rev. 1.3

12/8/00

US3027

ELECTRICAL SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

V5 supply Voltage ........................................... 7V
V12 Supply Voltage ............................................ 20V
Storage Temperature Range ................................. -65 TO 150

Operating Junction Temperature Range .......... 0 TO 125

PACKAGE INFORMATION

28 PIN WIDE BODY PLASTIC SOIC (W)

=80

C/W

Unless otherwise specified ,these specifications apply over ,V12 = 12V, V5 = 5V and Ta=0 to 70

C. Typical values

refer to Ta =25

C. Low duty cycle pulse testing are used which keeps junction and case temperatures equal to the

ambient temperature.
PARAMETER

SYM

TEST CONDITION

MIN

TYP

MAX

UNITS

Supply UVLO Section
UVLO Threshold-12V

Supply ramping up

UVLO Hysterises-12V

0.6

UVLO Threshold-5V

Supply ramping up

4.4

UVLO Hysterises-5V

0.3

Supply Current
Operating Supply Current

V12

Switching Controllers; Vcore (Vsen 1) and AGP (Vsen 2)
VID Section (Vcore only)
DAC output voltage (note 1)

0.99Vs

1.01Vs

DAC Output Line Regulation

0.1

DAC Output Temp Variation

0.5

VID Input LO

0.8

VID Input HI

VID input internal pull-up
resistor to V5

Vsen2 Voltage

Select<0.8V

1.5

Select>2V

3.3

TOP VIEW

Drive2

Fix

VID4

VID3

VID2

VID1

VID0

PGood

Vsen2

Select

Fault / Rt

Vsen4

Drive4

Gnd

Drive3

Vsen3

Vsen1

OCSet

PGnd

LGate

Phase

UGate

V12

US3027

4-3

Rev. 1.3
12/8/00

Error Comparator Section
Input bias current

Input Offset Voltage

-2

Delay to Output

Vdiff=10mV

100

Current Limit Section
C.S Threshold Set Current

200

C.S Comp Offset Voltage

-5

Hiccup Duty Cycle

Css=0.1 uF

Output Drivers Section
Rise Time

CL=3000pF

Fall Time

CL=3000pF

Dead band Time Between
High side and Synch Drive
(Vcore Switcher Only)

CL=3000pF

200

Oscillator Section (internal)
Osc Frequency

Rt=Open

217

Khz

1.8V Regulator (Vsen 4)
Vsense Voltage

Vo4

Ta=25, Drive4 = Vsen4

1.800

Vsense Voltage

1.800

Input bias current

Output Drive Current

Vaux-Vdrive>0.6V

1.5V Regulator (Vsen 3)
Vsense Voltage

Vo3

Ta=25, Drive3 = Vsen3

1.500

Vsense Voltage

1.500

Input bias current

Output Drive Current

Vaux-Vdrive>0.6V

Power Good Section
Vsen1 UV lower trip point

Vsen1 ramping down

0.90Vs

Vsen1 UV upper trip point

Vsen1 ramping up

0.92Vs

Vsen1 UV Hysterises

.02Vs

Vsen1 HV upper trip point

Vsen1 ramping up

1.10Vs

Vsen1 HV lower trip point

Vsen1 ramping down

1.08Vs

Vsen1 HV Hysterises

.02Vs

Vsen2 trip point

Select<0.8V

1.100

Select>2V

2.560

Vsen4 trip point

Fix=GND

0.920

Fix=Open

1.320

Vsen3 trip point

Fix=GND

0.920

Fix=Open

1.140

Power Good Output LO

RL=3mA

0.4

Power Good Output HI

RL=5K pull up to 5V

4.8

Fault (Overvoltage) Section
Core O.V. upper trip point

Vsen1 ramping up

1.17Vs

Core O.V. lower trip point

Vsen1 ramping down

1.15Vs

FAULT Output HI

Io=3mA

Soft Start Section
Soft Start Current

OCset=0V , Phase=5V

4-4

Rev. 1.3

12/8/00

US3027

Note 1: Vs refers to the set point voltage given in Table 1.

Pin Description
LSB input to the DAC that programs the output voltage. This pin is TTL compatible that
realizes a logic "1" as either HI or Open. When left open,his pin is pulled up internally by
a 27k

resistor to 5V supply.

Input to the DAC that programs the output voltage. This pin is TTL compatible that real-
izes a logic "1" as either HI or Open. When left open,his pin is pulled up internally by a
27k

resistor to 5V supply.

Input to the DAC that programs the output voltage. This pin is TTL compatible that real-
izes a logic "1" as either HI or Open. When left open,his pin is pulled up internally by a
27k

resistor to 5V supply.

MSB input to the DAC that programs the output voltage. This pin is TTL compatible that
realizes a logic "1" as either HI or Open. When left open,his pin is pulled up internally by
a 27k

resistor to 5V supply.

This pin selects a range of output voltages for the DAC.When in the LOW state the range
is 1.3V to 2.05V and when it switches to HI state the range is 2.0V to 3.5V. This pin is
TTL compatible that realizes a logic "1" as either HI or Open. When left open,his pin is
pulled up internally by a 27k

resistor to 5V supply.

This pin is an open collector output that switches LO when any of the outputs are outside
of the specified under voltage trip point. It also switches low when Vsen1 pin is more than
10% above the DAC voltage setting.
This pin provides the feedback for the synchronous switching regulator. Typically this pin
can be connected directly to the output of the switching regulator. However, a resistor
divider is recommended to be connected from this pin to vout1 and GND to adjust the
output voltage for any drop in the output voltage that is caused by the trace resistance.
The value of the resistor connected from Vout1 to FB1 must be less than 1000

This pin controls the gate of an external MOSFET for the AGP linear regulator.
This pin provides shutdown for all the regulatos. A TTL compatible, logic level high applied
to this pin disables all the outputs and discharges the soft start capacitor. The SD signal
turns off the synchronous allowing body diode to conduct and discharge the output cap.

PIN# PIN SYMBOL
7

VID0

VID1

VID2

VID3

VID4

PGOOD

Drive2

PIN DESCRIPTIONS

1 1.075

0 1.100

1 1.125

0 1.150

1 1.175

0 1.200

1 1.225

0 1.250

1 1.275

0 1.300

1 1.325

0 1.350

1 1.375

0 1.400

1 1.425

0 1.450

1 1.475

0 1.500

1 1.525

0 1.550

1 1.575

0 1.600

1 1.625

0 1.650

1 1.675

0 1.700

1 1.725

0 1.750

1 1.775

0 1.800

1 1.825

0 1.850

Table 1 - Set point voltage vs. VID codes

US3027

4-5

Rev. 1.3
12/8/00

Pin Description
This pin is internally connected to the undervoltage and overvoltage comparators sensing
the Vcore status. It must be connected directly to the Vcore supply.
This pin provides the feedback for the AGP linear regulator. The Select pin when con-
nected to the "Type Detect" pin of the AGP slot automatically selects the right voltage for
the AGP Vddq.
This pin controls the gate of an external MOSFET for the 1.8V chip set linear regulator.
This pin is connected to the Drain of the power MOSFET of the Core supply and it
provides the positive sensing for the internal current sensing circuitry. An external resis-
tor programs the C.S threshold depending on the Rds of the power MOSFET. An external
capacitor is placed in parallel with the programming resistor to provide high frequency
noise filtering.
This pin is connected to the Source of the power MOSFET for the Core supply and it
provides the negative sensing for the internal current sensing circuitry.
This pin provides the soft start for all the regulators. An internal current source charges
an external capacitor that is connected from this pin to GND which ramps up the outputs
of the regulators, preventing the outputs from overshooting as well as limiting the input
current. The second function of the Soft Start cap is to provide long off time (HICCUP) for
the synchronous MOSFET during current limiting.
This pin has dual function. It acts as an output of the OVP circuitry or it can be used to
program the frequency using an external resistor . When used as a fault detector, if any
of the switcher outputs exceed the OVP trip point, the FAULT pin switches to 12V and
the soft start cap is discharged. If the FAULT pin is to be connected to any external
circuitry, it needs to be buffered.
This pin controls the gate of an external transistor for the 1.5V GTL+ linear regulator.
This pin provides the feedback for the linear regulator that its output drive is Drive3.
This pin is NO connect.

This pin provides the feedback for the linear regulator that its output drive is Drive4.
This pin serves as the ground pin and must be connected directly to the ground plane.
This pin serves as the Power ground pin and must be connected directly to the GND
plane close to the source of the synchronous MOSFET. A high frequency capacitor
(typically 1 uF) must be connected from V12 pin to this pin for noise free operation.
Output driver for the synchronous power MOSFET for the Core supply.
Output driver for the high side power MOSFET for the Core supply.
This pin is connected to the 12 V supply and serves as the power Vcc pin for the output
drivers. A high frequency capacitor (typically 1 uF) must be placed close to this pin and
PGND pin and be connected directly from this pin to the GND plane for the noise free
operation.
5V supply voltage. A high frequency capacitor (0.1 to 1 uF) must be placed close to this
pin and connected from this pin to the GND plane for noise free operation.
This pin provides automatic voltage selection for the AGP switching regulator. When it is
pulled LO, the voltage is 1.5V and when left open or pulled to HI, the voltage is 3.3V.
Leaving this pin open provides fixed output voltages of the 1.5V and 1.8V for the #3 and #4
linear regulators. When this pin is grounded the reference to the linear regulators are set
to 1.26V and therefore the output of the regulators can be programmed to any voltages
above the 1.26V using; Vout=1.26*(1+Rtop/Rbot)
Where:
Rtop=Top resistor connected from the output to the Vsense pin
Rbot=Bottom resistor connected from the Vsense pin to ground.

PIN# PIN SYMBOL
22

Vsen1

Vsen2

Drive4

OCSET

PHASE

FAULT/Rt

Drive3

Vsen3

Vsen4

GND

PGND

LGATE

UGATE

V12

Select

FIX

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