TM5400/TM5600
Data Book
November 1, 2000
Confidential Information--NDA Required
November 1, 2000
TM5400/TM5600 Data Book
2
Confidential Information--NDA Required
CrusoeTM Processor Model TM5400/TM5600
Data Book
TMDFA-13 Revision 1.3
Confidential Information--NDA Required
Revision History:
1.0
Initial release. (2/18/00)
1.1
Added TM5600. Changed frequency/voltage SKUs. Corrected sequential pin listing and added alphabetic pin
listing. Removed S_CLK[7:4]. Updated electrical specs. (5/25/00)
1.2
Added SDR/DDR interface memory timing tables, thermal diode specs, new package drawings, updated
package marking specifications. (10/23/00)
1.3
Removed 633 MHz SKU (11/1/00)
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November
1,
2000
Confidential Information--NDA Required
3
Table of Contents
Introduction
................................................................................................................... 9
Chapter 1
Functional Interface Description
........................................................................... 13
1.1
DDR SDRAM Interface .................................................................
13
1.2
SDR SDRAM Interface..................................................................
14
1.3
PCI Interface..................................................................................
16
1.3.1
PCI Bus Commands .................................................................................... 16
1.3.2
Bus Arbitration ........................................................................................... 17
1.4
Southbridge Sidebands..................................................................
19
1.5
Serial Interfaces ............................................................................
19
1.6
Clocks .............................................................................................
20
1.7
Power Management.......................................................................
21
1.7.1
Power Management States ......................................................................... 21
1.7.2
SDRAM Power Saving Mode ...................................................................... 23
1.8
Test and Debug..............................................................................
24
1.9
Supply Voltages .............................................................................
24
1.10 Power On Sequence .......................................................................
25
Chapter 2
Pin Description
........................................................................................................... 27
2.1
Signal Definitions ..........................................................................
27
2.2
I/O Signal Listings.........................................................................
38
2.3
Footprint and Pin Assignments....................................................
40
November 1, 2000
TM5400 Data Book
4
Confidential Information--NDA Required
Chapter 3
Electrical Specifications
...........................................................................................53
3.1
Absolute Maximum Ratings .........................................................
53
3.2
Recommended Operating Conditions ..........................................
54
3.3
Power and Current Specifications ...............................................
55
3.4
DC Specifications for I/O Signals .................................................
57
3.5
Timing Specifications for I/O Signals ..........................................
59
3.5.1
General AC Testing Conditions ..................................................................59
3.5.2
Power On Specifications..............................................................................60
3.5.3
Input Clocks .................................................................................................62
3.5.4
DDR SDRAM Interface ...............................................................................64
3.5.5
SDR SDRAM Interface................................................................................69
3.5.6
PCI Interface................................................................................................74
3.5.7
Southbridge Sidebands and Power Management Interface ......................74
3.5.8
Debug Interface ...........................................................................................75
3.5.9
Code Morphing Software Boot ROM Interface ..........................................76
3.5.10 Configuration ROM Interface .....................................................................77
3.5.11 JTAG Interface ............................................................................................78
Chapter 4
Mechanical Specifications
.......................................................................................81
4.1
Thermal Specifications .................................................................
81
4.1.1
Thermal Diode .............................................................................................81
4.2
Package Dimensions .....................................................................
82
4.3
Package Marking ..........................................................................
85
November
1,
2000
Confidential Information--NDA Required
5
List of Tables
TABLE 1 ..................................................DDR SDRAM Memory Configurations 13
TABLE 2 ................ Core and DDR SDRAM Interface Frequency Configurations 14
TABLE 3 ...................................................SDR SDRAM Memory Configurations 15
TABLE 4 .........................Core and SDR SDRAM Bus Frequency Configurations 15
TABLE 5 ............................................................... PCI Bus Commands Supported 17
TABLE 6 .......................................................... Power Management System States 21
TABLE 7 .........................................TM5400/TM5600 Power Management States 22
TABLE 8 .......................................................................................Signal Summary 27
TABLE 9 ..............................................................DDR SDRAM Interface Signals 28
TABLE 10 Logical Alignment of DDR Byte Enables, Data Strobes and Data Bits 29
TABLE 11............................................................. SDR SDRAM Interface Signals 30
TABLE 12 ..Logical Alignment of SDR Clocks, Clock Enables, and Chip Selects 31
TABLE 13 ....................... Logical Alignment of SDR Byte Enables and Data Bits 31
TABLE 14 ...............................................................Memory Address Translations 32
TABLE 15 ............................................................................. PCI Interface Signals 33
TABLE 16 ................................................ Southbridge Sideband Interface Signals 34
TABLE 17 .......................................................................... Serial Interface Signals 34
TABLE 18 ............................................................ Master Clock and Reset Signals 35
TABLE 19 ................................................... Power Management Interface Signals 35
TABLE 20 ........................................................................... Miscellaneous Signals 36
TABLE 21 .......................................................................... JTAG Interface Signals 37
TABLE 22 .................................................................... Power and Ground Signals 37
TABLE 23 ................................................................................. Input Only Signals 38
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