Document Outline
- FEATURES
- APPLICATIONS
- DESCRIPTION
- SIMPLIFIED APPLICATION DIAGRAM
- ABSOLUTE MAXIMUM RATINGS
- RECOMMENDED OPERATING CONDITIONS
- ORDERING INFORMATION
- CONNECTION DIAGRAM
- THERMAL INFORMATION
- ELECTRICAL CHARACTERISTICS
- FUNCTIONAL BLOCK DIAGRAM
- PIN ASSIGNMENTS
- APPLICATION INFORMATION
- Using UCC2540 as the Secondary-Side PWM Controller in the Cascaded Push-Pull Buck Two Stage Converter
- UCC2540 in Multiple Output Power Supplies
- Using UCC2540 as the Secondary-Side Post Regulator
- CEA- and VEA- pins: Current Limit and Hiccup Mode
- Voltage vs. Current Programming (refer to Figure 6):
- COMP, VEA- and CEA- pins: Voltage and Current Error Amplifiers
- Stable Dynamic Current Loop Design (refer to Figure 6):
- RSET, RAMP, G2C, SS pins: Programming the Timer Currents
- G2C pin: G2 Timer
- RAMP pin: PWM Modulator and G1 Timer
- SYNCIN pin
- Ground Clamping
- Overvoltage Clamping
- SYNCIN Clamping for the Isolated Cascaded Buck Topology
- VDD, VDRV, VREF and BST pins: Modes of Operation
- Charge Pump Capacitor Selection
- Output Stage
- Predictive Gate DriveTM Technology
- VDD and IDD
- Soft-Start and Tracking Features
- Ratio-Metric Tracking Design Procedure (see Figures 21 and 22)
- THERMAL INFORMATION
- TYPICAL CHARACTERISTICS
- RELATED PRODUCTS
- REFERENCES
- MECHANICAL DATA
- PWP (R-PDSO-G**) PowerPAD PLASTIC SMALL-OUTLINE
- IMPORTANT NOTICE
UCC2540
SLUS539A - JUNE 2004 - REVISED AUGUST 2004
HIGH EFFICIENCY SECONDARY SIDE
SYNCHRONOUS BUCK PWM CONTROLLER
1
www.ti.com
FEATURES
D
On-Chip Predictive Gate Drive
t
for
High-Efficiency Synchronous Buck
Operation
D
Dual
3-A TrueDrive
t
Outputs
D
1-MHz High Frequency Operation with 70-ns
Delay from SYNCIN to G1 Output
D
Leading Edge Modulation
D
Overcurrent Protection using a Parallel
Average Current Mode Control Loop
D
3 Modes to Support 2.7-V to 35-V Bias
Operation
D
Reverse Current Protection for Output Stage
D
User Programmable Shutdown
D
1.0% Initial Tolerance Bandgap Reference
D
High Bandwidth Error Amplifiers
D
Thermally Enhanced HTSSOP 20-Pin
PowerPAD
t
Package
SIMPLIFIED APPLICATION DIAGRAM
APPLICATIONS
D
Secondary-Side Post Regulation (SSPR) for
Multiple Output Power Supplies
D
Cascaded Buck Converters
D
Post Processing Converters for Bus
Converter and DC Transformer Architectures
DESCRIPTION
The UCC2540 is a secondary-side synchronous
buck PWM controller for high current and low
output voltage applications. It can be used either
as the local secondary-side controller for isolated
dc-to-dc converters using two-stage cascaded
topologies or as a secondary-side post regulator
(SSPR) for multiple output power supplies.
The UCC2540 runs with the synchronization
signal from either the primary side or the high duty
cycle quasi-dc output of bus converters or dc
transformers. For higher efficiency, it also
incorporates the Predictive Gate Drive
t
technology that virtually eliminates body diode
conduction losses in synchronous rectifiers.
UDG-04057
V FB
C1
OUT
Input
QP
Main
Output
FB
UCC25701
13
14
12
16
7
2
VEA-
REF
VDRV
G2
G2S
VDD
UCC2540
19
18
20
17
9
3
8
COMP
G2C
CEA-
BST
G1
SWS
SW
15
11
1
5
RSET
RAMP
PGND
SS
4
SYNCIN
R1
R2
RSNS
AUX
Output
10
TR
Main
Output
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
2004, Texas Instruments Incorporated
Predictive Gate Drive
, TrueDrive
, and PowerPAD
, are a trademarks of Texas Instruments Incorporated.
UCC2540
SLUS539A - JUNE 2004 - REVISED AUGUST 2004
2
www.ti.com
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DESCRIPTION (CONT.)
The UCC2540 is available in the extended temperature range of 40
C to 105
C and is offered in thermally
enhanced PowerPAD
t
20-pin HTSSOP (PWP) package. This space saving package with standard 20-pin
TSSOP footprint has a drastically lower thermal resistance of 1.4
C/W
JC
to accommodate the dual
high-current drivers on board.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)(2)
UCC2540
UNIT
Supply voltage range, VDD
36
V
Supply current, IVDD
VDD
50
mA
CEA-, COMP, G2C, RAMP, SS, TR, VEA-
-0.3 to 3.6
VDRV
-0.3 to 9
Analog input voltages
G1, BST
SW-0.3 to SW+9
V
Analog input voltages
SW, SWS
-1 to 36
V
G2, G2S
-1 to 9
SYNCIN
-0.3 to 8.0
Sink current (peak), IOUT_SINK
G1, G2
3.5
A
Source current (peak), IOUT_SOURCE
G1, G2
-3.5
A
Operating junction temperature range, TJ
-55 to 150
Storage temperature, Tstg
-65 to 150
C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
300
C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions"
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND. Currents are positive into, and negative out of the specified terminal.
RECOMMENDED OPERATING CONDITIONS
MIN
TYP
MAX
UNIT
Supply voltage, VDD
Mode 1
8.5
35
Supply voltage, VDRV
Mode 2
4.75
8.00
V
Supply voltage, REF
Mode 3
3.0
3.3
3.6
V
Supply voltage bypass, CVDD
1.0
2.2
Reference bypass capacitor, CREF
0.1
1.0
2.2
F
VDRV bypass capacitor, CVDRV
0.2
F
BST-SW bypass capacitor, CBST-SW
0.1
Timer current resistor range, RRSET
10
50
k
PWM ramp capacitor range, CRAMP
100
680
pF
Turn-off capacitor range, CG2C
120
1000
pF
COMP pin load range, RLOAD
6.5
k
Junction operating temperature, TJ
-40
105
C
UCC2540
SLUS539A - JUNE 2004 - REVISED AUGUST 2004
3
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ORDERING INFORMATION
TA = TJ
HTSSOP-20 (PWP)(1)
TA = TJ
Bulk
-40
C to +105
C
UCC2540PWP
(1) The PWP package is also available at 70 devices per tube and taped and reeled at
2,000 devices per reel. Add an R suffix to the device type (i.e., UCC2540PWPR). See
the application section of the data sheet for PowerPAD drawing and layout information.
CONNECTION DIAGRAM
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
RSET
REF
G2C
SYNCIN
RAMP
GND
VEA-
CEA-
COMP
TR
SWS
BST
G1
SW
VDD
PGND
G2
VDRV
G2S
SS
PWP PACKAGE
(TOP VIEW)
NOTE: The PowerPAD
t
is not directly connected to any lead of the package. It is electrically and thermally connected to the substrate of the
device which acts as ground and should be connected to PGND on the PCB. The exposed dimension is 1.3 mm x 1.7 mm. However, the
tolerances can be +1.05 mm / -0.05 mm (+41 mils / -2 mils) due to position and mold flow variation.
THERMAL INFORMATION
PACKAGE
FAMILY
PACKAGE
DESIGNATOR
JA (
C/W)
(with PowerPAD)
JC (
C/W)
(without PowerPAD)
JC (
C/W)
(with PowerPAD)
MAXIMUM DIE
TEMPERATURE
PowerPAD
HTSSOP-20
PWP
22.3 to 32.6
(500 to 0 LFM)
19.9
1.4
125
C
UCC2540
SLUS539A - JUNE 2004 - REVISED AUGUST 2004
4
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ELECTRICAL CHARACTERISTICS
VDD = 12 V, 1-
F capacitor from VDD to GND, 1-
F capacitor from BST to SW, 1-
F capacitor from REF to GND, 0.1-
F and 2.2-
F capacitors
from VDRV to PGND, fSYNCIN = 200 kHz, TA = TJ = -40
C to 105
C, (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OVERALL
IVDD
Operating current
DC
8
11
13
mA
IVDD
Operating current
fS = 200 kHz,
CLOAD = 2.2 nF
9
12
30
mA
UNDERVOLTAGE LOCKOUT
VVDD
Start threshold voltage
MODE 1
8.0
8.5
9.0
VVDD
Stop threshold voltage
MODE 1
7.5
8.0
8.5
VVDD
Hysteresis
MODE 1
0.3
0.5
0.8
VVDRV
Start threshold voltage
MODE 2,
VVDD = 4 V
4.30
4.65
4.85
VVDRV
Stop threshold voltage
MODE 2
4.0
4.3
4.6
V
VVDRV
Hysteresis
MODE 2
0.15
0.35
0.55
V
VREF
Start threshold voltage
MODE 3
VVDD= VVDRV= 2.7 V
2.75
3.00
3.20
VREF
Stop threshold voltage
MODE 3
2.25
2.50
2.70
VREF
Hysteresis
MODE 3
0.3
0.5
0.8
VOLTAGE REFERENCE (REF)
VREF
Reference output voltage
TA = 25
C
3.28
3.30
3.32
V
VREF
Reference output voltage
Total variation
3.2
3.3
3.4
V
ISC
Short circuit current
VREF = 0 V,
TA = 25
C
10
13
20
mA
Line regulation
5.25 V
VREF
7.2 V
0
1.5
15
mV
Load regulation
0 mA
IREF
5 mA
0
30
70
mV
PWM (RAMP)
DMIN
Minimum duty cycle
0%
VRAMP
Offset voltage
0.10
0.25
0.45
V
Timeout threshold voltage
2.3
2.5
2.8
V
tDEAD
G1 deadtime at maximum duty cycle ratio
fSYNC = 200 kHz
150
175
200
ns
IRAMP
Ramp charge current
RRSET = 10 k
-325
-300
-275
A
CURRENT ERROR AMPLIFIER
VCEA+
Offset voltage
Total variation
45
50
55
mV
GBW
Gain bandwidth(3)
3
4
MHz
VOL
Low-level output voltage
ICOMP = 0 A,
VCEA- = 3.3 V,
VVEA- = 2.0 V
0.1
V
VOL
Low-level output voltage
ICOMP = 200
A, VCEA- = 1.5 V
VVEA- = 1 V
0
0.60
0.83
V
VOH
High-level output voltage
ICOMP = 0 A,
VCEA- = 0 V,
VVEA- = 1 V
2.2
2.5
3.0
V
AVOL
Open loop
60
100
140
dB
IBIAS
Bias current
-200
-80
-10
nA
ISINK
Sink current
VCOMP = 1.0 V,
VCEA- = 1.5 V,
VVEA- = 0 V
0.35
0.80
1.70
mA
CMR
Common mode input range(3)
0
2
V
(3) Ensured by design. Not production tested.
UCC2540
SLUS539A - JUNE 2004 - REVISED AUGUST 2004
5
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ELECTRICAL CHARACTERISTICS
VDD = 12 V, 1-
F capacitor from VDD to GND, 1-
F capacitor from BST to SW, 1-
F capacitor from REF to GND, 0.1-
F and 2.2-
F capacitors
from VDRV to PGND, fSYNCIN = 200 kHz, TA = TJ = -40
C to 105
C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOLTAGE ERROR AMPLIFIER
VSS_OFF Offset voltage from soft-start input
ICOMP = VVEA-, VSS- = 1.5 V
0.40
0.75
1.00
V
VTR_OFF Offset voltage from tracking input
VTR = 1.0 V,
VCOMP = VVEA-
25
48
70
mV
VVEA+
Threshold voltage (from VEA- to COMP)
0
C
TA
105
C
1.485
1.500
1.515
V
VVEA+
Threshold voltage (from VEA- to COMP)
Total variation
1.47
1.50
1.53
V
GBW
Gain bandwidth(3)
3
4
MHz
VOL
Low-level output voltage
ICOMP = 0 A,
VCEA- = 1.75 V,
VVEA- = 2.0 V,
0.1
VOL
Low-level output voltage
ICOMP = 200
A, VCEA- = 0 V,
VVEA- = 1 V,
VTR = 0 V
0
0.60
0.83
V
VOH
High-level output voltage
ICOMP = 0 A,
VCEA- = 0 V
VVEA- = 1 V
2.2
2.5
3.0
AVOL
Open loop
60
100
140
dB
IBIAS
Bias current
-300
-150
-50
A
ISINK
Sink current(4)
VCOMP = 1.0 V,
VCEA- = 0 V,
VVEA- = 1.5 V
0.35
0.80
1.70
mA
CURRENT SET
IOUT
Output current
RRSET = 10 k
-158
-150
-142
A
VRSET
RSET voltage
RRSET = 10 k
1.42
1.50
1.58
V
SYNCHRONIZATION AND SHUTDOWN TIMER (SYNCIN, G2C)
Timer threshold
2.3
2.5
2.7
V
SYNCIN threshold
1.50
1.65
1.80
V
ICHG(G2C) Shutdown timer charge current
RRSET = 10 k
-325
-300
-275
A
SOFT-START (SS)
ICH(SS)
Charge current
RRSET = 10 k
-230
-200
-170
A
IDSCH(SS) Discharge current
RRSET = 10 k
50
70
100
A
Discharge/shutdown threshold
0.35
0.45
0.55
V
DRIVE REGULATOR (VDRV)
VVDRV
Output voltage
VVDD = 8.5 V
6.87
7.20
7.53
V
Line regulation
9 V
VVDD
35 V
0
50
100
mV
Load regulation
-5 mA
IVDRV
0 mA
0
50
100
mV
ISC
Short-circuit current
15
30
50
mA
G2S GATE DRIVE SENSE
G2S rising threshold voltage
VSWS = 0 V
1.90
2.25
3.10
V
G2S falling threshold voltage
VSWS = 0 V
1.00
1.25
1.03
V
IG2S
Current
VG2S = 0 V
-0.70
-0.50
-0.37
mA
SWS GATE DRIVE SENSE
SWS rising threshold voltage
VG2S = 0 V
1.90
2.25
2.90
V
SWS falling threshold voltage
VG2S = 0 V
1.0
1.2
1.3
V
ISWS
Current
VSWS = 0 V
-1.8
-1.3
-0.9
mA
Negative threshold voltage
-0.5
-0.3
-0.1
V
(3) Ensured by design. Not production tested.
UCC2540
SLUS539A - JUNE 2004 - REVISED AUGUST 2004
6
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ELECTRICAL CHARACTERISTICS
VDD = 12 V, 1-
F capacitor from VDD to GND, 1-
F capacitor from BST to SW, 1-
F capacitor from REF to GND, 0.1-
F and 2.2-
F capacitors
from VDRV to PGND, fSYNCIN = 200 kHz, TA = TJ = -40
C to 105
C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
G1 MAIN OUTPUT
RSINK
Sink resistance
VSW = 0 V,
VBST = 6 V,
VG1 = 0.5 V
0.3
0.7
1.3
RSRC
Source resistance
VSW = 0 V,
VBST = 6 V,
VG1 = 5.7 V
10
25
45
ISINK
Sink current(3)
VSW = 0 V,
VBST = 6 V,
VG1 = 3.0 V
3
A
ISRCE
Source current(3)
VSW = 0 V,
VBST = 6 V,
VG1 = 3.0 V
-3
A
tRISE
Rise time
CLOAD = 2.2 nF, from G1 to SW
12
25
ns
tFALL
Fall time
CLOAD = 2.2 nF, from G1 to SW
12
25
ns
G2 SYNCHRONOUS RECTIFIER OUTPUT
RSINK
Sink resistance
VG2 = 0.3 V
5
15
30
ISINK
Sink current(3)
VG2 = 3.25 V
3
A
ISRC
Source current(3)
VG2 = 3.25 V
-3
A
tRISE
Rise time
CLOAD = 2.2 nF, from G2 to PGND
12
25
ns
tFALL
Fall time
CLOAD = 2.2 nF, from G2 to PGND
12
25
ns
VOH
High-level output voltage, G2
VSW = GND
6.2
6.7
7.5
V
DEADTIME DELAY (see Figure 1)
tON(G1)
RAMP rising to G1 rising
90
115
130
tOFF(G1)
SYNCIN falling to G1 falling
50
70
90
tON(G2)
tOFF(G2)
Delay control resolution
3.5
5.0
6.5
ns
tON(G2)
G2 on-time minimum
wrt G1 falling
-24
ns
tON(G2)
G2 on-time maximum
wrt G1 falling
62
tOFF(G2)
G2 off-time minimum
wrt G1 rising
-68
tOFF(G2)
G2 off-time maximum
wrt G1 rising
10
(3) Ensured by design. Not production tested.
SYNCIN
G1
G2
G2C
RAMP
tOFF(G1)
tON(G1)
tON(G2)
tOFF(G2)
VERR
Figure 1. Predictive Gate Drive Timing Diagram
UCC2540
SLUS539A - JUNE 2004 - REVISED AUGUST 2004
7
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FUNCTIONAL BLOCK DIAGRAM
UVLO
REFERENCE
PREDICTIVE
LOGIC
RAMP
&
PWM LOGIC
SYNC
1
2
3
4
6
7
8
9
19
16
13
12
11
18
14
10
G2
G1
PGND
VDRV
GND
BST
SW
SYNCIN
RSET
REF
G2C
COMP
VEA-
TR
CEA-
G2S
UVLO
PWM
HUP
VERR
RAMP
CLK
17
SWS
5
RAMP
15
VDD
DRIVE
REGULATOR
VREF
VREF
SS
LOW SIDE
DRIVER
VDD
VDD
VDRV
VREF
PGND
20
PGND
HIGH SIDE
DRIVER
VREF
VREF
PWR
BIAS
PWR
G2 TIMER
G2
GLO
GLO
+
-
1.5V
G1D
UVLO
G2TO
G1D
UDG-04056
ISET
2
ISET
1.33
ISET
1.73
ISET
100 ns
2
ISET
ERROR
AMPLIFIERS
AND
FAULT LOGIC
UCC2540
SLUS539A - JUNE 2004 - REVISED AUGUST 2004
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PIN ASSIGNMENTS
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
BST
19
I
Floating G1 driver supply pin. VHI is fed by an external Schottky diode during the SR MOSFET on time. Bypass
BST to SW with an external capacitor.
CEA-
8
I
Inverting input of the current error amplifier used for output current regulation.
COMP
9
I
Output of the voltage and current error amplifiers for compensation.
G1
18
O
High-side gate driver output that swings between SW and BST.
G2
14
O
Low-side gate driver output that swings between PGND and VDRV.
G2C
3
I
Timer pin to turn off synchronous rectifier. The capacitor connected to this pin programs the maximum duration
that G2 is allowed to stay HIGH.
G2S
12
I
Used by the predictive deadtime controller for sensing the SR MOSFET gate voltage to set the appropriate dead-
time.
GND
6
-
Ground for internal circuitry. GND and PGND should be tied to the pc-board ground plane with vias.
PGND
15
-
Ground return for the G2 driver. Connect PGND to the pc-board ground plane with several vias.
RAMP
5
I
Input pin to connect capacitor to GND to generate the PWM ramp and serve as a maximum duty ratio timer.
REF(1)
2
I/O
3.3-V reference pin. All internal circuits are powered from this 3.3-V rail. Bypass this pin with at least 0.1
F of
capacitance for REF loads that are 0 mA to -1 mA. Bypass this pin with at least 1
F of capacitance if it is used
as an input (Mode 3) or if it has large or pulsating loads.
RSET
1
I
Pin to program timer currents for G2C, RAMP, SS charge and SS discharge. This pin generates a current propor-
tional to the value of the external resistor connected from RSET pin to GND. RSET range is 10 k
to 50 k
(giv-
ing a programmable nominal ISET range of 30
A to 150
A, respectively).
SS
11
I
Soft start and shutdown pin. Connect a capacitor to GND to set the soft-start time. Add switch to GND for imme-
diate shutdown functionality.
SYNCIN
4
I
Input pin for timing signal.
SW
17
-
G1 driver return connection.
SWS
20
I
Used by the predictive controller to sense SR body-diode conduction. Connect to SR MOSFET drain close to the
MOSFET package.
TR
10
I
Tracking input to the voltage error amplifier. Connect to REF when not used.
VDD
16
I
Power supply pin to the device and input to the internal VDRV drive regulator. Normal VDD range is from 4.5 V to
36 V. Bypass the pin with at least 1
F of capacitance.
VDRV
13
I
Output of the drive regulator and power supply pin for the G2 driver. VDRV is also the supply voltage for the in-
ternal logic and control circuitry.
VEA-
7
I
Inverting input of the voltage error amplifier used for output voltage regulation.
(1) REF is an input in Mode 3 only.
UCC2540
SLUS539A - JUNE 2004 - REVISED AUGUST 2004
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APPLICATION INFORMATION
The UCC2540 is a high-efficiency synchronous buck controller that can be used in many point-of-load
applications. It can be used as a local controller for cascaded techniques such as post processing converters
for isolated integrated bus converters (IBC) and dc transformer architectures. It can also be used as a general
purpose secondary-side post regulator for high-accuracy multiple-output power supplies.
Using UCC2540 as the Secondary-Side PWM Controller in the Cascaded Push-Pull Buck Two Stage
Converter
The two-stage cascaded push-pull buck topology converts higher-input bus voltage such as 48-V telecom
voltage to sub 2-V output voltages.
UDG-02140
UCC28089
13
14
13
16
7
2
VEA-
REF
VDRV
G2
G2S
VDD
UCC2540
19
18
20
17
9
3
8
COMP
G2C
CEA-
BST
G1
SWS
SW
15
11
1
5
RSET
RAMP
PGND
SS
4
SYNCIN
R1
R2
C2
Q4
RA
RB
L1
Q3
V3
Q2'
Q1'
NS2
NS1
NP2
Q2
Q1
NP1
T1
V1
C1
OUT1 OUT2
SYNC
CLOCK RESET
VIN
48-V
OUT1
10
TR
Figure 2. Secondary-Side Controlled Cascaded Push-Pull/Buck Converter
The primary-side power stage is an open loop push-pull converter that provides voltage step-down, and
galvanic isolation. This takes the high bus voltage and converts it into an intermediate voltage such as 7 V. The
primary-side push-pull gate drive signals can come from either off-the-shelf oscillators or a fully integrated 50%
duty dual-output oscillator such as the UCC28089.
The secondary-side power stage is a buck converter that is optimized for low-output voltage regulation. The
clock reset pulse signal from the primary side is transmitted using a signal transformer.
UCC2540
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APPLICATION INFORMATION
There are many advantages to this secondary-side control circuit. The simple isolated power stage does not
require any feedback across the isolation boundary. Since the primary-side oscillator is free running, there is
no need for an isolated start-up power supply. This high-frequency circuit provides soft-switching operation (for
all six MOSFET switches), optimum transformer core utilization, and minimizes filter requirements because
there are no additional high-current inductors.
The push-pull primary side permits simple direct drive control of the input stage MOSFETs. In exchange, it
requires that the input MOSFETs are rated to at least twice the peak input line voltage. This configuration works
well for 36-V to 72-V input line applications, because there are many suitable power MOSFETs available in the
range of 150 V. For applications with larger input voltages, a half bridge or full bridge with alternating modulation
might be more suitable for an input stage. Thus, the cascaded topology has a large degree of flexibility with input
power stages. The cascaded topology also has flexibility in the output stages, as well.
For additional information on this topology refer to Power Supply Seminar SEM-1300 Topic 1: Unique
Cascaded Power Converter Topology for High Current Low Output Voltage Applications [1]. The topic discusses
the operating principles, design trade-offs, and critical design procedure steps.
UCC2540 in Multiple Output Power Supplies
One such flexibility is an ability to easily add independently regulated auxiliary outputs. A multiple output
implementation of the cascaded push-pull/buck power converter is shown in Figure 3.
UDG-02142
UCC28089
UCC2540
14
18
G2
G1
4
SYNCIN
C1
OUT1
OUT2
SYNC
CLOCK
RESET
INPUT
C2
Q4
Q3
Q2'
Q1'
NP1
NP2
Q1
Q2
L2
OUT1
PWM
UCC2540
14
18
G2
G1
4
SYNCIN
C3
Q6
Q5
L3
OUT2
PWM2
PWM
PWM2
SYNCIN
SYNCIN
Figure 3. Multiple Output Implementation of Push-Pull/Buck Cascaded Converter
UCC2540
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APPLICATION INFORMATION
Using UCC2540 as the Secondary-Side Post Regulator
UCC2540 can also be used as a secondary-side post regulator (SSPR) for precision regulation of the auxiliary
voltages of multiple output power supplies, as shown in Figure 4. The UCC2540 uses leading-edge modulation
so that it is compatible with either voltage-mode or current-mode primary-side control converters using any
topology such as forward, half-bridge or push-pull.
C1
OUT1
OUT2
INPUT
C2
Q2'
Q1'
NP1
NP2
Q1
Q2
L2
MAIN
OUTPUT
UCC2540
14
18
G2
G1
4
SYNCIN
C3
Q6
Q5
PWM2
L3
AUX
OUT1
PWM2
1
FB
UCC3808x
UDG-02145
VFB
Figure 4. Multiple Output Converter with Primary Side Push-Pull Converter
UCC2540
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APPLICATION INFORMATION
CEA- and VEA- pins: Current Limit and Hiccup Mode
Typical power supply load voltage versus load current is shown in Figure 5. This figure shows steady state
operation for no-load to overcurrent shutdown (soft-start retry is not depicted in the diagram). During the voltage
regulation conditions, the voltage error amplifier output is lower than the current error amplifier, allowing the
voltage error amplifier to control operation. During the current limit conditions, the current error amplifier output
is lower than the voltage error amplifier, allowing the current error amplifier to control operation. The boundary
between voltage and current control occurs when the difference between CEA- and VEA- tries to exceed
50 mV.
Current limiting begins to occur when the difference between CEA- and VEA- exceeds 50 mV. For currents
that exceed this operating condition, the UCC2540 controls the converter to operate as a pure current source
until the output voltage falls to half of its rated steady state level. Then the UCC2540 sets both G1 and G2 outputs
to LOW and it latches a fault that discharges the soft-start voltage at 30% of its charging rate. The UCC2540
inhibits a retry until the soft-start voltage falls below 0.5 V. A functional diagram of the voltage and current error
amplifiers is shown in Figure 6.
UDG-04053
Shutdown
Limited
Current
ILOAD - Load Current - A
V
LOAD
- Load V
o
ltage - V
VREG
Figure 5. Typical Power Supply Load Voltage vs Current
UCC2540
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APPLICATION INFORMATION
UDG-04052
RLOAD
RS
RI1
RV1
RI2
RV2
RFI
CFI
RFV
CFV
ZFV
ZIV
CFIR
VERR to
1.5 V
VEA-
7
8
9
CEA-
UCC2540
+
+
+
Voltage
Error
Amplifier
COMP
Modulator
Current
Error
Amplifier
C
+
+
SS
TR
R
+
1.25 R
50 mV
ZFV
ZIV
From Power MOSFET
Switch Node
1.5 V
Inverting
Amplifier
+
0.7 V
Figure 6. Error Amplifier Configuration
Component selection includes setting the voltage regulation threshold, then the current limit threshold, as
described below.
Voltage vs. Current Programming (refer to Figure 6):
1.
Determine the ratio
R
V1
R
V2
+
V
LOAD(reg)
V
VEA
*
)
Threshold Voltage
*
1 V
+
V
LOAD(reg)
1.5 V (typ)
*
1 V
2.
Sense resistor R
S
+
1
)
R
V1
R
V2
V
CEA
)
offset voltage
I
S(max)
, where I
S(max)
is the current limit level,
V
CEA+
offset = 50 mV (typ).
3.
Arbitrarily select either R
V1
or R
V2
so that the smallest of the two resistors is between 6.5 k
and 20 k
.
Then calculate the value of the other resistor using the equation in the first step.
If the converter is in a current-limit condition and the output voltage falls below half of the regulated output
voltage, the UCC2540 enters into a hiccup (restart-retry) mode. Figure 7 shows typical signals during hiccup
mode.
UCC2540
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APPLICATION INFORMATION
SYNCIN
SS
RAMP
G2C
G1
G2
0.5 V
3.3 V
ILOAD
VLOAD
UDG-04046
Figure 7. Typical Hiccup Mode waveforms
COMP, VEA- and CEA- pins: Voltage and Current Error Amplifiers
From no-load to full rated load operating conditions, the UCC2540 operates as a voltage mode controller. Above
the programmed rated current, there are two levels of over current protection; constant current limit and
overcurrent reset/retry. This section gives suggestions on how to design the voltage controller and current
controller so that they interact with one another in a stable fashion. Refer to the functional diagram of the voltage
and current error amplifiers in Figure 6. The voltage error amplifier in the figure shows three non-inverting inputs.
The lowest of the three non-inverting inputs (1.5 V, SS and TR) is summed with the non-inverting input to
achieve the voltage error signal. The lowest of the two outputs drives the inverting stage which in turn, drives
the modulator.
During steady state voltage control operation, the feedback elements in the current loop have no effect on the
loop stability. When current limit occurs, the voltage error amplifier effectively shuts OFF and the current error
amplifier takes control. During steady state current limit operation, the negative feedback elements in the
voltage error amplifier loop become positive feedback elements in the current error amplifier loop. In order for
the current error amplifier to be stable, the impedances in the feedback path of the current error amplifier must
be lower than the impedances in the feedback path of the voltage error amplifier. This means that resistors in
the current error amplifier negative feedback path must be less than the resistors in the voltage error amplifier
negative feedback path. Also capacitors in the current error amplifier negative feedback path must be larger
than capacitors in the negative feedback path of the voltage error amplifier negative feedback path.
(Capacitance is really an admittance value rather than an impedance value). This concept is illustrated in
Figure 6.
In order for the current loop to be stable in Figure 6, ||Z
IV
|| must be less than ||Z
FV
|| over all frequencies. This
can be achieved if R
FI
< R
FV
and C
FI
> C
FV
.
UCC2540
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APPLICATION INFORMATION
Another issue that can occur during current limit operation is modulator stability. In order for the modulator to
be stable, the rising slope of the current ripple measured at the COMP pin must be smaller than the rising slope
that is measured at the RAMP pin. This can be met either in the selection of the ratio of ||Z
IV
|| to ||Z
FV
||, or by
the addition of a capacitor in parallel to R
FI
and C
FI
, such as C
FIR
, in Figure 6.
Stable Dynamic Current Loop Design (refer to Figure 6):
1.
Using any favorite approach, design the voltage error amplifier for stable voltage mode design. Use at least
15 k
for any resistors in the negative feedback path of the voltage error amplifier (between pins 9 and 7).
This does not apply to resistance values between the power supply output voltage and pin 7; it also does
not apply to resistance values between ground and pin 7.
2.
The goal is to design the current limit control loop so that it drives the converter to maintain 50 mV between
the VEA- pin and the CEA- pin during current-limit conditions. Select the current sense element and the
voltage divider ratios for the VEA- pin to ground and the CEA- pin to ground to provide the desired current
limit level.
3.
Place the same configuration of components in the negative feedback path of the current error amplifier
(between pins 9 and 8), that are in the negative feedback path of the voltage error amplifier (between pins
9 and 7). However, use resistors with values that are 67% of the corresponding resistors that are between
pins 9 and 7 and use capacitors that are 150% of the corresponding capacitors that are between pin 9 and
pin 7.
4.
Check the COMP signal. If it is unstable, place a capacitor (or increase the capacitance) between pins 9
and 8 in order to attenuate the current ripple. Raise the value of the capacitor until the COMP pin voltage
becomes stable. Compare the COMP voltage with the RAMP voltage. With stable operation, the rising slope
of the COMP voltage ripple is less than the rising slope of the RAMP pin.
UCC2540
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APPLICATION INFORMATION
RSET, RAMP, G2C, SS pins: Programming the Timer Currents
Set the base current to the timers with a resistor between RSET and GND. The block diagram of the UCC2540
shows the interaction of the RSET pin and the dependent current sources for the RAMP, G2C and SS features.
The RSET pin is a voltage source; the current of the RSET pin is reflected and multiplied by a gain and distributed
to the RAMP (gain = 2), G2C (gain = 2) and SS (charge gain = 1.33, net discharge gain = 0.4). The resistance
applied to the RSET pin and GND should be in the range of 10 k
< R
RSET
< 50 k
. RAMP, G2C and SS timers
are programmed by the selection of capacitors tied between each of their respective pins and GND.
G2C pin: G2 Timer
3
G2C
+
S
Q
Q
G2C
Latch
G2TO
G2 Timeout
Comparator
2.5 V
UVLO
*G1D
GLO
G2
*G1 with delay, but not blanked
UDG-04047
CG2C
2
y
IRSET
RD
Figure 8. Functional diagram of the G2 Timer
The G2C pin programs the maximum duration of the synchronous rectifier to facilitate low or zero duty ratio
operation. FIgure 8 shows the functional diagram. This function is programmed by connecting a capacitor
between the G2C pin and GND. The capacitor on G2C should be slightly larger than the capacitor on the RAMP
pin. For best results, program the typical G2 time limit to be between 1.5 and 3 times the switching period (T).
Notice that when the G2 timer reaches its limit, both G1 and G2 are forced to a LOW output. This feature
prevents the current in the output inductor from excessive negative excursions during zero-duty ratio conditions.
Program the G2 time-out (G2TO) duration using equation (1):
C
G2C
+
2
V
RSET
R
RSET
G2 Timeout Duration
G2C Timer Threshold
, Farads
where
D
V
RSET
= 1.5 V(typ)
D
1.5 T < G2 Timeout Duration < 3T
S
D
G2C Timer Threshold = 2.5 V (typ)
(1)
UCC2540
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APPLICATION INFORMATION
RAMP pin: PWM Modulator and G1 Timer
The RAMP pin serves two purposes: (1) programming the gain of the PWM modulator and (2) programming
the time-out duration of G1 in case the main power stage has not caused a SYNC pulse to occur. A diagram
of the PWM modulator and G1 timer is shown in Figure 9. The UCC2540 has a leading edge modulator that
compares the error output with the RAMP voltage. The modulator frequency is externally driven through the
SYNCIN pin. The RAMP pin provides both a sawtooth wave for the PWM comparator and it functions as G1
time-out protection that is programmed by R
SET
and the value of the RAMP capacitor.
A switching cycle begins with the falling edge of the SYNCIN signal, which must be LOW for at least
50 nanoseconds. The falling edge of SYNCIN generates a 100 ns discharge strobe (CLK), to the RAMP function
and then, allows the RAMP capacitor to charge from the 2
I
RSET
current source.
5
RAMP
+
S
Q
Q
PWM
Latch
G1 Timeout
Comparator
250 mV
ENA
CLK
+
+
2.5 V
PWM
PWM
Comparator
UDG-04048
2
y
IRSET
RD
VERR
Figure 9. PWM Modulator and G1 Time-Out Comparator
Low-line or brownout conditions can cause the primary side duty ratio to approach 100% where parasitic
converter impedances may temporarily impair the quality of the SYNCIN pulse. The RAMP timing function
terminates the G1 pulse when the RAMP voltage exceeds 2.5 V. The duration of the RAMP timing function
should be set as follows:
C
RAMP
w
2
V
RSET
R
RSET
T
S
PWM
RAMP
timeout threshold voltage
where
D
T
S
= switching period
D
V
RSET
= 1.5 (typ)
D
PWM
(RAMP)
= 2.5 V (typ)
R
SET
C
RAMP
w
1.2
f
S
Gain (PWM modulator)
w
0.4
In order to use the G1 Timer feature, the peak RAMP voltage at the end of a switch cycle should be as close
to 2.5 V as the C
RAMP
and R
RSET
tolerances allow. In other words, the PWM modulator gain should be
programmed to be equal to, or slightly greater than 0.4 inverse-V.
(2)
(3)
UCC2540
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APPLICATION INFORMATION
SYNCIN pin
A falling edge applied to the SYNCIN pin generates a narrow pulse that is the base timer for internal UCC2540
functions. The SYNCIN pulse must be HI for at least 100 ns preceding the falling edge and LOW for at least
50 ns in order to be registered as a valid pulse. Due to the critical nature of the timing, avoid filtering the falling
edge of the SYNCIN signal in order to avoid signal delay. The peak SYNCIN voltage can easily range from
between 2.5 V and 6.6 V, which allows a simple resistive divider to scale the secondary transformer voltage in
post regulator applications.
Situations where the line voltage varies more extensively or there is extensive ringing may call for clamping
and/or additional gain.
Ground Clamping
In applications where a ring or a spike causes SYNCIN to fall below GND, protect the pin with a Schottky diode
(cathode = SYNCIN, anode = GND).
Overvoltage Clamping
The SYNCIN signal may require overvoltage clamping in applications where the peak SYNCIN voltage is
perilously close to the absolute maximum level of 8 V, due to either ringing or voltage levels. The REF or VDRV
can be used as clamp voltages, as in Figure 10. Make sure that REF or VDRV always sources current. The
reason is that both REF and VDRV are used to detect the mode of operation when they are back-driven and
they could latch into the wrong operating mode at start-up.
RSR
RSY
RRF
1
F
UDG-04049
2 REF
4 SYNCIN
18
G1
14
G2
UCC2540
Auxiliary
Output
Main
Output
+
Figure 10. REF Clamp for SYNCIN. Note the REF Load Resistor.
UCC2540
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APPLICATION INFORMATION
Another overvoltage clamping option is to directly clamp the SYNCIN pin. Unfortunately, Zener diodes have
excessive junction capacitance which causes too much delay in the signal. However, a base-emitter clamp that
achieves the desired clamping action can be employed with minimal delay to the SYNCIN signal. See Figure 11.
Simply select R
SR
and (R
CB
+ R
BE
) to give the appropriate 0 V to 3.3 V signal at low-line conditions. Then, select
the ratio of R
CB
to R
BE
to cause the transistor to turn-on when SYNCIN exceeds 4 V.
UDG-04050
RSR
RCB
RBE
4
SYNCIN
18
G1
14
G2
UCC2540
Auxiliary
Output
Main
Output
+
Figure 11. VBE Clamp for SYNCIN
SYNCIN Clamping for the Isolated Cascaded Buck Topology
The UCC2540 is ideally suited as a secondary side controller for the cascaded buck topology, when it is
partnered with the UCC28089 primary side start-up controller. The primary side controller transmits a pulse
edge during its dead time. The UCC2540 uses the primary-side pulse in order to provide zero voltage conditions
for primary- and secondary-side switches. The predictive delay feature tunes the secondary-side transition to
minimize reverse recovery losses in the synchronous rectifier. The pulse-edge information can vary with the
primary side bias voltage and therefore, it must be clamped. The circuit shown in Figure 12 includes the
appropriate pulse-edge shaping circuit, clamping and 1500-V isolation. The recommended transformer, COEV
part # MGBBT-00011-01, is smaller than many opto-isolators.
SYNC
GND
UCC28089
C1
680 pF
QCL
2N3904
REF
SYNCIN
UCC2540
T1
1:1
Secondary Ground
Primary Ground
UDG-04051
L1
15
H
RCB
RBE
R1
634
Figure 12. Isolation and Clamping the SYNCIN Signal for Cascaded Buck Converters
UCC2540
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APPLICATION INFORMATION
VDD, VDRV, VREF and BST pins: Modes of Operation
Depending on the available bias voltage for the UCC2540, the startup, shutdown, and restart conditions are
different. There are three distinct configurations or modes of biasing the UCC2540. The mode is detected and
latched into an internal register during power-up when VREF crosses 2 V. The register is cleared when VDD,
VDRV and VREF are simultaneously less than 1 V. All modes are compatible with either cascaded buck or with
secondary-side post regulator (SSPR) topologies. The main bias voltage of Modes 1 and 2 can be implemented
with a diode and a capacitor from an ac-voltage such as the secondary winding of the transformer. A summary
of the modes and their programming requirements are listed in Table 1.
Table 1. Modes and Programming Requirements
Mode
VBIAS
Range (V)
Bias Pin
UVLO ON
(V)
UVLO OFF
(V)
Mode Requirement
at Power-Up and
VVREF = 2 V
Remarks
1
8.5 to 36
VDD [16]
VVDD = 8.5
VVDD = 8.0
V
VDD
u
V
VDRV
and V
REF
Widest line operation
2
4.75 to 8.5
VDRV [13]
VVDRV = 4.65 VVDRV = 4.3 V
VDRV
u
V
VDD
and V
REF
3
3.0 to 3.6
VREF [2]
VREF = 3.0
VREF= 2.5
V
REF
u
V
VDD
and V
VDRV
Needs regulated bias and low
VTH power MOSFETs
D
Mode 1, or normal operation requires the availability of a bias of 8.5 V or higher for the device. Here, the
bias drives the VDD pin. The low-side drive bias, V
VDRV
= 7 V, is generated from an internal linear regulator
and it directly draws current from the VDD pin. The high-side driver bias is a flying capacitor that is charged
from the VDRV pin through the G2 pin, when G2 is HI, via a diode between G2 and BST. The UCC2540
operates in Mode 1 if V
VDD
> (V
VDRV
and V
VREF
) when V
VREF
rises above 2 V. Mode 1 permits the widest
range of bias voltages, operational from 8.5 V < V
VDD
< 35 V. This mode is compatible with systems that
have a 12 V
DC
bias supply already available. Alternatively, Mode 1 is particularly useful for applications
where the input line voltage varies over a wide range and the bias is to be derived directly from the reflected
line voltage, such as in Fig. 13.
D
Mode 2 is suitable for applications where the bias is typically 5 V (between 4.5 V and 8.0 V). The bias
voltage is applied to the VDRV terminal of the UCC2540. The high-side driver bias is a flying capacitor that
is charged from the VDRV pin through the G2 pin, when G2 is HI. Bias voltage to the VDD pin is obtained
through an external voltage-doubler charge pump. If the system uses low threshold voltage power
MOSFETs, VDD can be directly tied to the VDRV pin. The bias voltage could be either a bus converter output
or an auxiliary supply, or the reflected converter input voltage that originates from a regulated source.
D
Mode 3 is for synchronous buck converter applications where the bias voltage is a regulated 3.3-V source.
This is a common main output voltage in multiple output power converters. The bias voltage is applied to
the VREF pin of the UCC2540. The UCC2540 operates in Mode 3 if it detects (V
VREF
> V
VDRV
and VDD)
when V
VREF
rises above 2 V.
Assorted combinations of modes and biasing schemes are shown in Figure 13 through Figure 18. In Mode 1
and Mode 2, the bias voltage can either be an independent auxiliary supply or it can be generated by rectifying
and filtering the reflected line voltage, as shown in Figure 13 through Figure 16. A regulated auxiliary supply
must be used with Mode 3 because the tolerance of the VREF voltage is the control tolerance of the UCC2540.
In Mode 3, the regulated auxiliary supply can be independent of the power supply input voltage (as shown in
Figure 18) or, the regulated auxiliary supply can be the same source as the power supply input voltage.
UCC2540
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APPLICATION INFORMATION
UDG-04038
Drive (7.2 V)
Regulator
VREF (3.3 V)
Regulator
Predictive
Logic
16
13
2
VDD
VDRV
VREF
BST
19
18
20
17
14
12
15
G1
SWS
SW
G2
G2S
PGND
High-Side
Driver
Low-Side
Driver
C1
D1
C2
C3
C4
Q1
Q2
D2
Vin
0 V
Rectified Bias
UCC2540
8.5 V
VVDD
35 V
8.5 V
VIN
35 V
Figure 13. Mode 1 With Rectified Biasing for Input Voltages Between 8.5 V and 35 V
Drive (7.2 V)
Regulator
VREF (3.3 V)
Regulator
Predictive
Logic
16
13
2
VDD
VDRV
VREF
BST
19
18
20
17
14
12
15
G1
SWS
SW
G2
G2S
PGND
High-Side
Driver
Low-Side
Driver
C1
D1
C2
C3
C4
Q1
Q2
Vin
0 V
AUX Bias
UCC2540
UDG-04039
8.5 V
VVDD
35 V
0 V
VIN
35 V
Figure 14. Mode 1 With Auxiliary Biasing for Bias Voltages Between 8.5 V and 35 V
UCC2540
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APPLICATION INFORMATION
UDG-04040
4.75 V
VVDRV
8.0 V
Drive (7.2 V)
Regulator
VREF (3.3 V)
Regulator
Predictive
Logic
16
13
2
VDD
VDRV
VREF
BST
19
18
20
17
13
12
11
G1
SWS
SW
G2
G2S
PGND
High-Side
Driver
Low-Side
Driver
C1
D1
C2
C3
C4
Q1
Q2
Rectified Bias
UCC2540
C5
D3
D4
D2
Vin
0 V
Figure 15. Mode 2 With Rectified Biasing for Input Voltages Between 4.75 V and 8.0 V
UDG-04041
4.75 V
VVDRV
8.0 V
0 V
VIN
35 V
Drive (7.2 V)
Regulator
VREF (3.3 V)
Regulator
Predictive
Logic
16
13
2
VDD
VDRV
VREF
BST
19
18
20
17
13
12
11
G1
SWS
SW
G2
G2S
PGND
High-Side
Driver
Low-Side
Driver
C1
D1
C2
C3
C4
Q1
Q2
AUX Bias
UCC2540
C5
D3
D2
Vin
0 V
Figure 16. Mode 2 With Auxiliary Biasing for Bias Voltages Between 4.75 V and 8.0 V
UCC2540
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APPLICATION INFORMATION
UDG-04042
Drive (7.2 V)
Regulator
VREF (3.3 V)
Regulator
Predictive
Logic
16
13
2
VDD
VDRV
VREF
BST
19
18
20
17
14
12
15
G1
SWS
SW
G2
G2S
PGND
High-Side
Driver
Low-Side
Driver
C1
D1
C2
C3
C4
Q2
Vin
0 V
AUX Bias
UCC2540
Q1
4.75 V
VVDRV
8.0 V
0 V
VIN
35 V
(Low VTH)
(Low VTH)
Figure 17. Mode 2 With Auxiliary Biasing for Bias Voltages Between 4.75 V and 8.0 V and Low Threshold
Power MOSFET Transistors
UDG-04043
4.75 V
3
VVDRV
3
8.0 V
(Low VTH)
(Low VTH)
1.8 V
3
VIN
3
5 V
Regulated 3.3-VDC Bias
Drive (7.2 V)
Regulator
VREF (3.3 V)
Regulator
Predictive
Logic
16
13
2
VDD
VDRV
VREF
BST
19
18
20
17
13
12
11
G1
SWS
SW
G2
G2S
PGND
High-Side
Driver
Low-Side
Driver
C1
D1
C2
C4
UCC2540
C5
D3
D2
Q2
Q1
DC or Pulse Train
Figure 18. Mode 3 With Regulated 3.3-V
DC
Bias
UCC2540
SLUS539A - JUNE 2004 - REVISED AUGUST 2004
24
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APPLICATION INFORMATION
Charge Pump Capacitor Selection
Capacitors C1 through C5 are all part of a charge distribution network that allows the UCC2540 to pass charge
to the MOSFET gates of Q1 and Q2 (all reference designators in this section refer to the schematics in Figure 13
through Figure 18). This section gives guidelines on selecting the values of C1 through C5 so that the converter
functions properly. Specific capacitor values may need to be larger than the recommended value due to
MOSFET characteristics, diode D1 D4 characteristics and closed-loop converter performance. All three
modes of operation require a charge pump capacitor and diode, C1 and D1, in order to drive the high-side power
MOSFET. Modes 2 and 3 require additional charge pump capacitors and diodes in order to supply voltage to
VDD. In general, all charge pump diodes should be Schottky diodes in order to have low forward voltage and
high speed. The charge pump capacitors should be ceramic capacitors with low effective series resistance
(ESR), such as X5R or X7R capacitors.
The value of the charge pump capacitor C1 depends on the power MOSFET gate charge and capacitance, the
voltage level of the Miller plateau threshold, the forward drop of D1 and the closed-loop response time. The
unloaded high-side gate driver typically draws 2 nC of charge per rising edge plus 30
A of direct current from
C1. Usually, the unloaded high-side gate driver load is miniscule compared to the gate charge requirements
of the high-side power MOSFET, Q1. Typical values for C1 are approximately 50 to 100 times the input
capacitance (C
ISS
) of MOSFET Q1. This usually allows for transient operation at extremely large duty ratio,
where C1 does not have sufficient time to fully recharge. If C1 is excessively large, its ESR and ESL prevents
it from recharging during transients, including the start-up transient.
Capacitors C2 through C5 are then selected based on the direction of charge transfer and the requirements of
the UCC2540. Selection guidelines are shown in Table 2. Keep in mind that each converter design may require
adjustments for larger capacitor ratios than those that are suggested in Table 2. The selection process begins
at the left side of Table 2 and progresses towards the right side of the table, which is the reverse order of the
charge flow during the first few cycles of start-up. If iteration is required in the design process, review the
progression of the capacitors in the order from left to right that is shown in the table.
Table 2. Charge Pump and Bias Capacitor Selection Guidelines
Mode
High-Side Drive
Capacitor (
0.1
F)
VDRV Filter
Capacitor
VREF Filter
Capacitor
VDD Filter
Capacitor
VDD Charging
Capacitor
1
C1 > 50 CISS
C3 > 2
C1
C2 > 0.1
F
C4 > 1
F
n/a
2
C1 > 50 CISS
C3 > 2
C1
C2 > 0.1
F
C4 > 1
F, 2
C3
C5 > 2
C4
3
C1 > 50 CISS
C4 > 1
F
2
C1
C2 > 1.0
F
C4 > 1
F, 2
C1
C5 > 2
C4
For Modes 2 and 3, the VDD filter capacitor, C4, in Table 2 must supply the I
VDD
idle current to the UCC2540
(approximately 11 mA) plus the charge to drive the gates G1 and G2. Capacitor C4 must be large enough to
sustain adequate operating voltages during start-ups and other transients under the full operational I
VDD
current. Knowing the operating frequency and the MOSFET gate charges (Q
G
), the average I
VDD
current can
be estimated as:
I
VDD
+
I
VDD(idle)
)
Q
G1
)
Q
G2
f
S
D
where f
S
is switching frequency
In order to prevent noise problems, C4 must be at least 1
F. Furthermore, it needs to be large enough to pass
charge along to the power MOSFET gates. Thus C4 often needs to have at least twice the capacitance of the
VDRV filter capacitor, as shown in Table 2.
(4)
UCC2540
SLUS539A - JUNE 2004 - REVISED AUGUST 2004
25
www.ti.com
APPLICATION INFORMATION
Output Stage
The UCC2540 includes dual gate drive outputs and each is capable of
3-A peak current. The pull-up/ pull-down
circuits of the driver are bipolar and MOSFET transistors in parallel. High-side and low-side dual drivers provide
a true 3-A high-current capability at the MOSFET's Miller Plateau switching region where it is most needed. The
peak output current rating is the combined current from the bipolar and MOSFET transistors. The output
resistance is the R
DS(on)
of the MOSFET transistor when the voltage on the driver output is less than the
saturation voltage of the bipolar transistor.
The output drivers can switch from VDD to GND. Each output stage also provides a very low impedance to
overshoot and undershoot. This means that in many cases, external-schottky-clamp diodes are not required.
The outputs are also designed to withstand 500-mA reverse current without either damage to the device or logic
upset.
For additional information on drive current requirements at MOSFET's Miller plateau region, refer to the Power
Supply Seminar SEM-1400
[2]
and the UCC37323/4/5 datasheet
[3]
.
Predictive Gate Drive
TM
Technology
The Predictive Gate Drive
technology maximizes efficiency by minimizing body diode conduction. It utilizes
a digital feedback system to detect body diode conduction, and adjusts the deadtime delays to minimize the
conduction time interval. This closed loop system virtually eliminates body diode conduction while adjusting for
different MOSFETs, temperature, and load dependent delays. Since the power dissipation is minimized, a
higher switching frequency can be utilized, allowing for a smaller component size. Precise gate timing at the
nanosecond level reduces the reverse recovery time of the synchronous rectifier MOSFET body diode, which
reduces reverse recovery losses seen in the main (high-side) MOSFET. Finally, the lower power dissipation
results in increased reliability.
19 BST
20
17
18
14
G1
SWS
SW
G2
12
15
G2S
PGND
Predictive
Logic
VDRV
UDG-02149
Figure 19.
For additional information on Predictive Gate Drive
control and efficiency comparisons to earlier adaptive
delay and adaptive control techniques, refer to the UCC27223 datasheet
[3]
.
UCC2540
SLUS539A - JUNE 2004 - REVISED AUGUST 2004
26
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APPLICATION INFORMATION
VDD and IDD
Although quiescent VDD current is low, total supply current is higher, depending on output gate drive
requirements and the programmed oscillator frequency. Total VDD current (I
VDD
) is the sum of quiescent VDD
current and the average output currents of G1 and G2, as described in equation (3). Knowing the operating
frequency and the MOSFET gate charge (Q
G
), average driver output current, per gate, can be calculated from:
I
G
+
Q
G
f
S
where
D
f
S
is switching frequency
To prevent noise problems, connect a 1-
F ceramic capacitor between the VDD and GND pins. Place the 1-
F
ceramic capacitor as close to the UCC2540 as possible. This capacitor is in addition to any electrolytic energy
storage capacitors that may be used in the bias supply design.
Soft-Start and Tracking Features
Separate pins are provided for the soft-start feature and the tracking feature. Soft-start or tracking (sequencing)
can be easily implemented with this configuration using a minimum number of external components. During a
power-up transient, the converter output tracks the lower of the SS voltage, the TR voltage or a 1.5-V internal
reference, provided the system is not in current limit. In other words, the voltage control loop is closed during
power-up, provided the system is not current limited. Figure 20 shows the UCC2540 configured for soft-start
operation. For applications that do not use the tracking feature, connect the TR pin to either SS or REF, as shown
in the figure. Remote shutdown and sequential power-up can be easily implemented as a transistor switch
across C
SS
.
UDG-04045
CSS
1.33
y
IRSET
1.73
y
IRSET
TR
10
11
7
SS
VEA-
UCC2540
+
+
+
+
50 mV
1.5 V
Voltage
Error
Amplifier
COMP
REF (3.3 V)
To Positive Input of
Current Error Amplifier
HUP
UVLO
+
0.7 V
Figure 20. Using the Soft-Start Feature
(5)
UCC2540
SLUS539A - JUNE 2004 - REVISED AUGUST 2004
27
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APPLICATION INFORMATION
The soft-start interval begins when the UCC2540 recognizes that the appropriate voltage (see Mode 1, 2 or 3)
is above the UVLO level. The voltage of C
SS
then linearly increases until it is clamped at the REF voltage of
3.3V. Regulation should be reached when the soft-start voltage reaches about 2.2 V (1.5 V plus a diode drop).
Select a C
SS
capacitor value using equation (5) to program a desired soft-start duration,
t
SS
.
C
SS
+
1.33
V
RSET
R
SET
D
t
SS
D
V
SS
+
1.33
1.5 V
R
SET
D
t
SS
2.2 V
Farads
If a UVLO fault is encountered, both outputs of the UCC2540 are disabled and the soft-start pin (SS) is
discharged to GND. The UCC2540 does not retry until the UVLO fault is cleared.
Using the TR pin, the UCC2540 can be programmed to track another converter output voltage. If the voltage
to be tracked is between 0 V and 3.3 V, simply connect the TR pin to the voltage to be tracked with a resistor
that is approximately equal to the DC impedance that is connected to the VEA- terminal (R
V1
|| R
V2
, in Figure 6).
If the voltage is above that range, use a voltage divider, again with an equivalent resistance that approximately
equals the DC impedance that is connected to the VEA- terminal. Other strategies can be used to achieve
sequential, ratiometric or simultaneous power supply tracking
[14
].
An implementation of sequential sequencing of a multiple output power supply
[5]
is shown in Figure 21.
Applications where the loads include a processor with a core voltage of 1.5 V and I/O ports that require 3.3 V
can require sequential sequencing in order to resolve system level bus contention problems during start-up.
In this circumstance the core must power-up first, then after an initialization period of 130 ms, the ports are
allowed to power-up.
UDG-04061
G1
TR
G2
UCC2540
SS
From Transformer Secondary
VDD
TPS3103K33
GND
PFI
G1
TR
G2
UCC2540
SS
Core
1.5 V
5 V
0 V
I/O
3.3 V
REF
1.6 k
1 k
10 k
CSS
CSS
RESET
MR
PFO
Figure 21. Sequencing a Multiple Output Post Regulated Power Supply
(6)
UCC2540
SLUS539A - JUNE 2004 - REVISED AUGUST 2004
28
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APPLICATION INFORMATION
UDG-04061
Regulation loss due to
loss of primary line
voltage
VI/O
t - Time
1.5
0
1.43
3.3
130 ms
V - V
o
ltage - V
VCORE
Figure 22.
Using the TR pin, the UCC2540 can be programmed to ratio-metrically track another converter output voltage
[5]
.
Ratio-metric tracking is when the ratio of the output voltages is constant from zero volts to the point where one
or more of the outputs lock into regulation. The TR pin is easier to use for tracking than the SS pin because the
external currents that would be applied to the SS pin may interfere with SS discharge currents and fault recovery.
It should be understood that the voltage that is being tracked must lag the bias voltages (VDD, VDRV and REF)
on start-up and lead the bias voltages during shutdown. Furthermore, the output that is being tracked must not
reach its steady state DC level before the output that is tracking reaches its steady state DC level. Figure 23
illustrates the concept of programming an output voltage V
C
, to ratio-metrically track another output, V
M
.
UDG-04061
VC
Tracking Ratio
(Tracker)
(Tracker)
(Tracker)
(Leader)
(Leader)
(Leader)
ratio-metric
sequencing
ratio-metric
sequencing
simultaneous
sequencing
(a)
(b)
(c)
Main Power Supply
(Leader)
+
Core Power Supply
(Trader)
+
UCC2540
7
TR
VM
VM
MM
MC
MM
MC
VM
VC
VC
VM
VC
MM
MC
A
T
^
M
C
M
M
Figure 23. Ratio-Metric Tracking
UCC2540
SLUS539A - JUNE 2004 - REVISED AUGUST 2004
29
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APPLICATION INFORMATION
The general circuit to program the UCC2540 to track the leader supply voltage by the tracking ratio A
T
is shown
in Figure 24. To program the tracking profile gains G
T1
and G
T2
, follow the ratio-metric tracking design procedure
that is listed below. The special case of simultaneous sequencing for V
M
> 1.5V is the simplest to design; set
R
T1
= R
V1
and R
T2
= R
V2
, G
T2
is not needed. In many other cases, the circuit can be simplified with the removal
of the operational amplifier for G
T2
and the Zener clamping diode. If an operational amplifier is necessary, it
should be capable of rail to rail operation and usually low voltage bias; the TLV271 is an inexpensive solution
for both of those requirements. Notice that the tracking circuit in Figure 24 also has a soft-start capacitor, C
SS
.
The soft-start capacitor is useful for limiting the time between short-circuit retry attempts and it can prevent
overshoot when recovering from a fault that is experienced in only the tracking supply but not the main supply.
Ratio-Metric Tracking Design Procedure (see Figures 21 and 22)
1.
Determine the tracking ratio, A
T
.
A
T
+
M
C
M
M
where M
C
and M
M
are the soft-start slopes of V
C
and V
M
, respectively.
2.
Determine G
V
.
G
V
+
R
V2
R
V1
)
R
V2
where R
V2
and R
V1
are selected when designing the voltage control loop.
3.
Test G
T2
if necessary when V
M
1.5 V or A
T
G
V
> 1.
a.
If G
T2
is needed, set GT2 so that both equations (8) and (9) apply.
G
T2
+
1
)
R
F1
R
F2
so that both of the following apply:
G
T2
+
1.5 V
V
M
G
T1
and
G
T2
u
A
T
G
V
b.
If G
T2
is not needed, set G
T2
= 1.
4.
Set G
T1
.
G
T1
+
A
T
G
V
G
T2
+
R
T2
R
T1
)
R
T2
5.
Select R
T1
and R
T2
so that R
T1
|| R
T2
R
V1
|| R
V2
to minimize offset differences.
(7)
(8)
(9)
(10)
(11)
UCC2540
SLUS539A - JUNE 2004 - REVISED AUGUST 2004
30
www.ti.com
UDG-04059
Use GT2 stage if
ATGV > 1 OR if
VMGT1
1.5 V at
steady-state
Main
Power
Supply
(Leader)
G1
TR
VEA-
G2
UCC2540
SS
CSS
3.3 V
+
0 V
Rectified Secondary Voltage
+
+
G
T2
+
1
)
R
F1
R
F2
G
T1
+
R
T2
R
T1
)
R
T2
RF2
RF1
TLV271
RT2
RT1
*DZ
*DZ needed only if VMGT1GT2 > 3 V
G
V
+
R
V2
R
V1
)
R
V2
RV2
RV1
VC
VM
nVIN
Determined by voltage loop design
Figure 24. Programming the UCC2540 to Track Another Output
More elaborate power supply sequencing and tracking can easily be implemented by extending the above
techniques. Consult reference [5] for further information
THERMAL INFORMATION
The useful temperature range of a controller that contains high-current output drivers is greatly affected by the
drive power requirements of the load and the thermal characteristics of the device package. In order for a power
driver to be useful over a particular temperature range the package must allow for the efficient removal of the
heat produced while keeping the junction temperature within rated limits. The UCC2540 is available in the 20-pin
HTSSOP PowerPAD
t
package.
The PowerPAD
TM
HTSSOP-20 (PWP) offers the most effective means of removing the heat from the
semiconductor junction and therefore long term reliability improvement. As illustrated in [5], the PowerPAD
packages offer a leadframe die pad that is exposed at the base of the package. This pad is soldered to the
copper on the PC board directly underneath the device package, reducing the
jc down to 2
C/W. Data is
presented in [5] to show that the power dissipation can be quadrupled in the PowerPAD configuration when
compared to the standard packages. The PC board must be designed with thermal lands and thermal vias to
complete the heat removal subsystem, as summarized in [6] to realize a significant improvement in heat-sinking
over standard non-PowerPAD surface mount packages.
UCC2540
SLUS539A - JUNE 2004 - REVISED AUGUST 2004
31
www.ti.com
TYPICAL CHARACTERISTICS
Figure 25
TJ - Junction Temperature -
C
V
VREF
- Reference V
oltage - V
OUTPUT REFERENCE VOLTAGE
vs
TEMPERATURE
-50
3.25
3.20
0
3.35
3.30
3.40
50
100
150
-325
-315
-285
-295
-275
-50
0
50
100
150
-305
Figure 26
RAMP CURRENT
vs
TEMPERATURE
I RAMP
- Ramp Current -
A
TJ - Junction Temperature -
C
RRSET = 10 k
0.5
-50
0
50
100
150
0.6
1.0
0.9
1.1
0.8
0.7
Figure 27
TJ - Junction Temperature -
C
A/
A
I
G2C
/I
RAMP
AND I
SS
/I
RAMP
vs
TEMPERATURE
IG2C/IRAMP, RRSET = 10 k
IG2C/IRAMP, RRSET = 50 k
ISS/IRAMP, RRSET = 10 k
ISS/IRAMP, RRSET = 50 k
6.8
7.6
7.4
7.2
7.0
-50
0
50
100
150
Figure 28
REGULATOR OUTPUT VOLTAGE
vs
TEMPERATURE
V
VDR
V
- Regulator Output V
o
ltage - V
TJ - Junction Temperature -
C
MODE 1
UCC2540
SLUS539A - JUNE 2004 - REVISED AUGUST 2004
32
www.ti.com
TYPICAL CHARACTERISTICS
Figure 29
TJ - Junction Temperature -
C
V
TR(OS)
- Offset V
oltage - mV
TRACKING TO VOLTAGE ERROR AMPLIFIER OFFSET
vs
TEMPERATURE
0
10
60
50
70
40
30
20
-50
0
50
100
150
Figure 30
CURRENT ERROR AMPLIFIER OFFSET
vs
TEMPERATURE
V
CEA-
- Current Error Amplifier Offset V
oltage -
m
V
TJ - Junction Temperature -
C
45
47
53
55
51
49
-50
0
50
100
150
Figure 31
TJ - Junction Temperature -
C
V
SYNCHIN
-
T
iming
Signal
V
oltage - V
SYNCIN THRESHOLD VOLTAGE
vs
TEMPERATURE
1.50
1.55
1.75
1.70
1.80
1.65
1.60
-50
0
50
100
150
5
0
-5
-25
-10
-15
10 k
100 M
1 k
1 M
-90
-45
-180
-135
0
-225
-270
100 k
10 M
-20
Phase
Gain
f - Frequency - Hz
INVERTING AMPLIFIER GAIN AND PHASE
vs
FREQUENCY
Gain -
d
B
Phase -
Figure 32
UCC2540
SLUS539A - JUNE 2004 - REVISED AUGUST 2004
33
www.ti.com
TYPICAL CHARACTERISTICS
20
100
80
120
60
40
0
-20
-40
100
1 k
10 M 100 M
10
-90
-45
-180
-135
0
100 k 1 M
10 k
1
Figure 33
f - Frequency - Hz
CURRRENT ERROR AMPLIFIER GAIN AND PHASE
vs
FREQUENCY
Phase
Gain
Gain -
d
B
Phase -
120
-90
-45
-180
-135
0
100
1 k
10 M 100 M
10
100 k 1 M
10 k
1
20
100
80
60
40
0
-20
-40
Figure 34
VOLTAGE ERROR AMPLIFIER GAIN AND PHASE
vs
FREQUENCY
f - Frequency - Hz
Phase
Gain
Gain - dB
Phase -
Figure 35
VVDD - Bias Voltage - V
OPERATING CURRENT (DC)
vs
BIAS VOLTAGE
I VDD
- Bias Current - mA
5
15
25
30
40
0
35
10
20
0
2
12
10
8
6
4
UCC2540
SLUS539A - JUNE 2004 - REVISED AUGUST 2004
34
www.ti.com
TYPICAL CHARACTERISTICS
Figure 36. Predictive Gate Drive - G2 Falling
G2 Lower Gate
Drive (5V/div)
SW Node
(5V/div)
t - Time - 20 ns/div
Figure 37. Predictive Gate Drive - G2 Falling
G2 Lower Gate
Drive (5V/div)
SW Node
(500 mV/div)
t - Time - 20 ns/div
Synchronous
FET Body Diode
Conduction
Predictive
Delay
Adjustment
Figure 38. Predictive Gate Drive - G2 Falling
t - Time - 20 ns/div
Predictive
Delay
Adjustment
G2 Lower Gate Drive
SW Node
UCC2540
SLUS539A - JUNE 2004 - REVISED AUGUST 2004
35
www.ti.com
RELATED PRODUCTS
D
UCC28089 Primary Side Push-Pull Oscillator
D
UCC27223 High Efficiency Predictive Synchronous Buck Driver with Enable
D
UCC3583 Switch Mode Secondary Side Post Regulator
D
UCC25701 Advanced Voltage Mode Pulse Width Modulator
D
UCC3808A Low-Power Currrent-Mode Push-Pull PWM
D
UCC38083/4/5/6 8-Pin Current-Mode Push-Pull PWM with Programmable Slope Compensation
REFERENCES
1.
Power Supply Seminar SEM-1300 Topic 1: Unique Cascaded Power Converter Topology for High Current
Low Output Voltage Applications, by L. Balogh, C. Bridge, and B. Andreycak, (SLUP118)
2.
Power Supply Seminar SEM-1400 Topic 2: Design And Application Guide For High Speed MOSFET Gate
Drive Circuits, by L. Balogh, (SLUP133)
3.
Datasheet, UCC27223 High Efficiency Predictive Synchronous Buck Driver, (SLUS558)
4.
Datasheet, UCC37323/4/5 Dual 4-A Peak High Speed Low-Side Power MOSFET Drivers, (SLUS492A)
5.
Power Supply Seminar SEM1600 Topic 2: Sequencing Power Supplies in Multiple Voltage Rail
Environments, by D. Daniels, D. Gehrke, and M. Segal, (SLUP224)
6.
Technical Brief, PowerPAD Thermally Enhanced Package, (SLMA002)
7.
Application Brief, PowerPAD Made Easy, (SLMA004)
8.
Datasheet, TPS3103K33 Ultra-Low Supply Current/Supply Voltage Supervisory Circuits, (SLVS363)
9.
Application Note, A Revolutionary Power Management Solution for Highly Efficient, Multiple Output
Applications, by Bill Andreycak, (SLUA255)
10. Application Note, Predictive Gate Drive
E
FAQ, by Steve Mappus (SLUA285)
UCC2540
SLUS539A - JUNE 2004 - REVISED AUGUST 2004
36
www.ti.com
MECHANICAL DATA
PWP (R-PDSO-G**)
PowerPAD
PLASTIC SMALL-OUTLINE
4073225/F 10/98
0,50
0,75
0,25
0,15 NOM
Thermal Pad
(See Notes D and F)
Gage Plane
28
24
7,70
7,90
20
6,40
6,60
9,60
9,80
6,60
6,20
11
0,19
4,50
4,30
10
0,15
20
A
1
0,30
1,20 MAX
16
14
5,10
4,90
PINS **
4,90
5,10
DIM
A MIN
A MAX
0,05
Seating Plane
0,65
0,10
M
0,10
0
- 8
20 PINS SHOWN
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusions.
D. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane.
This pad is electrically and thermally connected to the backside of the die and possibly selected leads.
E. Falls within JEDEC MO-153
F. The PowerPAD
t
is not directly connected to any lead of the package. It is electrically and thermally connected to the substrate of
the device which acts as ground and should be connected to PGND on the PCB. The exposed dimension is 1.3 mm x 1.7 mm.
However, the tolerances can be +1.05 mm / -0.05 mm (+41 mils / -2 mils) due to position and mold flow variation.
Powe
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enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI's terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
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Use of such information may require a license from a third party under the patents or other intellectual property
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Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
Telephony
www.ti.com/telephony
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright
2004, Texas Instruments Incorporated
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