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Электронный компонент: UC2726DWPTR

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750mA Output Drive, Source or Sink
8 to 35V Operation
Transmits Drive Logic and Power
through Low Cost Transformer
Programmable Operating Frequency
Up to 750kHz Operation
Improved Output Control Algorithm
Minimizes Output Jitter
Fault Logic Monitors Isolated High
Side IGBT Driver UC1727 for Faults
User Programmable Fault Timing
Screens False Fault Signals
Shutdown Mode Disables On Chip
Logic Reference for Low Standby
Power
Optional External Biasing of Logic
Circuitry can Reduce Overall Power
Dissipation
The UC1726 Isolated Drive Transmitter, and its companion chip, the
UC1727 Isolated High Side IGBT Driver, provide a unique solution to driv-
ing isolated power IGBTs. They are particularly suited to drive the high
side devices on a high voltage H-bridge. The UC1726 device transmits
the drive logic and drive power, along with transferring and receiving fault
information with the isolated gate circuit using a low cost pulse trans-
former.
This drive system utilizes a duty cycle modulation technique that gives in-
stantaneous response to the drive control transitions, and reliably passes
steady state, or DC conditions. High frequency operation, up to 750kHz,
allows the cost and size of the coupling transformer to be minimized.
The UC1726 can be powered from a single V
CC
supply which internally
generates a voltage reference for the logic circuitry. It can also be placed
into a low power shutdown mode that disables the internal reference. The
IC's logic circuitry can be powered from an external supply, V
L
, to mini-
mize overall power dissipation. Fault logic monitors the Isolated High Side
IGBT Driver UC1727 for faults. Based on user defined timing, the
UC1726 distinguishes valid faults, which it responds to by setting the fault
latch pin. This also disables the gate drive information until the fault reset
pin is toggled to a logic one.
The UC1726 operates over an 8 to 35 volt supply range. The typical V
CC
voltage will be greater than 28 volts to be compatible with the UC1727.
The undervoltage lockout circuitry of the Isolated High Side IGBT Driver
UC1727 locks out the drive information during its undervoltage lockout.
Isolated Drive Transmitter
FEATURES
DESCRIPTION
BLOCK DIAGRAM
UC1726
UC2726
UC3726
7/95
UDG-94004-1
CONNECTION DIAGRAMS
UC1726
UC2726
UC3726
ABSOLUTE MAXIMUM RATINGS
Supply Voltage V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40V
Source/Sink Current (Pulsed). . . . . . . . . . . . . . . . . . . . . . 1.5A
Source/Sink Current (Continuous) . . . . . . . . . . . . . . . . . . 1.0A
Output Voltage (pins 12, 14). . . . . . . . . .
-
0.3 to (V
CC
+ 0.3)V
C
F
, F
RESET
, FAULT, SHTDWN,
F
LATCH
, V
L
, PHI, R
T
. . . . . . . . . . . . . . . . . . . . . . .
-
0.3 to 6.0V
C
T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 to 6.0V
Operating Junction Temperature (Note 2) . . . . . . . . . . 150
C
Storage Temperature Range . . . . . . . . . . . . .
-
65
C to 150
C
Lead Temperature (Soldering, 10 seconds). . . . . . . . . 300
C
Note 1: All voltages are with respect to GND (Pin 2); all
currents are positive into, negative out of part.
Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +9 to +35.0V
Sink/Source Current (each output) . . . . . . . . . . . . . . . 0 to 750mA
Timing Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4k to 200k
Timing Capacitor (C
T
). . . . . . . . . . . . . . . . . . . . . . . 75pF to 2.0nF
Timing Capacitor (C
F
). . . . . . . . . . . . . . . . . . . . . . . 75pF to 3.0nF
Note 2: See Unitrode Integrated Circuits databook for information
regarding thermal specifications and limitations of
packages.
Note 3: Range over which the device is functional and parameter
limits are guaranteed.
RECOMMENDED OPERATING CONDITIONS
(Note 3)
DIL-16 (Top View)
N Package
DIL-16 (Top View)
SP Package
DIL-18 (Top View)
J Package
SOIC-28 (Top View)
DWP Package
PACKAGE PIN FUNCTION
FUNCTION
PIN
GND
1
C
T
2
N/C
3-4
R
T
5
SHTDWN
6
V
L
7
V
CC
8
N/C
9
PV
CC
10
OUTB
11
PGND
12-18
GND
19
OUTA
20
PHI
21
F
LATCH
22
F
RESET
23
FAULT
24
N/C
25
C
F
26
N/C
27
N/C
28
PLCC-28 (Top View)
QP Package
2
UC1726
UC2726
UC3726
PARAMETERS
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Retriggerable one shot
Initial Accuracy
T
J
= 25
C
1.400
1.600
1.800
sec
Temperature Stability
Over operating T
J
1.000
2.200
sec
Voltage Stability
V
CC
= 10 to 35V
0.2
%/V
Operating Frequency
L
LOAD
= 1.5mH
170
kHz
PHI Input (Control Input)
HIGH Input Voltage
2.0
V
LOW Input Voltage
0.8
V
HIGH Input Current
10
A
LOW Input Current
-300
-
600
A
Delay to one shot
100
250
nsec
Delay to Output
C
T
= 1.4V
250
nsec
Output Drivers
Output Low Level
I
SINK
= 20mA
0.3
0.5
V
I
SINK
= 400mA
0.5
2.6
V
Output High Level
I
SOURCE
=
-
20mA
2.0
2.6
V
(volts below V
CC
)
I
SOURCE
=
-
400mA
2.0
2.9
V
Rise and Fall Times
No load
30
60
nsec
Logic Voltage Reference
V
L
- Logic Voltage
Internal Voltage
4.20
4.40
4.60
V
Logic Supply Current
V
L
= 4.75V to 5.25V, C
T
= 1.4V
13.0
20.0
mA
Shut Down Circuit
Logic Voltage - Off
0.5
V
High Input Current
V
IH
= 2.4
-100
A
Low Input Current
V
IL
= 0.4
-20
A
Fault Logic
Fault Reset High Input Current
V
IH
= 2.4
5
A
Fault Reset Low Input Current
V
IL
= 0.4
-10
A
Fault High Input Current
V
IH
= 2.4
5
A
Fault Low Input Current
V
IL
= 0.4
-60
A
Fault Pulse Width
C
F
= 330pF
3.0
s
C
F
= 2.2nF
17.0
s
Fault Latch, V
OH
I
LOAD
=
-
1mA, Volts below V
L
1.3
1.8
V
Fault Latch, V
OL
I
LOAD
= 1mA
0.25
0.5
V
Fault Latch, V
OH
I
LOAD
= 0, Volts below V
L
0.3
V
Fault Latch, V
OL
I
LOAD
= 0
0.2
V
Fault Reset Pulse Width
500
ns
UVLO
Turn On Threshold
7.1
V
Total Supply Current
Supply Current
C
T
= 1.4V
22
40
mA
C
T
= 1.4V, V
L
= 5.0V
12
20
mA
C
T
= 1.4V, Shutdown = 5.0V
2.5
mA
Unless otherwise stated, V
CC
= 20V, R
T
= 4.32k
, C
T
= 330pF and C
F
= 2.2nF, no
load on any output, and
-
55
C < T
A
< 125
C for the UC1726,
-
40
C < T
A
< 85
C for
the UC2726, and 0
C < T
A
< 70
C for the UC3726, T
A
= T
J
.
ELECTRICAL CHARACTERISTICS:
3
UC1726
UC2726
UC3726
PIN DESCRIPTIONS
C
F
: The timing input to the fault logic. A capacitor is
placed across the input of C
F
and ground. The timing win-
dow is approximately t = 2.1C
F
R
T
.
C
T
: The connection to the timing capacitor that controls
the operating frequency. A capacitor to ground is repeti-
tively charged during the one shot pulse width. It is dis-
charged when a comparator senses zero current in the
primary side of the transformer. The one shot pulse width
is consequently determined by the time it takes to charge
the capacitor from a threshold voltage of V
L
/4 to V
L
/2.
This pin must be tied to a capacitor. See Recommended
Operating Conditions.
FAULT: This input to the fault logic initiates the user pro-
grammable timer. This time interval, specified by the ca-
pacitor on C
F
, determines the validity of the fault. The pin
is tied to a low cost optocoupler, and is high until the
UC1727 sends drive information from the PHI pin through
the transformer while the FAULT pin stays low. Once this
pin goes high, it must stay high during the entire fault win-
dow to be accepted as a valid fault. A valid fault sets the
F
LATCH
pin high and prevents the transmitting of gate
drive information until the F
RESET
is toggled high. If fault
logic is not used, the FAULT pin must be grounded.
F
LATCH
: A valid fault sets this pin to a logic one and pre-
vents the transmitting of gate drive information. The
F
LATCH
pin can only be reset by connecting the F
RESET
to
a logic 0.
F
RESET
: The input to the fault logic that resets the fault
logic latch (F
LATCH
) and enables drive transmit data. This
input must be low when powered up and stay low until af-
ter the fault latch has been set.
GND: The signal and power ground for the device. The
power ground of the output transistor is isolated on the
chip from the substrate ground which biases the remain-
der of the device.
OUTA: One output of the two totem pole outputs con-
nected across the transformer primary winding. When
PHI is high, the output toggles between 0.3V during the
one shot charge time and approximately V
CC
+ 0.4V dur-
ing the remainder of the period. When PHI is low the out-
put toggles between V
CC
- 2V during the one shot charge
time and approximately 0.6V
CC
during the remainder of
the period.
OUTB: One output of the two totem pole outputs con-
nected across the transformer primary winding. When
PHI is high, the output toggles between V
CC
- 2V during
the one shot charge time and approximately 0.6V
CC
dur-
ing the remainder of the period. When PHI is low the out-
put toggles between 0.3V during the one shot charge
time and approximately V
CC
+ 0.4V during the remainder
of the period.
PGND: This is the ground for the output transistors
bonded in the 28 pin packages. On the sixteen pin pack-
ages it is bonded separately to the GND pin.
PHI: A logic control input to the isolated gate drive that
changes the outputs as described above. This changes
the duty cycle of the voltage wave form applied across
the transformer. The Isolated High Side IGBT Driver
UC1727 senses the different duty cycles as different
drive commands.
PV
CC
: This is the input voltage for the output transistors
on the 28 pin package. On the sixteen pin packages it is
bonded separately to the V
CC
pin.
R
T
: The input that sets the C
T
and C
F
capacitor currents
with a resistor to ground. The voltage on R
T
is approxi-
mately 0.3V
L
. The resulting charge currents are: IC
T
=
IC
F
= V
L
/ 4R
T
.
SHTDWN: This input shuts down the internal reference. A
TTL logic one puts the UC1726 into a low standby current
mode. This input has a pull down resistor on the chip to
guarantee proper operation when left open. If an external
logic voltage is applied to V
L
, this shutdown feature can-
not be used without bringing the external voltage source
to zero volts.
V
CC
: The input voltage that biases the outputs and the in-
ternal reference. It can vary between 8V to 35V. This sup-
ply pin will typically be greater than 28V to be compatible
with the UC1727. In order to minimize power dissipation
use an external logic supply, V
CC
approximately 15V, and
a step up transformer (N = 2).
V
L
: The logic supply pin that biases all circuits except for
the totem pole outputs. A bypass capacitor is recom-
mended on this pin when left unconnected. The internal
reference is approximately 4.4V. A 5.0V supply can be
applied to this pin to assure minimum power dissipation.
When an external supply higher than the V
L
voltage is
applied to this pin, the internal reference turns off.
Refer to Typical Application on Page 5 and Application Note U-143A "New Chip Pair Provides Isolated Drive
for High Voltage IGBTs"
4
UC1726
UC2726
UC3726
TYPICAL APPLICATION
UNITRODE INTEGRATED CIRCUITS
7 CONTINENTAL BLVD.
MERRIMACK, NH 03054
TEL. (603) 424-2410

FAX (603) 424-3460
IF FAULT LOGIC NOT USED, GROUND FAULT PIN.
UDG-94006
The chip operating frequency is determined by the values
of components connected to the R
T
and C
T
pins. A resis-
tor connected between R
T
and ground sets the charge
current to IC
T
= V
L
/ 4R
T
. The operating frequency varies
slightly depending on the V
CC
and V
L
voltages. The fol-
lowing equations approximate the one shot pulse width at
operating frequency when V
CC
= 20V.
T
PW
= 1.1R
T
(C
T
+ 50pF)
F
O
=
1
3.3
R
T
(
C
T
+
50pF
)
The 50pF additional capacity represents internal chip ca-
pacitance at the C
T
input.
OPERATING FREQUENCY:
5
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