TWL1102
VOICE-BAND AUDIO PROCESSOR (VBAP
TM
)
SLVS264 NOVEMBER 1999
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
2.7-V Operation
D
Two Differential Microphone Inputs, One
Differential Earphone Output, and One
Single-Ended Earphone Output
D
Programmable Gain Amplifiers for
Transmit, Receive, Sidetone, and Volume
Control
D
Earphone Mute and Microphone Mute
D
On-chip I
2
C-Bus, Which Provides a Simple,
Standard, Two-Wire Serial Interface With
Digital ICs
D
Programmable for 15-Bit Linear Data or
8-Bit Companded (
-Law or A-Law) Data
D
Available in a 32-Terminal TQFP Package
D
Designed for Analog and Digital Wireless
Handsets and Telecommunications
Applications
D
Dual-Tone Multi-Frequency (DTMF) and
Single Tone Generator
D
Pulse Density Modulated (PDM) Buzzer
Output
description
The voice-band audio processor (VBAP) is designed to perform the transmit encoding analog/digital (A/D)
conversion and receive decoding digital/analog (D/A) conversion, together with transmit and receive filtering
for voice-band communications systems. The device operates in either the 15-bit linear or 8-bit companded
(
-law or A-Law) mode, which is selectable through the I
2
C interface. From a 2.048-MHz master clock input,
the VBAP generates its own internal clocks.
PBS PACKAGE
(TOP VIEW)
31
30
29
28
27
9
10
PCMO
PCMI
DV
SS
DV
DD
SCL
SDA
NC
NC
PLLV
DD
EARV
SS
EAR1ON
EARV
DD
EAR1OP
EARV
SS
EAR2O
AV
DD
32
26
11
12
13
14
15
MBIAS
MIC1P
MIC1N
MIC2P
NC
16
25
1
2
3
4
5
6
7
8
24 23 22 21 20 19 18 17
MIC2N
REXT
AV
SS
MCLK
PLL
V
SS
V
SS
RESET
PWRUPSEL
BUZZCON
PCMSYN
PCMCLK
NC No internal connection
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These
circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C,
Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated
voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device
should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level,
preferably either VCC or ground. Specific guidelines for handling devices of this type are contained in the publication Guidelines for
Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments.
Copyright
1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
VBAP is a trademark of Texas Instruments Incorporated.
TWL1102
VOICE-BAND AUDIO PROCESSOR (VBAP
TM
)
SLVS264 NOVEMBER 1999
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
functional block diagram
PCMIN
PCMSYN
PCMCLK
MIC1P
MIC1N
MIC2P
MIC2N
MIC
Amplifier
1
g =
23.5 dB
MIC
Amplifier
2
g = 12 dB
or
0 dB
Analog
Modulator
TX Filter
and PGA
g = 10 dB
to
0 dB
PCM
Interface
Sidetone
g = 24 dB
to
12 dB
RX V
o
l
Control
g = 18 dB
to
0 dB
RX Filter
and PGA
g = 6 dB
to
+6 dB
Digital
Modulaor
and Filter
Ear
Amp1
Ear
Amp2
DTMF
Generator
Control Bus
I
2
C
I/F
REF
PLL
Buzzer
Control
Power and RESET
SCLK
SDAT
A
MBIAS
REXT
MCLK
RESET
SS
EARV
DD
EARV
SS
PLLV
DD
PLLV
SS
DV
DD
DV
SS
AV
DD
AV
SS
V
PWRUPSEL
PCMOUT
EAR1OP
EAR1ON
EAR2O
BUZZCON
TWL1102
VOICE-BAND AUDIO PROCESSOR (VBAP
TM
)
SLVS264 NOVEMBER 1999
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
functional description
power-on/reset
The power for the various digital and analog circuits is separated to improve the noise performance of the
device. An external reset must be applied to the active low RESET terminal to guarantee reset upon power on.
After the initial power-on sequence the TWL1102 can be functionally powered up and down by writing to the
power control register through the I
2
C interface. There is a hardwired terminal selectable power up in default
mode option. The PWRUPSEL function allows the VBAP to power up in the default mode and allows use without
a microcontroller.
reference
A precision band gap reference voltage that is generated internally supplies all required voltage references to
operate the transmit and receive channels. The reference system also supplies bias voltage for use with an
electret microphone at terminal MBIAS. If MBIAS is turned off by selecting MICBIAS power down in the power
control register, the MBIAS terminal becomes a digital output signal for an external MIC_OFF function. An
external precision resistor is required for reference current setting at terminal REXT.
control interface
The I
2
C interface is a two-wire bidirectional serial interface that controls the VBAP by writing data to six control
registers: 1) power control, 2) mode control, 3) transmit PGA and sidetone control, 4) receive PGA gain and
volume control, 5) DTMF high tone, 6) DTMF low tone.
There are two power-up modes which may be selected at the PWRUPSEL terminal: 1) The PWRUPSEL state
(Vdd at terminal 20) causes the device to power up in the default mode when power is applied. In the default
mode the I
2
C interface is not required and the device may be used without an I
2
C interface. The programmable
functions will be fixed at the default modes. 2) The PWRUPSEL state (ground at terminal 20) causes the device
to go to a power-down state when power is applied. In this mode an I
2
C interface is required to power up the
device.
phase-locked loop
The internal digital filters and modulators require a 10.24-MHz clock that is generated by phase locking to the
2.048-MHz master clock input.
PCM interface
The PCM interface transmits and receives data at the PCMO and PCMI terminals respectively. The data is
transmitted or received at the PCMCLK speed once every PCMSYN cycle. The PCMCLK may be tied directly
to the 2.048-MHz master clock (MCLK). The PCMSYN can be driven by an external source or derived from the
master clock and used as an interrupt to the host controller.
microphone amplifiers
The microphone input is a switchable interface for two differential microphone inputs. The first stage is a low
noise differential amplifier that provides a gain of 23.5 dB. The second stage amplifier has a selectable gain of
0 dB or 12 dB.
analog modulator
The transmit channel modulator is a third-order sigma-delta design.
transmit filter and PGA
The transmit filter is a digital filter designed to meet CCITT G.714 requirements. The device operates in either
the 15-bit linear or 8-bit companded
-law or A-law mode that is selectable through the I
2
C interface. The
transmit PGA defaults to 0 dB.
TWL1102
VOICE-BAND AUDIO PROCESSOR (VBAP
TM
)
SLVS264 NOVEMBER 1999
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
functional description (continued)
sidetone
A portion of the transmitted audio is attenuated and fed back to the receive channel through the sidetone path.
The sidetone path defaults to 12 dB. The sidetone path can be enabled by writing to the power control register.
receive volume control
The receive volume control block acts as an attenuator with a range of 18 dB to 0 dB in 2 dB steps for control
of the receive channel volume. The receive volume control gain defaults to 0 dB.
receive filter and PGA
The receive filter is a digital filter that meets CCITT G.714 requirements with a high-pass filter that is selectable
through the I
2
C interface. The device operates in either the 15-bit linear or 8-bit
-law or A-law companded
mode, which is selectable through the I
2
C interface. The gain defaults to 1 dB representing a 3 dBm0 level
for a 32
load impedance and the corresponding digital full scale PCMI code. The gain may be set to 2 dB
for the respective 3 dBm0 level for a 16-
load impedance.
digital modulator and filter
The second-order digital modulator and filter convert the received digital PCM data to the analog output required
by the earphone interface.
earphone amplifiers
The analog signal can be routed to either of two earphone amplifiers, one with differential output (EAR1ON and
EAR1OP) and one with single-ended output (EAR2O). Clicks and pops are suppressed for EAR1 differential
output only.
tone generator
The tone generator provides generation of standard DTMF tones and single tone frequencies which are output
to the following: 1) The buzzer driver, as a pulse density modulation (PDM) signal. 2) The receive path
digital/analog converter (D/A), for outputting through the earphone. There are 255 possible single tones. The
tone integer value is determined by the following formula Round (Tone Freq (Hz)/7.8135 Hz). The value is
loaded into one of two 8-bit registers, the high tone register [04}or the low tone register {05}. The tone output
is 2 dB higher when applied to the high tone register {04}. When generating DTMF tones the high DTMF tone
must be applied to the high tone register, and the low frequency tone to the low tone register.
TWL1102
VOICE-BAND AUDIO PROCESSOR (VBAP
TM
)
SLVS264 NOVEMBER 1999
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
NAME
PFB
I/O
DESCRIPTION
AVDD
32
I
Analog positive power supply
AVSS
8
I
Analog negative power supply
BUZZCON
19
O
Buzzer output, a pulse-density modulated signal to apply to external buzzer driver
DVDD
13
I
Digital positive power supply
DVSS
14
I
Digital negative power supply
EAR1ON
27
O
Earphone 1 amplifier output ()
EAR1OP
29
O
Earphone 1 amplifier output (+)
EAR2O
31
O
Earphone 2 amplifier output
EARVDD
28
I
Analog positive power supply for the earphone amplifiers
EARVSS
30, 26
I
Analog negative power supply for the earphone amplifiers
MBIAS
1
O
Microphone bias supply output, no decoupling capacitors. If MBIAS is turned off the MBIAS terminal becomes a
digital output signal for an external MIC_OFF function. When used as a digital output, logic high indicates XMIT
disable, logic low XMIT inable.
MCLK
22
I
Master system clock input (2.048 MHz) (digital)
MIC1P
2
I
MIC1 input (+)
MIC1N
3
I
MIC1 input ()
MIC2P
4
I
MIC2 input (+)
MIC2N
5
I
MIC2 input ()
PCMI
15
I
Receive PCM input
PCMO
16
O
Transmit PCM output
PCMSYN
18
I
PCM frame sync
PCMCLK
17
I
PCM data clock
PLLVSS
24
I
PLL negative power supply
PLLVDD
25
I
PLL digital power supply
PWRUPSEL
20
I
Selects the power-up default mode
REXT
6
I/O
Internal reference current setting terminal use precision 100
-
k
resistor and no filtering capacitors
RESET
21
I
Active low reset
SCL
12
I
I2C-bus serial clock this input is used to synchronize the data transfer from and to the VBAP
SDA
11
I/O
I2C-bus serial address/data input/output this is a bidirectional terminal used to transfer register control
addresses and data into and out of the CODEC. It is an open
-
drain terminal and therefore requires a pull-up
resistor to VDD (typical 10 k
for 100 kHz)
VSS
23
I
Ground return for bandgap internal reference
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