PDS-1267B

Printed in U.S.A. July, 1995

FEATURES

LOW POWER: 50mW/channel

UNITY GAIN STABLE BANDWIDTH:
360MHz

FAST SETTLING TIME: 20ns to 0.01%

LOW INPUT BIAS CURRENT: 5

DIFFERENTIAL GAIN/PHASE ERROR:
0.01%/0.025

14-PIN DIP and SO-14 SURFACE MOUNT
PACKAGES AVAILABLE

DESCRIPTION

The OPA4650 is a quad, low power, wideband voltage
feedback operational amplifier. It features a high band-
width of 360MHz as well as a 12-bit settling time of
only 20ns. The low input bias current allows its use in
high speed integrator applications, while the wide
bandwidth and true differential input stage make it
suitable for use in a variety of active filter applica-
tions. Its low distortion gives exceptional performance
for telecommunications, medical imaging and video
applications.

The OPA4650 is internally compensated for unity-
gain stability. This amplifier has a fully symmetrical
differential input due to its "classical" operational
amplifier circuit architecture. Its unusual combination
of speed, accuracy and low power make it an outstand-
ing choice for many portable, multi-channel and other
high speed applications, where power is at a premium.

The OPA4650 is also available in single (OPA650)
and dual (OPA2650) configurations.

Wideband, Low Power, Quad Voltage Feedback

OPERATIONAL AMPLIFIER

OPA4650

Current

Mirror

Output

Stage

Inverting

Input

Non-Inverting

Input

Output

Simplified Schematic

1 of 4 Channels

APPLICATIONS

HIGH RESOLUTION VIDEO

MONITOR PREAMPLIFIER

CCD IMAGING AMPLIFIER

ULTRASOUND SIGNAL PROCESSING

ADC/DAC BUFFER AMPLIFIER

ACTIVE FILTERS

HIGH SPEED INTEGRATORS

DIFFERENTIAL AMPLIFIER

International Airport Industrial Park · Mailing Address: PO Box 11400, Tucson, AZ 85734 · Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 · Tel: (520) 746-1111 · Twx: 910-952-1111

Internet: http://www.burr-brown.com/ · FAXLine: (800) 548-6133 (US/Canada Only) · Cable: BBRCORP · Telex: 066-6491 · FAX: (520) 889-1510 · Immediate Product Info: (800) 548-6132

OPA4650

DEMO BOARD

AVAILABLE

SBOS044

OPA4650

SPECIFICATIONS

At T

= +25

C, V

5V, R

= 100

, and R

= 402

unless otherwise noted. R

= 25

for a gain of +1.

OPA4650P, U

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

FREQUENCY RESPONSE
Closed-Loop Bandwidth

(1)

G = +1

360

MHz

G = +2

120

MHz

G = +5

MHz

G = +10

MHz

Gain Bandwidth Product

160

MHz

Slew Rate

(2)

G = +1, 2V Step

240

Over Specified Temperature

220

Rise Time

0.2V Step

Fall Time

0.2V Step

Settling Time

0.01%

G = +1, 2V Step

0.1%

G = +1, 2V Step

10.3

G = +1, 2V Step

7.9

Spurious Free Dynamic Range

G = +1, f = 5.0 MHz, V

= 2Vp-p

= 100

dBc

= 402

dBc

Differential Gain

G = +2, NTSC, V

= 1.4Vp, R

= 150

0.01

Differential Phase

G = +2, NTSC, V

= 1.4Vp, R

= 150

0.025

Degrees

Bandwidth for 0.1dB Flatness

G = +2

MHz

Crosstalk

Input Referred, 5MHz, all hostile

Input Referred, 5MHz, Channel-to-Channel

OFFSET VOLTAGE
Input Offset Voltage

5.5

Average Drift

Power Supply Rejection (+V

)

| = 4.5V to 5.5V

)

INPUT BIAS CURRENT
Input Bias Current

= 0V

Over Temperature

Input Offset Current

= 0V

0.5

1.0

Over Temperature

3.0

INPUT NOISE
Input Voltage Noise

Noise Density, f = 100Hz

nV/

f = 10kHz

9.4

nV/

f = 1MHz

8.4

nV/

f = 1MHz to 100MHz

8.4

nV/

Integrated Noise, BW = 10Hz to 100MHz

Vp-p

Input Bias Current Noise

Current Noise Density, f = 0.1MHz to 100MHz

1.2

pA/

Noise Figure (NF)

= 10k

4.0

dBm

= 50

19.5

dBm

INPUT VOLTAGE RANGE
Common-Mode Input Range

2.8

Over Specified Temperature

2.2

Common-Mode Rejection

0.5V

INPUT IMPEDANCE
Differential

15 || 1

|| pF

Common-Mode

16 || 1

|| pF

OPEN-LOOP GAIN
Open-Loop Voltage Gain

2V, R

= 100

Over Specified Temperature

2V, R

= 100

OUTPUT
Voltage Output

Over Specified Temperature

No Load

2.2

3.0

= 250

2.2

2.5

= 100

2.0

2.3

Output Current, Sourcing

110

Over Temperature Range

Output Current, Sinking

Over Temperature Range

Short-Circuit Current

150

Output Resistance

0.1MHz, G = +1

0.08

POWER SUPPLY
Specified Operating Voltage

Operating Voltage Range

4.5

5.5

Quiescent Current

All Channels

Over Specified Temperature

TEMPERATURE RANGE
Specification: P, U

+85

Thermal Resistance,

C/W

NOTES: (1) Frequency response can be strongly influenced by PC board parasites. The OPA4650 is nominally compensated assuming 2pF parasitic load. The
demonstration board, DEM-OPA465xP, shows a low parasitic layout for this part. (2) Slew rate is rate of change from 10% to 90% of output voltage step.

OPA4650

ORDERING INFORMATION

PRODUCT

PACKAGE

TEMPERATURE RANGE

OPA4650U

SO-14 Surface Mount

C to +85

OPA4650P

14-Pin Plastic DIP

C to +85

PACKAGE INFORMATION

PACKAGE DRAWING

PRODUCT

PACKAGE

NUMBER

(1)

OPA4650U

SO-14 Surface Mount

235

OPA4650P

14-Pin Plastic DIP

010

NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.

Total Supply Voltage Across Device ................................................... 11V
Internal Power Dissipation ........................... See Thermal Considerations
Differential Input Voltage ..................................................................

2.7V

Common-Mode Input Voltage Range ..................................................

Storage Temperature Range: P, U, .............................. 40

C to +125

Lead Temperature (soldering, 10s) .............................................. +300

(soldering, SOIC 3s) ....................................... +260

Junction Temperature (T

) ............................................................ +175

ABSOLUTE MAXIMUM RATINGS

ELECTROSTATIC
DISCHARGE SENSITIVITY

Electrostatic discharge can cause damage ranging from per-
formance degradation to complete device failure. Burr-Brown
Corporation recommends that all integrated circuits be handled
and stored using appropriate ESD protection methods.

ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet published speci-
fications.

Top View

DIP/SO-14

PIN CONFIGURATION

Output 4

Input 4

+Input 4

+Input 3

Input 3

Output 3

Output 1

Input 1

+Input 1

+Input 2

Input 2

Output 2

OPA4650

DISCUSSION OF
PERFORMANCE

The OPA4650 is a quad low power, wideband voltage
feedback operational amplifier. Each channel is internally
compensated to provide unity gain stability. The OPA4650's
voltage feedback architecture features true differential and
fully symmetrical inputs. This minimizes offset errors, mak-
ing the OPA4650 well suited for implementing filter and
instrumentation designs. As a quad operational amplifier,
OPA4650 is an ideal choice for designs requiring multiple
channels where reduction of board space, power dissipation
and cost are critical. Its ac performance is optimized to
provide a gain bandwidth product of 160MHz and a fast
0.1% settling time of 10.3ns, which is an important consid-
eration in high speed data conversion applications. Along
with its excellent settling characteristics, the low dc input
offset of

1mV and drift of

C support high accuracy

requirements. In applications requiring a higher slew rate
and wider bandwidth, such as video and high bit rate digital
communications, consider the quad current feedback
OPA4658.

CIRCUIT LAYOUT AND BASIC OPERATION

Achieving optimum performance with a high frequency am-
plifier like the OPA4650 requires careful attention to layout
parasitics and selection of external components. Recommen-
dations for PC board layout and component selection include:

a) Minimize parasitic capacitance to any ac ground for all
of the signal I/O pins. Parasitic capacitance on the output
and inverting input pins can cause instability; on the non-
inverting input it can react with the source impedance to
cause unintentional bandlimiting. To reduce unwanted ca-
pacitance, a window around the signal I/O pins should be
opened in all of the ground and power planes. Otherwise,
ground and power planes should be unbroken elsewhere on
the board.

b) Minimize the distance (< 0.25") from the two power pins
to high frequency 0.1

F decoupling capacitors. At the pins,

the ground and power plane layout should not be in close
proximity to the signal I/O pins. Avoid narrow power and
ground traces to minimize inductance between the pins and
the decoupling capacitors. Larger (2.2

F to 6.8

F) decoupling

capacitors, effective at lower frequencies, should also be
used. These may be placed somewhat farther from the
device and may be shared among several devices in the same
area of the PC board.

c) Careful selection and placement of external compo-
nents will preserve the high frequency performance of the
OPA4650. Resistors should be a very low reactance type.
Surface mount resistors work best and allow a tighter overall
layout. Metal film or carbon composition axially-leaded
resistors can also provide good high frequency performance.
Again, keep their leads as short as possible. Never use
wirewound type resistors in a high frequency application.

Since the output pin and the inverting input pin are most
sensitive to parasitic capacitance, always position the feed-
back and series output resistor, if any, as close as possible to

the package pins. Surface mount feedback resistors directly
adjacent to the output and inverting input pins work well for
the quad pinout. Other network components, such as non-
inverting input termination resistors, should also be placed
close to the package.

Even with a low parasitic capacitance shunting the resistor,
excessively high resistor values can create significant time
constants and degrade performance. Good metal film or
surface mount resistors have approximately 0.2pF in shunt
with the resistor. For resistor values > 1.5k

, this adds a

pole and/or zero below 500MHz that can affect circuit
operation. Keep resistor values as low as possible consistent
with output loading considerations. The 402

feedback

used for the Typical Performance Plots is a good starting
point for design. Note that a 25

feedback resistor, rather

than a direct short, is suggested for a unity gain follower.
This effectively reduces the Q of what would otherwise be
a parasitic inductance (the feedback wire) into the parasitic
capacitance at the inverting input.

d) Connections to other wideband devices on the board
may be made with short direct traces or through on-board
transmission lines. For short connections, consider the trace
and the input to the next device as a lumped capacitive load.
Relatively wide traces (50 to 100 mils) should be used,
preferably with ground and power planes opened up around
them. Estimate the total capacitive load and set R

ISO

from

the plot of recommended R

ISO

vs capacitive load. Low

parasitic loads may not need an R

ISO

since the OPA4650 is

nominally compensated to operate with a 2pF parasitic load.

If a long trace is required and the 6dB signal loss intrinsic to
doubly terminated transmission lines is acceptable, imple-
ment a matched impedance transmission line using microstrip
or stripline techniques (consult an ECL design handbook for
microstrip and stripline layout techniques). A 50

environ-

ment is not necessary on board, and in fact a higher imped-
ance environment will improve distortion as shown in the
distortion vs load plot. With a characteristic impedance
defined based on board material and desired trace dimen-
sions, a matching series resistor into the trace from the
output of the amplifier is used as well as a terminating shunt
resistor at the input of the destination device. Remember
also that the terminating impedance will be the parallel
combination of the shunt resistor and the input impedance of
the destination device; the total effective impedance should
match the trace impedance. Multiple destination devices are
best handled as separate transmission lines, each with their
own series and shunt terminations.

If the 6dB attenuation loss of a doubly terminated line is
unacceptable, a long trace can be series-terminated at the
source end only. This will help isolate the line capacitance
from the op amp output, but will not preserve signal integrity
as well as a doubly terminated line. If the shunt impedance
at the destination end is finite, there will be some signal
attenuation due to the voltage divider formed by the series
and shunt impedances.

e) Socketing a high speed part like the OPA4650 is not
recommended. The additional lead length and pin-to-pin
capacitance introduced by the socket creates an extremely
troublesome parasitic network which can make it almost

OPA4650

impossible to achieve a smooth, stable response. Best results
are obtained by soldering the part onto the board. If socket-
ing for the DIP package is desired, high frequency flush
mount pins (e.g., McKenzie Technology #710C) can give
good results.

The OPA4650 is nominally specified for operation using

power supplies. A 10% tolerance on the supplies, or an ECL
5.2V for the negative supply, is within the maximum speci-
fied total supply voltage of 11V. Higher supply voltages can
break down internal junctions possibly leading to catastrophic
failure. Single supply operation is possible as long as com-
mon mode voltage constraints are observed. The common
mode input and output voltage specifications can be inter-
preted as a required headroom to the supply voltage. Observ-
ing this input and output headroom requirement will allow
non-standard or single supply operation. Figure 1 shows one
approach to single-supply operation.

OFFSET VOLTAGE ADJUSTMENT

One simple way to null the initial offset voltage while
retaining the low offset drift of the OPA4650 is shown in
Figure 2. The 20k

potentiometer and the 47k

series

resistor R

TRIM

create a small correction current which is

summed into the inverting node. The 0.1

F capacitor keeps

high-frequency power supply noise from coupling into the
signal path. Although the initial offset will be nulled to zero
with this technique, issues of temperature drift must also be
considered. The additional resistor R

is shown matched to

the parallel combination R

and R

(the R

TRIM

path is

assumed to be negligible in this calculation). This will
eliminate the first-order offset drift due to input bias current
leaving only the input offset current (I

) drift multiplied by

the feedback resistor R

ESD PROTECTION

ESD damage has been a well recognized source of degrada-
tion for MOSFET type circuits, but any semiconductor
device can be vulnerable to damage. This becomes more of
an issue for very high speed processes like that used for the

FIGURE 1. Single Supply Operation.

FIGURE 2. Offset Voltage Trim.

OPA4650. ESD damage can cause subtle changes in ampli-
fier input characteristics without necessarily destroying the
device. In precision operational amplifiers, this may cause a
noticeable degradation of offset voltage and drift. ESD
handling precautions are strongly recommended when han-
dling the OPA4650.

OUTPUT DRIVE CAPABILITY

The OPA4650 has been optimized to drive 75

and 100

resistive loads. The device can drive 1Vp-p into a 75

load. This high output drive capability makes the OPA4650
an ideal choice for a wide range of RF, IF and video
applications. In many cases, additional buffer amplifiers
are unnecessary.

Many demanding high speed applications, such as driving
Analog-to-Digital converters, require op amps with low
wideband output impedance. For example, low output imped-
ance is essential when driving the signal-dependent capaci-
tance at the input of a flash A/D converter. As shown in
Figure 3, the OPA4650 maintains very low closed-loop
output impedance over frequency. Closed-loop output imped-
ance increases with frequency since loop gain is decreasing.

SMALL-SIGNAL OUTPUT IMPEDANCE

vs FREQUENCY

Frequency (Hz)

100

0.1

0.01

10k

100k

100M

10M

Output Impedance (

)

G = +1

FIGURE 3. Small-Signal Output Impedance vs Frequency.

OPA4650

= R

|| R

(1)

TRIM

20k

or Ground

Output Trim Range +V

to V

NOTE: (1) R

is optional and can be used to cancel offset errors

due to input bias currents.

TRIM

47k

TRIM

0.1µF

402

1/4

OPA4650

402

OUT

= + A

= 1 +

OPA4650

FREQUENCY RESPONSE COMPENSATION

Each channel of the OPA4650 is internally compensated to
be stable at unity gain with a nominal 60

phase margin.

This lends itself well to wideband integrator and buffer
applications. Phase margin and frequency response flatness
will improve at higher gains. Recall that an inverting gain of
1 is equivalent to a gain of +2 for bandwidth purposes, i.e.,
noise gain = 2. The external compensation techniques devel-
oped for voltage feedback op amps can be applied to this
device. For example, in the non-inverting configuration,
placing a capacitor across the feedback resistor will reduce
the gain to +1 starting at f = (1/2

). Alternatively, in the

inverting configuration, the bandwidth may be limited with-
out modifying the inverting gain by placing a series RC
network to ground on the inverting node. This has the effect
of increasing the noise gain at high frequencies, thereby
limiting the bandwidth for the inverting input signal through
the gain-bandwidth product.

At higher gains, the gain-bandwidth of this voltage feedback
topology will limit bandwidth according to the open-loop
frequency response curve. For applications requiring a wider
bandwidth at higher gains, consider the quad current feed-
back model, OPA4658. In applications where a large feed-
back resistor is required (such as photodiode transimpedance
circuits), precautions must be taken to avoid gain peaking
due to the pole formed by the feedback resistor and the
summing junction capacitance. This pole can be compen-
sated by connecting a small capacitor in parallel with the
feedback resistor, creating a cancelling zero term. In other
high-gain applications, use of a three-resistor "T" connec-
tion will reduce the feedback network impedance which
reacts with the parasitic capacitance at the summing node.

PULSE SETTLING TIME

High speed amplifiers like the OPA4650 are capable of
extremely fast settling time with a pulse input. Excellent
frequency response flatness and phase linearity are required
to get the best settling times. As shown in the specifications
table, settling time for a

1V step at a gain of +1 for the

OPA4650 is extremely fast. The specification is defined as
the time required, after the input transition, for the output to
settle within a specified error band around its final value. For
a 2V step, 1% settling corresponds to an error band of

20mV, 0.1% to an error band of

2mV, and 0.01% to an

error band of

0.2mV. For the best settling times, particu-

larly into an ADC capacitive load, little or no peaking in the
frequency response can be allowed. Using the recommended
R

ISO

for capacitive loads will limit this peaking and reduce

the settling times. Fast, extremely fine scale settling (0.01%)
requires close attention to ground return currents in the
supply decoupling capacitors. For highest performance, con-
sider the OPA642 which isolates the output stage decoupling
from the rest of the amplifier.

THERMAL CONSIDERATIONS

The OPA4650 will not require heatsinking under most
operating conditions. Maximum desired junction tempera-
ture will limit the maximum allowed internal power dissipa-
tion as described below. In no case should the maximum
junction temperature be allowed to exceed +175

Operating junction temperature (T

) is given by T

. The total internal power dissipation (P

) is a com-

bination of the total quiescent power for all channels (P

)

and the sum of the powers dissipated in each of the output
stages (P

) to deliver load power. Quiescent power is

simply the specified no-load supply current times the total
supply voltage across the part. P

will depend on the

required output signal and load but would, for a grounded
resistive load, be at a maximum when the output is a fixed
dc voltage equal to 1/2 of either supply voltage (assuming
equal bipolar supplies). Under this condition, P

= V

(4·R

) where R

includes feedback network loading. Note

that it is the power dissipated in the output stage and not in
the load that determines internal power dissipation. As an
example, compute the maximum T

for an OPA4650U at

= +2, R

= 100

, R

= 402

5V, with all 4

outputs at |V

/2|, and the specified maximum T

= +85

= 10V·35mA + 4·(5

)/(4·(100

||804

)) = 631mW.

Maximum T

= +85

C + 0.641W·75

C/W = 133

DRIVING CAPACITIVE LOADS

The OPA4650's output stage has been optimized to drive
low resistive loads. Capacitive loads will decrease phase
margin which may result in high frequency oscillations or
peaking. Capacitive loads greater than 10pF should be iso-
lated by connecting a small resistance (15

to 30

) in series

with the output as shown in Figure 4. This is especially
important when driving the capacitive input of high-speed
A/D converters. Increasing the gain from +1 will improve
the capacitive load drive due to increased phase margin.

In general, capacitive loads should be minimized for opti-
mum high frequency performance. Coax lines can be driven
if the cable is properly terminated. The capacitance of coax
cable (29pF/ft for RG-58) will not load the amplifier when
the cable is source and load terminated in its characteristic
impedance.

FIGURE 4. Driving Capacitive Loads.

OPA4650

ISO

typically 5

to 20

)

OPA4650

DIFFERENTIAL GAIN AND PHASE

Differential Gain (DG) and Differential Phase (DP) are
among the more important specifications for video applica-
tions. The percentage change in closed-loop gain over a
specified change in output voltage level is defined as DG.
DP is defined as the change in degrees of the closed-loop
phase over the same output voltage change. For the OPA4650,
DG and DP are both specified at the NTSC color sub-carrier
frequency of 3.58MHz and measured using industry stan-
dard video test equipment.

DISTORTION

The OPA4650's harmonic distortion characteristics for a
100

load are shown in the Typical Performance Curves.

Distortion can be improved by increasing the load resistance
as illustrated in Figure 5. Remember to include the contribu-
tion of the feedback network when calculating the effective
load resistance seen by the amplifier.

FIGURE 6. Channel-to-Channel Isolation and All Hostile

Crosstalk.

0.1

100

300

Frequency (Hz)

Crosstalk (dB)

G = +1

All Hostile

Channel-to-Channel

FIGURE 5. Harmonic Distortion vs Load Resistance.

100

Harmonic Distortion (dBc)

Load Resistance (

)

= 5MHz, 2Vp-p)

CROSSTALK

Crosstalk is the undesired coupling of one channel's signal
into the output of the other channels. Crosstalk is a consid-
eration in all multichannel integrated circuits. The effect of
crosstalk is measured by driving one ("channel-to-channel")
or more ("all-hostile") channels and observing the output of
the undriven channel. The magnitude of this effect is ex-
pressed in the crosstalk specification as decibels of gain.
"Input referred" points to the fact that there is a direct
correlation between gain and crosstalk, therefore output
crosstalk increases proportionally at higher gains.

In quad devices, the effect of all-hostile crosstalk is observed
by driving all three channels concurrently and measuring the
output of the undriven fourth channel. The plots in Figure 6
illustrate both channel-to-channel and all-hostile crosstalk
for the OPA4650.

FIGURE 7. Noise Figure vs Source Resistance.

Source Resistance (

)

100

100k

10k

Noise Figure (dB)

NF = 10 LOG 1 +

+ (I

)

4KTR

SPICE MODELS AND EVALUATION BOARD

Computer simulation using SPICE is often useful when
analyzing the performance of analog circuits and systems.
This is particularly true for Video and RF amplifier circuits
where parasitic capacitance and inductance can have a
major effect on circuit performance. SPICE models and
evaluation PC boards are available for the OPA4650. Con-
tact the Burr-Brown Applications Department to receive a
SPICE diskette.

NOISE FIGURE

The voltage and current noise spectral density are shown in
the Typical Performance Curves. For RF and IF applica-
tions, however, Noise Figure (NF) is often the preferred
specification. This specification shows a degradation in
SNR through a device relative to the thermal noise of the
source impedance alone.

The NF for the OPA4650, using 1MHz spot noise numbers
and an unterminated non-inverting input, is shown in
Figure 7.

DEMONSTRATION BOARD

PACKAGE

PRODUCT

DEM-OPA465xP

8-Pin DIP

OPA4650P

DEM-OPA465xU

SO-8

oPA4650U

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI's terms
and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:

Products

Applications

Amplifiers

amplifier.ti.com

Audio

www.ti.com/audio

Data Converters

dataconverter.ti.com

Automotive

www.ti.com/automotive

DSP

dsp.ti.com

Broadband

www.ti.com/broadband

Interface

interface.ti.com

Digital Control

www.ti.com/digitalcontrol

Logic

logic.ti.com

Military

www.ti.com/military

Power Mgmt

power.ti.com

Optical Networking

www.ti.com/opticalnetwork

Microcontrollers

microcontroller.ti.com

Security

www.ti.com/security

Telephony

www.ti.com/telephony

Video & Imaging

www.ti.com/video

Wireless

www.ti.com/wireless

Mailing Address:

Texas Instruments

Post Office Box 655303 Dallas, Texas 75265

2003, Texas Instruments Incorporated

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: OPA4650U/2K5

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: OPA4650U/2K5