DAC8802
www.ti.com
FEATURES
DESCRIPTION
APPLICATIONS
14
DAC
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
A0
A1
EN
A
B
Decode
SDI
CS
CLK
DGND
RS
MSB
LDAC
R A
FB
V
A B
REF
R B
FB
I
A
OUT
A
A
GND
A
B
GND
I
B
OUT
Input
Register
Input
Register
DAC A
Register
DAC B
Register
R
R
Power-On
Reset
R
R
DAC A
DAC B
DAC8802
SBAS351A AUGUST 2005 REVISED DECEMBER 2005
Dual, Serial Input 14-Bit Multiplying Digital-to-Analog Converter
Relative Accuracy: 1 LSB Max
The DAC8802 is a dual, 14-bit, current-output
Differential Nonlinearity: 1 LSB Max
digital-to-analog converter (DAC) designed to operate
from a single +2.7 V to 5.5 V supply.
2-mA Full-Scale Current
20%,
with V
REF
=
10 V
The applied external reference input voltage V
REF
0.5
s Settling Time
determines the full-scale output current. An internal
feedback resistor (R
FB
) provides temperature tracking
Midscale or Zero-Scale Reset
for the full-scale output when combined with an
Separate 4Q Multiplying Reference Inputs
external I-to-V precision amplifier.
Reference Bandwidth: 10 MHz
A
doubled-buffered,
serial
data
interface
offers
Reference Dynamics: 105 dB THD
high-speed,
3-wire,
SPI
and
microcontroller
SPITM-Compatible 3-Wire Interface:
compatible inputs using serial data in (SDI), clock
50 MHz
(CLK),
and
a
chip-select
(CS).
A
common
Double Buffered Registers Enable
level-sensitive load DAC strobe (LDAC) input allows
simultaneous
update
of
all
DAC
outputs
from
Simultaneous Multichannel Change
previously loaded input registers. Additionally, an
Internal Power-On Reset
internal power-on reset forces the output voltage to
Industry-Standard Pin Configuration
zero at system turn-on. An MSB pin allows system
reset assertion (RS) to force all registers to zero code
when MSB = 0, or to half-scale code when MSB = 1.
Automatic Test Equipment
The DAC8802 is available in an TSSOP-16 package.
Instrumentation
Digitally Controlled Calibration
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI is a trademark of Motorola, Inc.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright 2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
www.ti.com
ABSOLUTE MAXIMUM RATINGS
(1)
DAC8802
SBAS351A AUGUST 2005 REVISED DECEMBER 2005
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION
(1)
MINIMUM
RELATIVE
DIFFERENTIAL
SPECIFIED
TRANSPORT
ACCURACY
NONLINEARITY
TEMPERATURE
PACKAGE-
PACKAGE
ORDERING
MEDIA,
PRODUCT
(LSB)
(LSB)
RANGE
LEAD
DESIGNATOR
NUMBER
QUANTITY
DAC8802IPW
Tubes, 90
DAC8802
1
1
40C to +85C
TSSOP-16
PW
DAC8802IPWR
Tape and Reel, 2500
(1)
For the most current specifications and package information, see the Package Option Addendum located at the end of this document, or
see the TI website at
www.ti.com
.
DAC8802
UNIT
V
DD
to GND
0.3 to +8
V
V
REF
to GND
18 to +18
V
Logic inputs and output to GND
0.3 to + 8
V
V(I
OUT
) to GND
0.3 to V
DD
+ 0.3
V
A
GND
X to DGND
0.3 to +0.3
V
Input current to any pin except supplies
50
mA
Package power dissipation
(T
J
max T
A
)/
JA
W
Thermal resistance,
JA
100
C/W
Maximum junction temperature (T
J
max)
150
C
Operating temperature range
40 to +85
C
Storage temperature range
65 to + 150
C
(1)
Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum conditions for extended periods may affect device reliability.
2
www.ti.com
ELECTRICAL CHARACTERISTICS
(1)
DAC8802
SBAS351A AUGUST 2005 REVISED DECEMBER 2005
V
DD
= 2.7 V to 5.5 V, I
OUT
X = Virtual GND, A
GND
X = 0 V, V
REF
A, B = 10 V, T
A
= full operating temperature range, unless
otherwise noted.
DAC8802
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT
STATIC PERFORMANCE
(2)
Resolution
14
Bits
Relative accuracy
INL
1
LSB
Differential nonlinearity
DNL
1
LSB
Data = 0000h, T
A
= 25
C
10
nA
Output leakage current
I
OUT
X
Data = 0000h, T
A
= T
A
max
20
nA
Full-scale gain error
G
FSE
Data = 3FFFh
0.75
4
mV
Full-scale tempco
(3)
TCV
FS
1
ppm/
C
Feedback resistor
R
FB
X
V
DD
= 5 V
5
k
REFERENCE INPUT
V
REF
X Range
V
REF
X
15
15
V
Input resistance
R
REF
X
4
5
6
k
Input resistance match
R
REF
X
Channel-to-channel
1
%
Input capacitance
(3)
C
REF
X
5
pF
ANALOG OUTPUT
Output current
I
OUT
X
Data = 3FFFh
1.6
2.5
mA
Output capacitance
(3)
C
OUT
X
Code-dependent
50
pF
LOGIC INPUTS AND OUTPUT
V
DD
= +2.7 V
0.6
V
Input low voltage
V
IL
V
DD
= +5 V
0.8
V
V
DD
= +2.7 V
2.1
V
Input high voltage
V
IH
V
DD
= +5 V
2.4
V
Input leakage current
I
IL
1
A
Input capacitance
(3)
C
IL
10
pF
Logic output low voltage
V
OL
I
OL
= 1.6 mA
0.4
V
Logic output high voltage
V
OH
I
OH
= 100
A
4
V
INTERFACE TIMING
(3)
,
(4)
Clock width high
t
CH
25
ns
Clock width low
t
CL
25
ns
CS to Clock setup
t
CSS
0
ns
Clock to CS hold
t
CSH
25
ns
Clock to SDO prop delay
t
PD
2
20
ns
Load DAC pulsewidth
t
LDAC
25
ns
Data setup
t
DS
20
ns
Data hold
t
DH
20
ns
Load setup
t
LDS
5
ns
Load hold
t
LDH
25
ns
(1)
Specifications subject to change without notice.
(2)
All static performance tests (except I
OUT
) are performed in a closed-loop system using an external precision OPA277 I-to-V converter
amplifier. The DAC8802 R
FB
terminal is tied to the amplifier output. Typical values represent average readings measured at +25
C.
(3)
These parameters are specified by design and not subject to production testing.
(4)
All input control signals are specified with t
R
= t
F
= 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
3
www.ti.com
PARAMETER MEASUREMENT INFORMATION
SDI
CLK
CS
LDAC
t
CSS
t
ds
t
dh
t
ch
t
cl
t
csh
Input REG. LD
t
lds
t
LDAC
t
LDH
A1
A0
D13 D12 D11 D10
D1
D0
DAC8802
SBAS351A AUGUST 2005 REVISED DECEMBER 2005
ELECTRICAL CHARACTERISTICS (continued)
V
DD
= 2.7 V to 5.5 V, I
OUT
X = Virtual GND, A
GND
X = 0 V, V
REF
A, B = 10 V, T
A
= full operating temperature range, unless
otherwise noted.
DAC8802
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CHARACTERISTICS
Power supply range
V
DD RANGE
2.7
5.5
V
Logic inputs = 0 V, V
DD
= +4.5 V to +5.5 V
2
5
A
Positive supply current
I
DD
Logic inputs = 0 V, V
DD
= +2.7 V to +3.6 V
1
2.5
A
Power dissipation
P
DISS
Logic inputs = 0 V
0.0275
mW
Power supply sensitivity
P
SS
V
DD
=
5%
0.006
%
AC CHARACTERISTICS
(5)
To
0.1% of full-scale,
s
0.3
Data = 0000h to 3FFFh to 0000h
Output voltage settling time
t
s
To
0.006% of full-scale,
s
0.5
Data = 0000h to 3FFFh to 0000h
Reference multiplying BW
BW 3 dB
V
REF
X = 100 mV
RMS
, Data = 3FFFh, C
FB
= 3 pF
10
MHz
DAC glitch impulse
Q
V
REF
X = 10 V, Data = 1FFFh to 2000h to 1FFFh
5
nV/s
Feedthrough error
V
OUT
X/V
REF
X
Data = 0000h, V
REF
X = 100 mV
RMS
, f = 100 kHz
70
dB
Data = 0000h, V
REF
B = 100 mV
RMS
,
dB
Crosstalk error
V
OUT
A/V
REF
B
100
Adjacent channel, f = 100 kHz
Digital feedthrough
Q
CS = 1 and f
CLK
= 1 MHz
1
nV/s
Total harmonic distortion
THD
V
REF
= 5 V
PP
, Data = 3FFFh, f = 1 kHz
105
dB
Output spot noise voltage
e
n
f = 1 kHz, BW = 1 Hz
12
nV/
Hz
(5)
All ac characteristic tests are performed in a closed-loop system using an THS4011 I-to-V converter amplifier.
Figure 1. DAC8802 Timing Diagram
4
www.ti.com
PIN CONFIGURATIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
15
DGND
DAC8802
(TOP VIEW)
A
GND
A
I
OUT
A
V
REF
A
R
FB
A
R
FB
B
V
REF
B
I
OUT
B
A
GND
B
LDAC
MSB
RS
V
DD
CS
CLK
SDI
DAC8802
SBAS351A AUGUST 2005 REVISED DECEMBER 2005
PIN DESCRIPTION
PIN
NAME
DESCRIPTION
1
R
FB
A
Establish voltage output for DAC A by connecting to external amplifier output.
DAC A Reference voltage input terminal. Establishes DAC A full-scale output voltage.
2
V
REF
A
Can be tied to V
DD
pin.
3
I
OUT
A
DAC A Current output.
4
A
GND
A
DAC A Analog ground.
5
A
GND
B
DAC B Analog ground.
6
I
OUT
B
DAC B Current output.
DAC B Reference voltage input terminal. Establishes DAC B full-scale output voltage.
7
V
REF
B
Can be tied to V
DD
pin.
8
R
FB
B
Establish voltage output for DAC B by connecting to external amplifier output.
9
SDI
Serial data input; data loads directly into the shift register.
Reset pin; active low input. Input registers and DAC registers are set to all 0s or midscale.
10
RS
Register data = 0x0000 when MSB = 0. Register data = 0x2000 when MSB = 1 for
DAC8802.
Chip-select; active low input. Disables shift register loading when high. Transfers serial
11
CS
register data to input register when CS/LDAC goes high. Does not affect LDAC operation.
12
DGND
Digital ground.
13
V
DD
Positive power-supply input. Specified range of operation is 2.7 V to 5.5 V.
MSB bit sets output to either 0 or midscale during a RESET pulse (RS) or at system
14
MSB
power-on. Output equals zero scale when MSB = 0 and midscale when MSB = 1. MSB
pin can be permanently tied to ground or V
DD
.
Load DAC register strobe; level sensitive active low. Transfers all input register data to
15
LDAC
the DAC registers. Asynchronous active low input. See
Table 2
for operation.
16
CLK
Clock input. Positive edge clocks data into shift register.
5
www.ti.com
TYPICAL CHARACTERISTICS: V
DD
= +5 V
Channel A
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0
2048
4096
6144
8192 10240 12288 14336 16383
INL (LSB)
Code
T
A
= +25C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0
2048
4096
6144
8192 10240 12288 14336 16383
DNL (LSB)
Code
T
A
= +25C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0
2048
4096
6144
8192 10240 12288 14336 16383
INL (LSB)
Code
T
A
= 40C
-
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0
2048
4096
6144
8192 10240 12288 14336 16383
DNL (LSB)
Code
T
A
= 40
-
C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0
2048
4096
6144
8192 10240 12288 14336 16383
INL (LSB)
Code
T
A
= +85C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0
2048
4096
6144
8192 10240 12288 14336 16383
DNL (LSB)
Code
T
A
= +85C
DAC8802
SBAS351A AUGUST 2005 REVISED DECEMBER 2005
At T
A
= +25C, +V
DD
= +5 V, unless otherwise noted.
LINEARITY ERROR
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
vs DIGITAL INPUT CODE
Figure 2.
Figure 3.
LINEARITY ERROR
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
vs DIGITAL INPUT CODE
Figure 4.
Figure 5.
LINEARITY ERROR
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
vs DIGITAL INPUT CODE
Figure 6.
Figure 7.
6
www.ti.com
Channel B
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0
2048
4096
6144
8192 10240 12288 14336 16383
INL (LSB)
Code
T
A
= +25C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0
2048
4096
6144
8192 10240 12288 14336 16383
DNL (LSB)
Code
T
A
= +25C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0
2048
4096
6144
8192 10240 12288 14336 16383
INL (LSB)
Code
T
A
= 40
-
C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0
2048
4096
6144
8192 10240 12288 14336 16383
DNL (LSB)
Code
T
A
= 40
-
C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0
2048
4096
6144
8192 10240 12288 14336 16383
INL (LSB)
Code
T
A
= +85C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0
2048
4096
6144
8192 10240 12288 14336 16383
DNL (LSB)
Code
T
A
= +85C
DAC8802
SBAS351A AUGUST 2005 REVISED DECEMBER 2005
TYPICAL CHARACTERISTICS: V
DD
= +5 V (continued)
At T
A
= +25C, +V
DD
= +5 V, unless otherwise noted.
LINEARITY ERROR
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
vs DIGITAL INPUT CODE
Figure 8.
Figure 9.
LINEARITY ERROR
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
vs DIGITAL INPUT CODE
Figure 10.
Figure 11.
LINEARITY ERROR
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
vs DIGITAL INPUT CODE
Figure 12.
Figure 13.
7
www.ti.com
180
160
140
120
100
80
60
40
20
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Supply Current, I
D
D
(
m
A)
Logic Input Voltage (V)
V
= +5.0V
DD
V
= +2.7V
DD
6
0
-6
-12
-18
-24
-30
-36
-42
-48
-54
-60
-66
-72
-78
-84
-90
-96
-102
-108
-114
10
100
1k
10k
100k
1M
10M
100M
Attenuation (dB)
Bandwidth (Hz)
Time (0.2 s/div)
m
Output V
oltage (50mV/div)
LDAC Pulse
Code: 1FFFh to 2000h
Time (0.1 s/div)
m
Output V
oltage (5V/div)
Trigger Pulse
Voltage Output Settling
DAC8802
SBAS351A AUGUST 2005 REVISED DECEMBER 2005
TYPICAL CHARACTERISTICS: V
DD
= +5 V (continued)
At T
A
= +25C, +V
DD
= +5 V, unless otherwise noted.
SUPPLY CURRENT
REFERENCE MULTIPLYING BANDWIDTH
vs LOGIC INPUT VOLTAGE
Figure 14.
Figure 15.
DAC GLITCH
DAC SETTLING TIME
Figure 16.
Figure 17.
8
www.ti.com
TYPICAL CHARACTERISTICS: V
DD
= +2.7 V
Channel A
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0
2048
4096
6144
8192 10240 12288 14336 16383
INL (LSB)
Code
T
A
= +25C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0
2048
4096
6144
8192 10240 12288 14336 16383
DNL (LSB)
Code
T
A
= +25C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0
2048
4096
6144
8192 10240 12288 14336 16383
INL (LSB)
Code
T
A
= 40
-
C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0
2048
4096
6144
8192 10240 12288 14336 16383
DNL (LSB)
Code
T
A
= 40
-
C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0
2048
4096
6144
8192 10240 12288 14336 16383
INL (LSB)
Code
T
A
= +85C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0
2048
4096
6144
8192 10240 12288 14336 16383
DNL (LSB)
Code
T
A
= +85C
DAC8802
SBAS351A AUGUST 2005 REVISED DECEMBER 2005
At T
A
= +25C, +V
DD
= +2.7 V, unless otherwise noted.
LINEARITY ERROR
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
vs DIGITAL INPUT CODE
Figure 18.
Figure 19.
LINEARITY ERROR
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
vs DIGITAL INPUT CODE
Figure 20.
Figure 21.
LINEARITY ERROR
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
vs DIGITAL INPUT CODE
Figure 22.
Figure 23.
9
www.ti.com
Channel B
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0
2048
4096
6144
8192 10240 12288 14336 16383
INL (LSB)
Code
T
A
= +25C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0
2048
4096
6144
8192 10240 12288 14336 16383
DNL (LSB)
Code
T
A
= +25C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0
2048
4096
6144
8192 10240 12288 14336 16383
INL (LSB)
Code
T
A
= 40
-
C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0
2048
4096
6144
8192 10240 12288 14336 16383
DNL (LSB)
Code
T
A
= 40
-
C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0
2048
4096
6144
8192 10240 12288 14336 16383
INL (LSB)
Code
T
A
= +85C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0
2048
4096
6144
8192 10240 12288 14336 16383
DNL (LSB)
Code
T
A
= +85C
DAC8802
SBAS351A AUGUST 2005 REVISED DECEMBER 2005
TYPICAL CHARACTERISTICS: V
DD
= +2.7 V (continued)
At T
A
= +25C, +V
DD
= +2.7 V, unless otherwise noted.
LINEARITY ERROR
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
vs DIGITAL INPUT CODE
Figure 24.
Figure 25.
LINEARITY ERROR
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
vs DIGITAL INPUT CODE
Figure 26.
Figure 27.
LINEARITY ERROR
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
vs DIGITAL INPUT CODE
Figure 28.
Figure 29.
10
www.ti.com
THEORY OF OPERATION
CIRCUIT OPERATION
Digital-to-Analog Converters
R
R
R
2R
2R
2R
R
5 k
S2
S1
DGND
V
REF
X
V
DD
R
FB
X
I
OUT
X
A
GND
X
Digital interface onnections are omitted for clarity.
Switches S1 and S2 are closed; V
must be powered.
DD
c
V
OUT
+ *
V
REF
D
16384
(1)
DAC8802
SBAS351A AUGUST 2005 REVISED DECEMBER 2005
The DAC8802 contains two 14-bit, current-output, digital-to-analog converters (DACs). Each DAC has its own
independent multiplying reference input. The DAC8802 uses a 3-wire, SPI-compatible serial data interface, with a
configurable asynchronous RS pin for half-scale (MSB = 1) or zero-scale (MSB = 0) preset. In addition, an LDAC
strobe enables two-channel simultaneous updates for hardware-synchronized output voltage changes.
The DAC8802 contains two current-steering R-2R ladder DACs.
Figure 30
shows a typical equivalent DAC. Each
DAC contains a matching feedback resistor for use with an external I-to-V converter amplifier. The R
FB
X pin is
connected to the output of the external amplifier. The I
OUT
X terminal is connected to the inverting input of the
external amplifier. The A
GND
X pin should be Kelvin-connected to the load point in the circuit requiring the full
14-bit accuracy.
Figure 30. Typical Equivalent DAC Channel
The DAC is designed to operate with both negative or positive reference voltages. The V
DD
power pin is only
used by the logic to drive the DAC switches on and off. Note that a matching switch is used in series with the
internal 5 k
feedback resistor. If users are attempting to measure the value of R
FB
, power must be applied to
V
DD
in order to achieve continuity. The DAC output voltage is determined by V
REF
and the digital data (D)
according to
Equation 1
:
Note that the output polarity is opposite of the V
REF
polarity for dc reference voltages.
The DAC is also designed to accommodate ac reference input signals. The DAC8802 accommodates input
reference voltages in the range of -15 V to +15 V. The reference voltage inputs exhibit a constant nominal input
resistance of 5 k
, 20%. On the other hand, DAC outputs I
OUT
A and B are code-dependent and produce
various output resistances and capacitances.
The choice of external amplifier should take into account the variation in impedance generated by the DAC8802
on the amplifiers' inverting input node. The feedback resistance, in parallel with the DAC ladder resistance,
dominates output voltage noise. For multiplying mode applications, an external feedback compensation capacitor
(C
FB
) may be needed to provide a critically damped output response for step changes in reference input
voltages.
11
www.ti.com
I
OUT
X
+
+
DGND
V
DD
R
FB
X
A
GND
X
Analog
Power
Supply
Load
15 V
2R
5 V
R
15 V
V
EE
V
CC
V
OUT
A1
DGND
V
REF
X
R
R
R
2R
2R
2R
R
5 k
S2
S1
Digital interface onnections are omitted for clarity.
Switches S1 and S2 are closed; V
must be powered.
DD
c
14
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
A0
A1
A
B
DAC
Decode
Input
Register
Input
Register
DAC A
Register
DAC B
Register
R
R
R
R
DAC A
DAC B
Set
MSB
Set
MSB
Power-On
Reset
DGND
MSB
LDAC
RS
V
DD
V
A B
REF
R A
FB
I
A
OUT
A
A
GND
A
B
GND
I
B
OUT
R B
FB
CS
CLK
SDI
EN
DAC8802
SBAS351A AUGUST 2005 REVISED DECEMBER 2005
Figure 15
shows the gain vs frequency performance at various attenuation settings using a 3 pF external
feedback capacitor connected across the I
OUT
X and R
FB
X terminals. In order to maintain good analog
performance, power supply bypassing of 0.01 F, in parallel with 1 F, is recommended. Under these conditions,
a clean power supply with low ripple voltage capability should be used. Switching power supplies is usually not
suitable for this application due to the higher ripple voltage and P
SS
frequency-dependent characteristics. It is
best to derive the DAC8802 5-V supply from the system analog supply voltages (do not use the digital 5-V
supply); see
Figure 31
.
Figure 31. Recommended Kelvin-Sensed Hookup
Figure 32. System Level Digital Interfacing
12
www.ti.com
SERIAL DATA INTERFACE
DAC8802
SBAS351A AUGUST 2005 REVISED DECEMBER 2005
The DAC8802 uses a 3-wire (CS, SDI, CLK) SPI-compatible serial data interface. Serial data of the DAC8802 is
clocked into the serial input register in an 16-bit data-word format. MSB bits are loaded first.
Table 1
defines the
16 data-word bits for the DAC8802.
Data is placed on the SDI pin, and clocked into the register on the positive clock edge of CLK subject to the data
setup and data hold time requirements specified in the Interface Timing specifications of the
Electrical
Characteristics
. Data can only be clocked in while the CS chip select pin is active low. For the DAC8802, only
the last 16 bits clocked into the serial register are interrogated when the CS pin returns to the logic high state.
Since most microcontrollers output serial data in 8-bit bytes, two right-justified data bytes can be written to the
DAC8802. Keeping the CS line low between the first and second byte transfer will result in a successful serial
register update.
Once the data is properly aligned in the shift register, the positive edge of the CS initiates the transfer of new
data to the target DAC register, determined by the decoding of address bits A1and A0. For the DAC8802,
Table 1
,
Table 2
,
Table 3
, and
Figure 1
define the characteristics of the software serial interface.
Table 1. Serial Input Register Data Format, Data Loaded MSB First
(1)
Bit
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0 (LSB)
Data
A1
A0
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
(1)
Only the last 16 bits of data clocked into the serial register (address + data) are inspected when the CS line positive edge returns to
logic high. At this point an internally-generated load strobe transfers the serial register data contents (bits D13-D0) to the decoded
DAC-input-register address determined by bits A1 and A0. Any extra bits clocked into the DAC8802 shift register are ignored; only the
last 16 bits clocked in are used. If double-buffered data is not needed, the LDAC pin can be tied logic low to disable the DAC registers.
Table 2. Control Logic Truth Table
(1)
CS
CLK
LDAC
RS
MSB
SERIAL SHIFT REGISTER
INPUT REGISTER
DAC REGISTER
H
X
H
H
X
No effect
Latched
Latched
L
L
H
H
X
No effect
Latched
Latched
L
+
H
H
X
Shift register data advanced one bit
Latched
Latched
L
H
H
H
X
No effect
Latched
Latched
+
L
H
H
X
No effect
Selected DAC updated with current SR contents
Latched
H
X
L
H
X
No effect
Latched
Transparent
H
X
H
H
X
No effect
Latched
Latched
H
X
+
H
X
No effect
Latched
Latched
H
X
H
L
0
No effect
Latched data = 0000h
Latched data = 0000h
H
X
H
L
H
No effect
Latched data = 2000h
Latched data = 2000h
(1)
+ = Positive logic transition; X = Do not care
Table 3. Address Decode
A1
A0
DAC DECODE
0
0
None
0
1
DAC A
1
0
DAC B
1
1
DAC A and DAC B
13
www.ti.com
A
B
Address
Decoder
Shift Register
EN
To Input Register
CS
CLK
SDI
POWER ON RESET
ESD Protection Circuits
V
DD
250 W
DGND
DIGITAL
INPUTS
PCB LAYOUT
DAC8802
SBAS351A AUGUST 2005 REVISED DECEMBER 2005
Figure 33
shows the equivalent logic interface for the key digital control pins for the DAC8802.
Figure 33. DAC8802 Equivalent Logic Interface
Two additional pins RS and MSB provide hardware control over the preset function and DAC register loading. If
these functions are not needed, the RS pin can be tied to logic high. The asynchronous input RS pin forces all
input and DAC registers to either the zero-code state (MSB = 0), or the half-scale state (MSB = 1).
When the V
DD
power supply is turned on, an internal reset strobe forces all the Input and DAC registers to the
zero-code state or half-scale, depending on the MSB pin voltage. The V
DD
power supply should have a smooth
positive ramp without drooping, in order to have consistent results, especially in the region of V
DD
= 1.5 V to
2.3 V. The DAC register data stays at the zero or half-scale setting until a valid serial register data load takes
place.
All logic-input pins contain back-biased ESD protection zener diodes connected to ground (DGND) and V
DD
, as
shown in
Figure 34
.
Figure 34. Equivalent ESD Protection Circuits
The DAC8802 is a high-accuracy DAC that can have its performance compromised by grounding and printed
circuit board (PCB) lead trace resistance. The 14-bit DAC8802 with a 10-V full-scale range has an LSB value of
610 V. The ladder and associated reference and analog ground currents for a given channel can be as high as
2 mA. With this 2 mA current level, a series wiring and connector resistance of only 305 m
will cause 1 LSB of
voltage drop. The preferred PCB layout for the DAC8802 is to have all A
GND
X pins connected directly to an
analog ground plane at the unit. The noninverting input of each channel I/V converter should also either connect
directly to the analog ground plane or have an individual sense trace back to the A
GND
X pin connection. The
feedback resistor trace to the I/V converter should also be kept short and low resistance to prevent IR drops from
contributing to gain error. This attention to wiring ensures the optimal performance of the DAC8802.
14
www.ti.com
APPLICATION INFORMATION
V
OUT
+
D
8192
*
1
V
REF
(2)
10 V
V
REF
10 k
10 k
5 k
V
DD
V
REF
X
R
FB
X
I
OUT
X
OPA277
A
GND
X
One Channel
DAC8802
V
OUT
Digital interface connections omitted for clarity.
- 10 V <
OUT
< +10V
V
OPA277
Cross-Reference
DAC8802
SBAS351A AUGUST 2005 REVISED DECEMBER 2005
The DAC8802, a 2-quadrant multiplying DAC, can be used to generate a unipolar output. The polarity of the
full-scale output I
OUT
is the inverse of the input reference voltage at V
REF
.
Some applications require full 4-quadrant multiplying capabilities or bipolar output swing, as shown in
Figure 35
.
An additional external op amp (A2) is added as a summing amp. In this circuit, the first and second amps (A1
and A2) provide a gain of 2X that widens the output span to 20 V. A 4-quadrant multiplying circuit is implemented
by using a 10-V offset of the reference voltage to bias A2. According to the following circuit transfer equation
(
Equation 2
), input data (D) from code 0 to full scale produces output voltages of V
OUT
= -10 V to V
OUT
= 10 V.
Figure 35. Four-Quadrant Multiplying Application Circuit
The DAC8802 has an industry-standard pinout.
Table 4
provides the cross-reference information.
Table 4. Cross-Reference
SPECIFIED
INL
DNL
TEMPERATURE
PACKAGE
PACKAGE
CROSS-REFERENCE
PRODUCT
(LSB)
(LSB)
RANGE
DESCRIPTION
OPTION
PART NUMBER
16-Lead Thin Shrink
DAC8802IPW
1
1
-40C to +85C
TSSOP-16
AD5555CRU
Small-Outline Package
15
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
DAC8802IPWR
PREVIEW
TSSOP
PW
16
2500
TBD
Call TI
Call TI
DAC8802IPWT
PREVIEW
TSSOP
PW
16
250
TBD
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco
Plan
-
The
planned
eco-friendly
classification:
Pb-Free
(RoHS)
or
Green
(RoHS
&
no
Sb/Br)
-
please
check
http://www.ti.com/productcontent
for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com
14-Nov-2005
Addendum-Page 1
MECHANICAL DATA
MTSS001C JANUARY 1995 REVISED FEBRUARY 1999
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65
M
0,10
0,10
0,25
0,50
0,75
0,15 NOM
Gage Plane
28
9,80
9,60
24
7,90
7,70
20
16
6,60
6,40
4040064/F 01/97
0,30
6,60
6,20
8
0,19
4,30
4,50
7
0,15
14
A
1
1,20 MAX
14
5,10
4,90
8
3,10
2,90
A MAX
A MIN
DIM
PINS **
0,05
4,90
5,10
Seating Plane
0
8
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI's terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
Telephony
www.ti.com/telephony
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright
2005, Texas Instruments Incorporated
PDF 
ZIP