Actual Size
7 mm x 7 mm
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FEATURES
DESCRIPTION
APPLICATIONS
Interface
Logic
Power-On
Reset
Input
Register
Input
Register
DAC
Register
16 Bit
DAC
16 Bit
DAC
Buffer
Buffer
DAC
Register
Power-Down
Logic
D15
D0
CS
LDAC
RST
IOV
DD
A0
V
FBA
V
FBB
V
OUTA
V
OUTB
V
OUTC
V
OUTD
V
FBC
V
FBD
IOGND V
DD
GND
V
REFA
+
V
REFA
-
V
REFB
+
V
REFB
-
DAC8544
PD
V
REFC
+ V
REFC
-
V
REFD
+
V
REFD
-
A1
R/W
DAC8544
SLAS420 MAY 2004
QUAD, 16-BIT, RAIL-TO-RAIL VOLTAGE OUTPUT, PARALLEL INTERFACE,
DIGITAL-TO-ANALOG CONVERTER
Single Supply: +2.7 V to +5.5 V
The DAC8544 is a low-power, quad-channel, 16-bit,
Micropower Operation: 950 A @ 5 V
voltage output DAC. Its on-chip precision output
amplifier allows rail-to-rail voltage
swing
to
be
Rail-To-Rail Voltage Output
achieved at the output. The DAC8544 is 16-bit
Ultralow Crosstalk: 110 dB
monotonic and offers exceptional absolute accuracy
Settling Time: 10 s To
0.003% FSR
with ultralow crosstalk. The DAC8544 uses a 16-bit
parallel interface and features additional power-down
16-Bit Monotonic
function pins as well as hardware-enabled, synchron-
Offset Error:
0.3 mV
ous DAC updating and reset capability.
Gain Error:
1 mV
The DAC8544 requires an external reference voltage
Total Error:
3 mV
to set the output range of the DAC. The device
Per-Channel V
REF+
, V
REF
, V
FB
Pins
incorporates a power-on-reset circuit that ensures
Logic Compatible: +1.8 V to +5.5 V
that the DAC outputs power up at zero volt and
Readback Capability
remains there until a valid write takes place. In
addition, the DAC8544 contains a power-down fea-
Double Buffered Inputs
ture, accessed via PD pin, that reduces the current
Simultaneous or Sequential Update
consumption of the device to 400 nA at 5 V. The
Schmitt-Triggered Digital Inputs
power consumption is typically under 5 mW at
Hardware Reset
V
DD
= 5 V.
48-Lead TQFP Package
The DAC8544 is available in a 48-lead TQFP pack-
age with an operating temperature range of 40
C to
+105
C.
Process Control
Data Acquisition Systems
Closed-Loop Servo Control
PC Peripherals
Optical Networking
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright 2004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
DAC8544
SLAS420 MAY 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE OPTIONS
PACKAGE DRAWING
PACKAGE
ORDERING
TRANSPORT
PRODUCT
PACKAGE
TA
NUMBER
MARKING
NUMBER
MEDIA
DAC8544IPFB
Tray
DAC8544
48 - TQFP
PFB
-40
C to 105
C
DAC8544I
DAC8544IPFBR
Tape and Reel
over operating free-air temperature range (unless otherwise noted)
(1)
V
DD
to GND
0.3 V to 6 V
IOV
DD
to IOGND
0.3 V to 6 V
Digital input voltage to IOGND
0.3 V to IOV
DD
+ 0.3 V
V
OUT
to GND
0.3 V to V
DD
+ 0.3 V
Operating temperature range
40
C to 105
C
Storage temperature range, Tstg
65
C to 150
C
Junction temperature, TJ max
+150
C
(1)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
V
DD
= + 2.7 V to + 5.5 V; R
L
= 2 k
to GND; C
L
= 200 pF to GND; all specifications 40
C to +105
C unless otherwise noted
DAC8544
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE
(1)
Resolution
16
Bits
Relative Accuracy
0.025
.098
%FSR
Differential Nonlinearity
16-Bit Monotonic
0.25
1
LSB
Measured at code 485, 25
C
0.3
3
Zero-Code Offset Error
mV
Measured at code 485, -40
C to 105
C
1.0
5.0
Zero-Code Error Drift
All zeroes loaded to DAC register
-20
V/
C
DC Crosstalk
0.1
LSB
AC Crosstalk
1-kHz sine wave
-110
dB
Measured at code 64714, 25
C
1.0
3.0
Gain Error
mV
Measured at code 64714, -40
C to
2.0
5.0
105
C
Gain Error Drift
-5
ppm of
FSR/
C
Measured at code 64714, 25
C
0.5
3.0
Full-Scale Error
mV
Measured at code 64714, -40
C to
1.0
5.0
105
C
OUTPUT CHARACTERISTICS
(2)
Output Voltage Range
0
V
REF
V
Output Voltage Settling Time
R
L
= 2 k
; C
L
<200 pF
8
10
s
R
L
= 2 k
; C
L
<500 pF
12
Slew Rate
R
L
= 2 k
; C
L
<200 pF
1
V/
s
(1)
Linearity calculated using a reduced code range of 485 to 64714. Output unloaded.
(2)
Assured by design and characterization, not production tested.
2
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DAC8544
SLAS420 MAY 2004
ELECTRICAL CHARACTERISTICS (continued)
V
DD
= + 2.7 V to + 5.5 V; R
L
= 2 k
to GND; C
L
= 200 pF to GND; all specifications 40
C to +105
C unless otherwise noted
DAC8544
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
R
L
=
470
pF
Capacitive Load Stability
R
L
= 2 k
1000
pF
Digital-to-Analog Glitch Impulse
20
nV-s
Digital Feedthrough
0.5
nV-s
DC Output Impedance
1
V
DD
= +5 V
50
Short-Circuit Current
mA
V
DD
= +3 V
20
Coming out of power-down mode,
2.5
V
DD
= +5 V
Power-Up Time
s
Coming out of power-down mode,
5
V
DD
= +3 V
REFERENCE INPUT
V
REF+
Input Range
0
V
DD
V
V
REF
Input Range
0.1
0.0
V
DD
/2
V
Reference Input Impedance
140
k
LOGIC INPUTS
Input Current
1
A
V
IN
L, Input Low Voltage
IOV
DD
= +1.8 V +5.5 V
0.3 x IOV
DD
V
V
IN
H, Input High Voltage
IOV
DD
= +1.8 V +5.5 V
0.7 x IOV
DD
V
Pin Capacitance
3
pF
POWER REQUIREMENTS
V
DD
2.7
5.5
V
IOV
DD
1.8
5.5
V
I
DD
(Normal Mode)
DAC active and excluding load current
V
DD
= +3.6 V to +5.5 V
VI
H
= IOV
DD
and VI
L
= IOGND
1.0
1.6
mA
V
DD
= +2.7 V to +3.6 V
VI
H
= IOV
DD
and VI
L
= IOGND
0.96
1.52
I
DD
(All Power-Down Modes)
V
DD
= +3.6 V to +5.5 V
VI
H
= IOV
DD
and VI
L
= IOGND
0.2
1
A
V
DD
= +2.7 V to +3.6 V
VI
H
= IOV
DD
and VI
L
= IOGND
0.05
1
POWER EFFICIENCY
I
OUT
/I
DD
I
LOAD
= 2 mA, V
DD
= +5 V
93
%
3
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TIMING CHARACTERISTICS
t
W
1
t
W
5
t
W
2
t
su
1
t
h
1
t
su
3
t
h
3
t
h
4
t
su
2
t
h
2
t
d
1
t
su
4
t
h
2
t
w
4
t
W
3
t
s
0.003% of FSR Error Bands
Data Out Valid
Data In Valid
CS
R/W
Data I/O
DB0-DB15
LDAC
V
(OUT)
DAC8544
SLAS420 MAY 2004
IOV
DD
= 1.8 V to 5.5 V; V
DD
= 2.7 V to 5.5 V; R
L
= 2 k
to GND; C
L
= 200 pF to GND; all specifications 40
C to 85
C (unless
otherwise noted)
MIN
TYP
MAX
UNIT
t
w
1
Pulse width: CS low for valid write
20
ns
t
su
1
Setup time: R/W low before CS falling
0
ns
t
su
2
Setup time: data in valid before CS falling
0
ns
t
h
1
Hold time: R/W low after CS rising
10
ns
t
h
2
Hold time: data in valid after CS rising
15
ns
t
w
2
Pulse width: CS low for valid read
40
ns
t
su
3
Setup time: R/W high before CS falling
30
ns
t
d
1
Delay time: data out valid after CS falling
60
80
ns
t
h
3
Hold time: R/W high after CS rising
10
ns
t
h
4
Hold time: data out valid after CS rising
5
20
ns
t
su
4
Setup time: LDAC rising after CS falling
10
ns
t
d
2
Delay time: CS low after LDAC rising
50
ns
t
w
3
Pulse width: LDAC low
40
ns
t
w
4
Pulse width: LDAC high
40
ns
t
w
5
Pulse width: CS high
80
ns
t
w
6
Pulse width: RST low
40
ns
t
w
7
Pulse width: RST high
40
ns
t
S
VOUT Settling time (settling time for a full-scale code change)
10
s
Data Read/Write Timing
4
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t
W
6
t
W
7
t
s
V
OUT
RST
+FS
DEVICE INFORMATION
1
2
3
4
5
6
7
8
9
10
11
12
13 14
15 16 17 18
19 20
21 22 23
24
36
35
34
33
32
31
30
29
28
27
26
25
37
38
39
40
41
42
43
44
45
46
47
48
VREFD-
VREFD+
VFBD
VOUTD
VDD
GND
PD
RST
GND
LDAC
R/W
CS
A0
A1
IOGND
IOVDD
D0
D1
D2
D3
D4
D5
D6
D7
VDD
GND
IOGND
IOVDD
D15
D14
D13
D12
D11
D10
D9
D8
VREF
A-
VREF
A+
VFBA
VOUT
A
VREFB-
VREFB+
VFBB
VOUTB
VREFC-
VREFC+
VOUTC
VFBC
DAC8544
DAC8544
SLAS420 MAY 2004
Reset Timing
Pin Configuration
5
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DAC8544
SLAS420 MAY 2004
DEVICE INFORMATION (continued)
TERMINAL FUNCTIONS
DAC8544
Pin
Mnemonic
Function
1
VDD
Analog supply voltage, +2.7 V to +5.5 V
2
GND
Analog supply ground
3
IOGND
Digital supply ground
4
IOVDD
Digital supply +1.8 V to +5.5 V
5
D15
Digital input, MSB
6
D14
Digital input
7
D13
Digital input
8
D12
Digital input
9
D11
Digital input
10
D10
Digital input
11
D9
Digital input
12
D8
Digital input
13
D7
Digital input
14
D6
Digital input
15
D5
Digital input
16
D4
Digital input
17
D3
Digital input
18
D2
Digital input
19
D1
Digital input
20
D0
Digital input, LSB
21
IOVDD
Digital supply +1.8 V to +5.5 V
22
IOGND
Digital supply ground
23
A1
Address pin for selecting between DAC channels
24
A0
Address pin for selecting between DAC channels
25
CS
Active-low chip select. Used with R/W_ to write/read data to/from device
26
R/W
Read/Write select used to write data to input register or read data from DAC register
27
LDAC
Load DACs, rising edge triggered loads all DAC registers
28
GND
Analog ground
29
RST
Asynchronously resets contents of all DAC Registers to zero-scale, but does not affect input register
30
PD
Active-low power-down pin puts entire device into power-down mode with DAC outputs in 3-state condition
31
GND
Analog supply ground
32
VDD
Analog supply voltage, +2.7 V to +5.5 V
33
VOUTD
Analog output voltage from DAC-D
34
VFBD
Analog output sense for DAC-D
35
VREFD+
High reference voltage input for DAC-D
36
VREFD
Low reference voltage input for DAC-D, normally VREFD = GND
37
VOUTC
Analog output voltage from DAC-C
38
VFBC
Analog output sense for DAC-C
39
VREFC+
High reference voltage input for DAC-C
40
VREFC
Low reference voltage input for DAC-C, normally VREFC = GND
41
VOUTB
Analog output voltage from DAC-B
42
VFBB
Analog output sense for DAC-B
43
VREFB+
High reference voltage input for DAC-B
44
VREFB
Low reference voltage input for DAC-B, normally VREFB = GND
45
VOUTA
Analog output voltage from DAC-A
6
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DAC8544
SLAS420 MAY 2004
DEVICE INFORMATION (continued)
TERMINAL FUNCTIONS (continued)
DAC8544
Pin
Mnemonic
Function
46
VFBA
Analog output sense for DAC-A
47
VREFA+
High reference voltage input for DAC-A
48
VREFA
Low reference voltage input for DAC-A, normally VREFA = GND
7
www.ti.com
TYPICAL CHARACTERISTICS
-0.005
-0.004
-0.003
-0.002
-0.001
0
0.001
0.002
0.003
0.004
0.005
0
10000
20000
30000
40000
50000
60000
Digital Input Code
T
otal Unadjusted Error - V
-3
-2
-1
0
1
2
3
-40
-20
0
20
40
60
80
100
Gain
Full-Scale
Zero-Scale
V
DD
= 5.5 V
T
A
- Free-Air Temperature -
C
Error - mV
-5
0
5
10
15
20
25
30
35
40
-1
-0.4
0
0.4
1
T
A
= 25
C
Percentage - %
Offset Error - mV
-0.2
-0.6
-0.8
0.2
0.6
0.8
-3
-2
-1
0
1
2
3
-40
-20
0
20
40
60
80
100
Gain
Full-Scale
Zero-Scale
V
DD
= 3.6 V
T
A
- Free-Air Temperature -
C
Error - mV
0
5
10
15
20
25
-1
-0.8
-0.6 -0.4
-0.2
0
0.2
0.4
0.6
0.8
1
T
A
= 25
C
Percentage - %
Gain Error - mV
0
5
10
15
20
25
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
T
A
= 25
C
Percentage - %
Full Scale Error - mV
DAC8544
SLAS420 MAY 2004
This condition applies to all typical characteristics: V
REF+
= V
DD
, V
REF
= GND, T
A
= 25
C (unless otherwise noted)
TOTAL UNADJUSTED ERROR
ERROR
vs
vs
DIGITAL INPUT CODE
TEMPERATURE
Figure 1.
Figure 2.
ERROR
vs
OFFSET ERROR DISTRIBUTION
TEMPERATURE
(ACROSS MANY SAMPLES)
Figure 3.
Figure 4.
GAIN ERROR DISTRIBUTION
FULL SCALE ERROR DISTRIBUTION
(ACROSS MANY SAMPLES)
(ACROSS MANY SAMPLES)
Figure 5.
Figure 6.
8
www.ti.com
-64
-48
-32
-16
0
16
32
48
64
0
10000
20000
30000
40000
50000
60000
Digital Input Code
Linearity Error - LSB
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
0
10000
20000
30000
40000
50000
60000
DLE - LSB
Digital Input Code
-64
-48
-32
-16
0
16
32
48
64
-40
0
40
80
MAX Error
MIN Error
T
A
- Free-Air Temperature -
5
C
Linearity Error - LSB
110
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
-40
0
40
80
Differential Linearity Error - LSB
T
A
- Free-Air Temperature -
C
Max
Max
Min
110
0
0.025
0.05
0.075
0.1
0.125
0.15
0
1
2
3
4
5
V
REF
= V
DD
-10 mV
DAC Loaded With 0000
- Output V
oltage - V
V
O
I
SINK
- Sink Current - mA
V
DD
= 5 V
V
DD
= 2.7 V
4.8
4.85
4.9
4.95
0
1
2
3
4
5
5
V
DD
= 5 V
V
REF
= V
DD
-10 mV
DAC Loaded With FFFFH
- Output V
oltage - V
V
O
I
SOURCE
- Source Current - mA
DAC8544
SLAS420 MAY 2004
TYPICAL CHARACTERISTICS (continued)
This condition applies to all typical characteristics: V
REF+
= V
DD
, V
REF
= GND, T
A
= 25
C (unless otherwise noted)
LINEARITY ERROR
DIFFERENTIAL LINEARITY ERROR
vs
vs
DIGITAL INPUT CODE
DIGITAL INPUT CODE
Figure 7.
Figure 8.
LINEARITY ERROR
DIFFERENTIAL LINEARITY ERROR
vs
vs
TEMPERATURE
TEMPERATURE
Figure 9.
Figure 10.
SINK CURRENT AT NEGATIVE RAIL
SOURCE CURRENT AT POSITIVE RAIL
Figure 11.
Figure 12.
9
www.ti.com
2.4
2.5
2.6
2.7
2.8
0
1
2
3
4
5
V
DD
= 2.7 V
V
REF
= V
DD
-10 mV
DAC Loaded With FFFFH
- Output V
oltage - V
V
O
I
SOURCE
- Source Current - mA
0
10000
20000
30000
40000
50000
60000
Digital Input Code
I
REF
Included
0
100
200
300
400
500
600
700
800
DDI
Supply Current -
-
A
V
DD
= 5 V
V
DD
= 2.7 V
-40
-20
0
20
40
60
80
100
V
DD
= 5.5 V
V
DD
= 2.7 V
I
REF
Included, Midcode
DDI
Supply Current -
-
A
T
A
- Free-Air Temperature -
5
C
0
200
400
600
800
1000
1200
1400
1600
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
DDI
Supply Current -
-
A
- Supply Voltage - V
V
DD
0
200
400
600
800
1000
1200
1400
1600
I
REF
= V
DD
, I
DD
Measured at Power-Up,
Reference Current Included, No Load
I
DD
- Supply Current -
m
A
Device Counts
V
DD
= 2.7 V
V
DD
= 5.5 V
I
REF
Included
0
500
1000
1500
2000
2500
3000
3500
4000
600
700
800
900
1000
1100
1200
1300
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0
1
2
3
4
5
I
DD
= 5.5 V
V
IH
= 2.7 V
DDI
Supply Current -
-
A
Logic Input Voltage - V
DAC8544
SLAS420 MAY 2004
TYPICAL CHARACTERISTICS (continued)
This condition applies to all typical characteristics: V
REF+
= V
DD
, V
REF
= GND, T
A
= 25
C (unless otherwise noted)
SUPPLY CURRENT
vs
SOURCE CURRENT AT POSITIVE RAIL
DIGITAL INPUT CODE
Figure 13.
Figure 14.
SUPPLY CURRENT
SUPPLY CURRENT
vs
vs
TEMPERATURE
SUPPLY VOLTAGE
Figure 15.
Figure 16.
SUPPLY CURRENT
vs
LOGIC INPUT VOLTAGE
HISTOGRAM OF CURRENT CONSUMPTION
Figure 17.
Figure 18.
10
www.ti.com
-0.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
- Output V
oltage - V
V
O
t - Time - 4
m
s/div
2.42
2.44
2.46
2.48
2.5
2.52
2.54
0
5
10
15
20
25
30
35
t - Time -
m
s
- Output V
oltage - V
V
O
Code Change From 7FFFh to 8000h to 7FFFh
0
1
2
3
4
5
- Output V
oltage - V
V
O
t - Time - 12
m
s/div
Large Signal
V
DD
= V
REF
= 5 V,
Output Loaded With
2 k
and 200 pF to
GND.
0
0.5
1
1.5
2
2.5
3
- Output V
oltage - V
V
O
t - Time - 12
m
s/div
Large Signal
V
DD
= V
REF
= 5 V,
Output Loaded With
2 k
and 200 pF to
GND.
0.00
0.50
1.00
1.50
t - Time - 12
m
s/div
V
O
U
T
- Output V
oltage - V
V
DD
= V
REF
= 2.7 V
Output Loaded With
2 k
and 200 pF to
GND
3.5
3
3.5
2.5
2
1.5
1
1.5
0.5
0
V
DD
= V
REF
= 2.7 V
Output Loaded With
2 k
and 200 pF to
GND
- Output V
oltage - V
V
O
t - Time - 12
m
s/div
Large Signal
DAC8544
SLAS420 MAY 2004
TYPICAL CHARACTERISTICS (continued)
This condition applies to all typical characteristics: V
REF+
= V
DD
, V
REF
= GND, T
A
= 25
C (unless otherwise noted)
EXITING POWER-DOWN MODE
OUTPUT GLITCH (MID-SCALE)
Figure 19.
Figure 20.
FULL-SCALE SETTLING TIME
HALF-SCALE SETTLING TIME
Figure 21.
Figure 22.
FULL-SCALE SETTLING TIME
HALF-SCALE SETTLING TIME
Figure 23.
Figure 24.
11
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98
96
94
92
90
88
86
84
0
500
1 k
1.5 k
2 k
2.5 k
3 k
3.5 k
4 k
4.5 k
Output Frequency - Hz
SNR - Signal-to-Noise Ratio - dB
V
DD
= V
REF
-1 dB FSR Digital Input, F
S
= 52 K
sps
Measurement Bandwidth = 20 kHz
V
DD
= 5 V
V
DD
= 2.7 V
0
500
1 k
1.5 k
2 k
2.5 k
3 k
3.5 k
4 k
Output Frequency - Hz
THD - T
otal Harmonic Distortion - dB
V
DD
= V
REF
= 5 V
F
S
= 52 K
sps
-1 dB FSR Digital Input
Measurement Bandwidth = 20 kHz
THD
3rd Harmonic
2nd Harmonic
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
- Output V
oltage - 5 mV/div
V
O
t - Time - 2
m
s/div
Small-Signal Settling
Trigger Signal
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
500
1 k
1.5 k
2 k
2.5 k
3 k
3.5 k
4 k
Output Frequency - Hz
THD - T
otal Harmonic Distortion - dB
V
DD
= V
REF
= 2.7 V
F
S
= 52 K
sps,
-1 dB FSR Digital Input
Measurement Bandwidth = 20 kHz
THD
3rd Harmonic
2nd Harmonic
- Output V
oltage - 5 mV/div
V
O
t - Time - 2
m
s/div
Small-Signal Settling
Trigger Signal
DAC8544
SLAS420 MAY 2004
TYPICAL CHARACTERISTICS (continued)
This condition applies to all typical characteristics: V
REF+
= V
DD
, V
REF
= GND, T
A
= 25
C (unless otherwise noted)
SIGNAL-TO-NOISE
TOTAL HARMONIC DISTORTION
vs
vs
OUTPUT FREQUENCY
OUTPUT FREQUENCY
Figure 25.
Figure 26.
TOTAL HARMONIC DISTORTION
vs
FULL-SCALE SETTLING TIME
OUTPUT FREQUENCY
(SMALL-SIGNAL POSITIVE-GOING STEP)
Figure 27.
Figure 28.
FULL-SCALE SETTLING TIME
(SMALL-SIGNAL NEGATIVE-GOING STEP)
Figure 29.
12
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THEORY OF OPERATION
D/A SECTION
_
+
Resistor String
V
REF +
V
REF -
DAC Register
V
OUT
External Reference ()
External Reference (+)
V
FB
R
R
V
OUT
+ 2 V
REF*
) (
V
REF
)
*
V
REF
*
)
D
65536
(1)
RESISTOR STRING
V
REF+
To Output
Amplifier
R
R
R
R
V
REF
OUTPUT AMPLIFIER
DAC8544
SLAS420 MAY 2004
The architecture of the DAC8544 consists of four string DACs followed by an output buffer amplifier. Figure 30
shows a block diagram of the DAC architecture.
Figure 30. DAC8544 Architecture
The input coding to the DAC8544 is unsigned binary, which gives the ideal output voltage as:
where
D = decimal equivalent of the binary code that is loaded to the DAC register; it can range from 0 to 65535.
The resistor string section is shown in Figure 31. It is simply a divide-by-two resistor, followed by a string of
resistors, each of value R. The code loaded into the DAC register determines at which node on the string the
voltage is tapped off, to be fed into the output amplifier, by closing one of the switches connecting the string to
the amplifier. Because it is a string of resistors, it is assured monotonic.
Figure 31. Resistor String
The output buffer is capable of generating rail-to-rail voltages at its output, which gives an output range of 0 V to
V
REF+
. It is capable of driving a load of 2 k
in parallel with 1000 pF to GND. The source and sink capabilities of
the output amplifier can be seen in the typical curves. The slew rate is 1 V/
s with a full-scale settling time of 10
s with the output loaded. The feedback and gain setting resistors of the amplifier are in the order of 50 k
. Their
absolute value can be off significantly, but they are matched to within 0.1%.
The inverting input of the output amplifier is brought out to the V
FB
pin, through the feedback resistor. This allows
for better accuracy in critical applications by tying the V
FB
point and the amplifier output together at the load.
Other signal conditioning circuitry may also be connected between these points for specific applications including
current sourcing.
13
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PARALLEL INTERFACE
LDAC FUNCTION
UPDATE SEQUENCE
READBACK
RST
DAC8544
SLAS420 MAY 2004
THEORY OF OPERATION (continued)
The DAC8544 provides a 16-bit parallel interface and supports both writing to and reading from the DAC input
register. (See the timing characteristics section for detailed information for a typical write or read operation.) In
addition to the data, CS, and R/W inputs, the DAC8544's interface also provides power down, LDAC, and
reset/reset-select control. Table 1 and Table 2 show the control signal actions and data format, respectively.
These features are discussed in more detail in the remaining sections.
Table 1. DAC8544 CONTROL SIGNAL SUMMARY
CS
R/W
LDAC
RST
PD
ACTION
H
X
X
X
X
Device data I/O is disabled on the bus.
(1)
L
X
H,L
H
Write initiated, present input data to the bus.
H
X
H,L
H
Read initiated, data from input register is presented to data bus.
X
X
H,L
H
Input data is latched when writing to the device.
X
X
H,L
H
Data from input register is transferred to DAC register and V
OUT
is updated.
DAC register and V
OUT
reset to min-scale. (If DAC is powered down during
X
X
X
H
reset, DAC register resets and V
OUT
settles to min-scale on power up.)
X
X
X
X
L
Power down device, V
OUT
impedance equals high impedance
(1)
Only disables 16-bit data I/O interface. Other control lines remain active.
The DAC8544 is designed using a double-buffered architecture. A write operation (rising edge of CS while R/W
is low) transfers data from the data input pins into the input register. The data is held in the input register until a
rising-edge is detected on the LDAC input. This rising-edge signal transfers the data from the input register to the
DAC register. On issuance of the rising LDAC edge, the output of the DAC8544 begins settling to the newly
written data value presented to the DAC register. Data in the input register is not changed when an LDAC rising
edge occurs.
For regular operation, R/W pin should be kept low while CS is kept high. Then, the 16-bit digital data should be
applied to the input bus. The channel selection should then be asserted by setting the A0 and A1 pins. The
falling edge of CS enables the device. Once the data is stable and the channels are selected, the first rising edge
of the CS signal latches the data to the input register of the selected channel. After the data is latched to the
input register, the rising edge of the LDAC signal updates all four channels simultaneously with existing data from
their corresponding input register.
For read-back operation, the user first releases the 16-bit bus, while CS is high. Then, the DAC channel should
be selected using the A0 and A1 pins. R/W pin is then brought high to enable read-back operation. Following the
falling edge of CS, the data from the selected channel (buffer data) is output on the bus.
The RST input controls the reset of the DAC register and, consequently, the DAC output, but does not change
the input register. The reset operation is edge-triggered by a low-to-high transition on the RST pin. Once a rising
edge on RST is detected, the DAC output settles to the zero code. Application of a valid reset signal to the DAC
does not overwrite existing data in the input register.
14
www.ti.com
POWER-ON RESET
POWER-DOWN MODES
VOLTAGE REFERENCE INPUTS
V
OUT
+
2
V
REF
*
) (
V
REF
)
*
V
REF
*
)
D
65536
(2)
ANALOG AND DIGITAL SUPPLIES
EXTERNAL REFERENCE VOLTAGE
DAC8544
SLAS420 MAY 2004
The DAC8544 contains a power-on reset circuit that controls the output voltage after power up. On power up, the
DAC register (and DAC output) is set to zero (plus a small offset error produced by the output buffer). It remains
at zero until a valid write sequence is made to the DAC, changing the DAC register data. This is useful in
applications where it is important to know the state of the output of the DAC after power up. All digital inputs
must be logic low until the digital and analog supplies are applied. Logic high voltages, applied to the input pins
when power is not applied to IOV
DD
and V
DD
, may power the device through the ESD input structures causing
undesired operation.
The DAC8544 uses two modes of operation. These modes are programmable via pin PD.
Table 2 shows how the state of the pin correspond to the mode of operation of the DAC8544.
Table 2. Modes of Operation for the DAC8544
PD
OPERATING MODE
High
Normal operation
Low
Power down, high impedance
When pin PD is high, the device works normally with its typical power consumption of 950 A at V
DD
= 5 V.
However, when PD pin is in low state, the device is in power-down mode, the supply current falls to 200 nA at
V
DD
= 5 V (50 nA at V
DD
= 3 V), and the output is open circuit (high impedance).
All analog circuitry is shut down when a power-down mode is activated. However, the contents of the DAC
register are unaffected when in power-down mode. This allows the DAC output voltage to return to the previous
level when power up resumes. The delay time required to exit power-down is typically 2.5 s for V
DD
= 5 V, and 5
s for V
DD
= 3 V. (See the typical characteristics section for additional information.)
Two voltage inputs provide the reference set points for the DAC architecture. These are V
REF+
and V
REF
. For
typical rail-to-rail operation, V
REF+
should be equivalent to V
DD
and V
REF
tied to GND. The output voltage is given
by:
The use of the V
REF
input allows minor adjustments to be made to the offset of the DAC output by applying a
small voltage to the V
REF
input. A low output impedance source is needed, so that the accuracy of the DAC over
its operating range is not affected.
The analog supply (V
DD
) powers the output buffer and DAC while the digital supply (IOV
DD
) powers the digital
interface. V
DD
can operate from 2.7 V to 5.5 V while IOV
DD
can independently function from 1.8 V to 5.5 V. IOV
DD
determines the interface logic level. See the device specification table for details.
To take advantage of the absolute accuracy of DAC8544, a high-performance reference voltage generator must
be used. DAC8544 has a typical absolute accuracy error of 2 millivolts, and a typical voltage drift of 3 ppm/
C.
This level of performance requires an accurate external reference voltage generator with good temperature drift
characteristics. Accuracy, drift, supply voltage, power consumption, and cost are important factors in choosing a
voltage reference. TI's REF02 is recommended. TI's REF3140 and REF3040 are small and low-cost
alternatives.
15
www.ti.com
FEEDBACK PINS
HOST PROCESSOR INTERFACING
DAC8544 to MSP430 Microcontroller
V
DD
0.1
m
F
10
m
F
V
DD
IOV
DD
0.1
m
F
10
m
F
IOV
DD
VFB
V
OUT
V
REF
+
0.1
m
F
1 to 10
m
F
V
REF
GND
IOGND
V
REF
-
A0
A1
PD
LDAC
RST
R/W
CS
16 Bits
8 Bits
8 Bits
D[15:0]
(Other Pins Omitted for Clarity)
P4[0:7]
P5[0:7]
P2:0
P2:1
P2:2
P2:4
P2:5
P2:6
P2:7
MSP430F149
DAC8544
V
OUT
DAC8544 to TMS320C5402 DSP
DAC8544
SLAS420 MAY 2004
For regular operation, the feedback pins (V
FBA
through V
FBD
) must be tied to their corresponding output pins
(V
OUTA
through V
OUTD
) at the load. For higher current applications sensitive to gain error, the feedback pin should
be routed to the target node, to sense the node voltage accurately (DAC8544 gain error is typically low, around 1
mV).
Figure 32 shows a typical parallel interface connection between the DAC8544 and a MSP430 microcontroller.
The setup for the interface shown uses ports 4 and 5 of the MSP430 to send or receive the 16-bit data while bits
0-7 of port 2 provides the control signals for the DAC. When data is to be transmitted to the DAC8544, the data
is made available to the DAC via P4 and P5, and P2.1 is taken low. The MSP430 then toggles P2.0 from
high-to-low and back to high, transferring the 16-bit data to the DAC. This data is loaded into the DAC register by
applying a rising edge to P2.4. The remaining five I/O signals of P2 shown in the figure control the reset,
power-down, and data format functions of the DAC. Depending on the specific requirements of a given
application, these pins may be tied to IOGND or IOV
DD
, enabling the desired mode of operation.
Figure 32. DAC8544 to MSP430 Microcontroller
Figure 33 shows the connections between the DAC8544 and the TMS320C5402 digital signal processor. Data is
provided via the parallel data bus of the DSP while the DAC CS control input is derived from the decoded I/O
strobe signal. The IOSTRB in addition to the R/W and XF(I/O) signals control the data transmission to and from
the DAC as well as the LDAC control. With additional decoding, multiple DAC8544s can be connected to the
same parallel data bus of the DSP.
16
www.ti.com
V
DD
0.1
m
F
10
m
F
V
DD
IOV
DD
0.1
m
F
10
m
F
IOV
DD
VFB
V
OUT
V
REF
+
0.1
m
F
1 to 10
m
F
V
REF
GND
IOGND
V
REF
-
LDAC
CS
16 Bits
D[15:0]
(Other Pins Omitted for Clarity)
D[15:0]
A[23:0]
IOSTRB
R/W
XF(I/O)
TMS320C5402
DAC8544
V
OUT
Address
Decoder
EN
R/W
BIPOLAR OPERATION USING THE DAC8544
V
OUT
VFB
V
REF
+
V
REF
-
R1 = 10 k
5 V
- 5 V
R2 = 10 k
5 V
DAC8544
0.1
F
10
F
5 V
(Other Pins Omitted for Clarity)
OPA703
-
+
V
OUT
+
10
D
65536
*
5V
(3)
DAC8544
SLAS420 MAY 2004
Figure 33. DAC8544 to TMS320 DSP
The DAC8544 has been designed for single-supply operation but a bipolar output range is also possible using
the circuit shown in Figure 34. The circuit allows the DAC8544 to achieve an analog output range of
5 V.
Rail-to-rail operation at the amplifier output is achievable using an OPA703 as the output amplifier.
Figure 34. Bipolar Operation With the DAC8544
With V
REF+
= 5 V, R1 = R2 = 10 k
:
17
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LAYOUT
DAC8544
SLAS420 MAY 2004
A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power
supplies. The following measures should be taken to assure optimum performance of the DAC8544. The
DAC8544 offers dual-supply operation, as it can often be used in close proximity with digital logic,
microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and
the higher the switching speed, the more important it becomes to separate the analog and digital ground and
supply planes at the DAC.
Because the DAC8544 has both analog and digital ground pins, return currents can be better controlled and
have less effect on the DAC output error. Ideally, GND would be connected directly to an analog ground plane
and GND to the digital ground plane. The analog ground plane would be separate from the ground connection for
the digital components until they were connected at the power entry point of the system. The power applied to
V
DD
and V
REF+
(this also applies to V
REF
if not tied to GND) should be well-regulated and low-noise. Switching
power supplies and dc/dc converters often have high-frequency glitches or spikes riding on the output voltage. In
addition, digital components can create similar high-frequency spikes as their internal logic switches states. This
noise can easily couple into the DAC output voltage through various paths between the power connections and
analog output.
As with the GND connection, V
DD
should be connected to a 5-V power supply plane or trace that is separate
from the connection for digital logic until they are connected at the power entry point. In addition, the 1-F to
10-F and 0.1-F bypass capacitors are strongly recommended. In some situations, additional bypassing may be
required, such as a 100-F electrolytic capacitor or even a Pi filter made up of inductors and capacitors--all
designed to essentially lowpass-filter the V
DD
supply, removing the high-frequency noise.
18
MECHANICAL DATA
MTQF019A JANUARY 1995 REVISED JANUARY 1998
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PFB (S-PQFP-G48)
PLASTIC QUAD FLATPACK
4073176 / B 10/96
Gage Plane
0,13 NOM
0,25
0,45
0,75
Seating Plane
0,05 MIN
0,17
0,27
24
25
13
12
SQ
36
37
7,20
6,80
48
1
5,50 TYP
SQ
8,80
9,20
1,05
0,95
1,20 MAX
0,08
0,50
M
0,08
0
7
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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