1
DAC8043
DAC8043
International Airport Industrial Park Mailing Address: PO Box 11400, Tucson, AZ 85734 Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 Tel: (520) 746-1111 Twx: 910-952-1111
Internet: http://www.burr-brown.com/ FAXLine: (800) 548-6133 (US/Canada Only) Cable: BBRCORP Telex: 066-6491 FAX: (520) 889-1510 Immediate Product Info: (800) 548-6132
DAC8043
FEATURES
q
12-BIT ACCURACY IN 8-PIN SOIC
q
FAST 3-WIRE SERIAL INTERFACE
q
LOW INL AND DNL:
1/2 LSB max
q
GAIN ACCURACY TO
1LSB max
q
LOW GAIN TEMPCO: 5ppm/
C max
q
OPERATES WITH +5V SUPPLY
q
TTL/CMOS COMPATIBLE
q
ESD PROTECTED
CMOS 12-Bit Serial Input Multiplying
DIGITAL-TO-ANALOG CONVERTER
APPLICATIONS
q
AUTOMATIC CALIBRATION
q
MOTION CONTROL
q
MICROPROCESSOR CONTROL SYSTEMS
q
PROGRAMMABLE AMPLIFIER/
ATTENUATORS
q
DIGITALLY CONTROLLED FILTERS
DESCRIPTION
The DAC8043 is a 12-bit current output multiplying
digital-to-analog converter (DAC) that is packaged in a
space-saving, surface-mount 8-pin SOIC. Its 3-wire se-
rial interface saves additional circuit board space which
results in low power dissipation. When used with micro-
processors having a serial port, the DAC8043 minimizes
the digital noise feedthrough from its input to output.
The serial port can be used as a dedicated analog bus and
kept inactive while the DAC8043 is in use. Serial inter-
facing reduces the complexity of opto or transformer
isolation applications.
The DAC8043 contains a 12-bit serial-in, parallel-out
shift register, a 12-bit DAC register, a 12-bit CMOS
DAC, and control logic. Serial input (SRI) data is clocked
into the input register on the rising edge of the clock
(CLK) pulse. When the new data word had been clocked
in, it is loaded into the DAC register by taking the LD
input low. Data in the DAC register is converted to an
output current by the D/A converter.
The DAC8043 operates from a single +5V power supply
which makes the DAC8043 an ideal low power, small
size, high performance solution for several applications.
12-Bit
D/A
Converter
12-Bit
DAC Register
12-Bit Input
Shift Register
12
12
V
REF
LD
CLK
SRI
R
FB
I
OUT
V
DD
GND
1
5
7
6
2
3
8
4
R
FB
1993 Burr-Brown Corporation
PDS-1197B
Printed in U.S.A. March, 1998
SBAS028
2
DAC8043
DAC8043U
DAC8043UC
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
At V
DD
= +5V; V
REF
= +10V; I
OUT
= GND = 0V; T
A
= Full Temperature Range specified under Absolute Maximum Ratings, unless otherwise noted.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE
Resolution
N
12
12
Bits
Nonlinearity
(1)
INL
1
1/2
LSB
Differential Nonlinearity
(2)
DNL
1
1/2
LSB
Gain Error
(3)
FSE
T
A
= +25
C
2
1
LSB
T
A
= Full Temp Range
2
2
LSB
Gain Tempco
(5)
TC
FSE
5
5
ppm/
C
Power Supply Rejection Ratio
PSRR
V
DD
=
5%
0.0006
0.002
0.0006
0.002
%/%
Output Leakage Current
(4)
I
LKG
T
A
= +25
C
5
5
nA
T
A
= Full Temp Range
100
25
nA
Zero Scale Error
(7, 12)
I
ZSE
T
A
= +25
C
0.03
0.03
LSB
T
A
= Full Temp Range
0.60
0.15
LSB
Input Resistance
(8)
R
IN
7
11
15
7
11
15
k
AC PERFORMANCE
Output Current Settling Time
(5, 6)
t
S
T
A
= +25
C
0.25
1
0.25
1
s
Digital-to-Analog Glitch
V
REF
= 0V
2
20
2
20
nVs
Energy
(5, 10)
Q
I
OUT
= Load = 100
C
EXT
= 13pF
DAC Register Loaded Alternately with all 0s and all 1s
Feedthrough Error
(5, 11)
FT
V
REF
= 20Vp-p at f = 10kHz
0.7
1
0.7
1
mVp-p
(V
REF
to I
OUT
)
Digital Input = 0000 0000 0000
T
A
= +25
C
Total Harmonic Distortion
(5)
THD
V
REF
= 6V
RMS
at 1kHz
85
85
dB
DAC Register Loaded with all 1s
Output Noise Voltage Density
(5, 13)
e
N
10Hz to 100kHz
17
17
nV/
Hz
Between R
FB
and I
OUT
DIGITAL INPUTS
Digital Input High
V
IH
2.4
2.4
V
Digital Input Low
V
IL
0.8
0.8
V
Input Leakage Current
(9)
I
IL
V
IN
= 0V to +5V
1
1
A
Input Capacitance
(5, 11)
C
IN
V
IN
= 0V
8
8
pF
ANALOG OUTPUTS
Output Capacitance
(5)
C
OUT
Digital Inputs = V
IH
110
110
pF
Digital Inputs = V
IL
80
80
pF
TIMING CHARACTERISTICS
(5, 14)
Data Setup Time
t
DS
T
A
= Full Temperature Range
40
40
ns
Data Hold Time
t
DH
T
A
= Full Temperature Range
80
80
ns
Clock Pulse Width High
t
CH
T
A
= Full Temperature Range
90
90
ns
Clock Pulse Width Low
t
CL
T
A
= Full Temperature Range
120
120
ns
Load Pulse Width
t
LD
T
A
= Full Temperature Range
120
120
ns
LSB Clock into Input Register
to Load DAC Register Time
t
ASB
T
A
= Full Temperature Range
0
0
ns
POWER SUPPLY
Supply Voltage
V
DD
4.75
5
5.25
4.75
5
5.25
V
Supply Current
I
DD
Digital Inputs = V
IH
or V
IL
500
500
A
Digital Inputs = 0V or V
DD
100
100
A
NOTES: (1)
1/2 LSB =
0.012% of Full Scale. (2) All grades are monotonic to 12-bits over temperature. (3) Using internal feedback resistor. (4) Applies to I
OUT
; All
digital inputs = 0V. (5) Guaranteed by design and not tested. (6) I
OUT
Load = 100
, C
EXT
= 13pF, digital input = 0V to V
DD
or V
DD
to 0V. Extrapolated to 1/2 LSB:
t
S
= propagation delay (t
PD
) + 9
where
= measured time constant of the final RC decay. (7) V
REF
= +10V, all digital inputs = 0V. (8) Absolute temperature coefficient
is less than
50ppm/
C. (9) Digital inputs are CMOS gates: I
IN
is typically 1nA at +25
C. (10) V
REF
= 0V, all digital inputs = 0V to V
DD
or V
DD
to 0V. (11) All digital
inputs = 0V. (12) Calculated from worst case R
REF
: I
ZSE
(in LSBs) = (R
REF
X I
LKG
X 4096)/V
REF
. (13) Calculations from en =
4K TRB where: K = Boltzmann constant,
J/
K, R = resistance,
. T = Resistor temperature,
K, B = bandwidth, Hz. (14) Tested at V
IN
= 0V or V
DD
.
3
DAC8043
DAC8043
PARAMETER
SYMBOL
CONDITIONS
LIMIT
UNITS
STATIC ACCURACY
Resolution
N
12
Bits min
Integral Nonlinearity
INL
1
LSB max
Differential Nonlinearity
DNL
1
LSB max
Gain Error
G
FSE
Using Internal Feedback Resistor
2
LSB max
Power Supply Rejection Ratio
PSRR
V
DD
=
5%
0.002
%/% max
Output Leakage Current (I
OUT
)
I
LKG
Digital Inputs = V
IL
5
nA max
REFERENCE INPUT
Input Resistance
R
IN
7/15
k
min/max
DIGITAL INPUTS
Digital Input HIGH
V
IH
2.4
V min
Digital Input LOW
V
IL
0.8
V max
Input Leakage Current
I
IL
V
IN
= 0V to V
DD
1
A max
POWER SUPPLY
Supply Current
I
DD
Digital Inputs = V
IH
or V
IL
500
A max
Digital Inputs = 0V to V
DD
100
A max
NOTE: Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not
guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
WAFER TEST LIMITS
At V
DD
= +5V; V
REF
= +10V; I
OUT
= GND = 0V; T
A
= +25
C.
ELECTROSTATIC
DISCHARGE SENSITIVITY
Any integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet
published specifications.
Digital Inputs: All digital inputs of the DAC8043 incorpo-
rate on-chip ESD protection circuitry. This protection is
designed and has been tested to withstand five 2500V
positive and negative discharges (100pF in series with 1500
)
applied to each digital input.
Analog Pins: Each analog pin has been tested to Burr-
Brown's analog ESD test consisting of five 1000V positive
and negative discharges (100pF in series with 1500
) ap-
plied to each pin. V
REF
and R
FB
show some sensitivity.
ABSOLUTE MAXIMUM RATINGS
V
DD
to GND .................................................................................. 0V, +7V
V
REF
to GND ......................................................................................
25V
V
RFB
to GND ......................................................................................
25V
Digital Input Voltage Range ................................................. 0.3V to V
DD
Output Voltage (Pin 3) ......................................................... 0.3 V to V
DD
Operating Temperature Range
AD ........................................................................................ 0
C to +70
C
U, UC ............................................................................... 40
C to +85
C
Junction Temperature .................................................................... +150
C
Storage Temperature .................................................... 65
C to + 150
C
Lead Temperature (soldering, 10s) .............................................. +300
C
JA
..........................................................................................................................
+100
C/W
JC
........................................................................................... +42
C/W
CAUTION: 1. Do not apply voltages higher than V
DD
or less than GND
potential on any terminal except V
REF
(Pin 1) and R
FB
(Pin 2). 2. The digital
control inputs are ESD protected: however, permanent damage may occur on
unprotected units from high-energy electrostatic fields. Keep units in conduc-
tive foam at all times until ready to use. 3. Use proper anti-static handling
procedures. 4. Absolute Maximum Ratings apply to both packaged devices.
Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device.
Top View
8-Pin SOIC
PIN CONFIGURATION
8
7
5
6
CLK
SRI
LD
V
DD
1
2
4
3
R
FB
I
OUT
GND
V
REF
PACKAGE/ORDERING INFORMATION
PACKAGE
TEMPERATURE
DRAWING
PRODUCT
INL
RANGE
PACKAGE
NUMBER
(1)
DAC8043U
1LSB
40
C to +85
C
8-pin SOIC
182
DAC8043UC
1/2LSB
40
C to +85
C
8-pin SOIC
182
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
4
DAC8043
WRITE CYCLE TIMING DIAGRAM
SRI
Bit 1
MSB
(1)
Bit 2
Bit 11
Bit 12
LSB
t
DH
t
CH
t
CL
1
CLK INPUT
LD
Load Serial Data
Into Input Register
Load Input Register's
Data Into DAC Register
t
DS
2
11
NOTE: (1) Data loaded MSB first.
t
ASB
t
LD
5
DAC8043
LINEARITY ERROR vs DIGITAL CODE
Digital Input Code (Decimal)
0
1024
2048
3072
4096
1
0.75
0.5
0.25
0
0.25
0.5
0.75
1
Linearity Error (LSB)
T
A
= +25C
V
REF
= +10V
DNL ERROR vs REFERENCE VOLTAGE
0.5
0.25
0
0.25
0.5
DNL (LSB)
V
REF
(V)
2
4
6
8
10
TOTAL HARMONIC DISTORTION vs FREQUENCY
(Multiplying Mode)
10
Frequency (Hz)
100
1000
10000
THD (dB)
0
20
40
60
80
100
120
V
DD
= +5V
V
IN
= 6Vrms
T
A
= +25C
SUPPLY CURRENT vs LOGIC INPUT VOLTAGE
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
I
DD
(mA)
V
IN
(V)
0
1
2
3
4
V
DD
= +5V
GAIN vs FREQUENCY
Gain (dB)
0
20
40
60
80
100
120
Frequency (Hz)
1k
10k
100k
1M
10M
Digital Input
= 1111 1111 1111
Digital Input
= 0000 0000 0000
V
DD
= +5V
V
REF
= 100mV
T
A
= +25C
LINEARITY ERROR vs REFERENCE VOLTAGE
0.5
0.25
0
0.25
0.5
INL (LSB)
V
REF
(V)
2
4
6
8
10
TYPICAL PERFORMANCE CURVES
At V
DD
= +5V; V
REF
= +10V; I
OUT
= GND = 0V; T
A
= Full Temperature Range specified under Absolute Maximum Ratings, unless otherwise noted.
6
DAC8043
DISCUSSION OF
SPECIFICATIONS
RELATIVE ACCURACY
This term, also known as end point linearity or integral
linearity, describes the transfer function of analog output to
digital input code. Relative accuracy describes the deviation
from a straight line, after zero and full scale errors have been
adjusted to zero.
DIFFERENTIAL NONLINEARITY
Differential nonlinearity is the deviation from an ideal 1LSB
change in the output when the input code changes by 1LSB.
A differential nonlinearity specification of 1LSB maximum
guarantees monotonicity.
GAIN ERROR
Gain error is the difference between the full-scale DAC
output and the ideal value. The ideal full scale output value
for the DAC8043 is (4095/4096)V
REF
. Gain error may be
adjusted to zero using external trims as shown in Figure 4.
OUTPUT LEAKAGE CURRENT
The current which appears at I
OUT
with the DAC loaded with
all zeros.
OUTPUT CAPACITANCE
The parasitic capacitance measured from I
OUT
to GND.
FEEDTHROUGH ERROR
The AC output error due to capacitive coupling from V
REF
to
I
OUT
with the DAC loaded with all zeros.
OUTPUT CURRENT SETTLING TIME
The time required for the output current to settle to within
+0.01% of final value for a full scale step.
DIGITAL-TO-ANALOG GLITCH ENERGY
The integrated area of the glitch pulse measured in nanovolt-
seconds. The key contributor to digital-to-analog glitch is
charge injected by digital logic switching transients.
CIRCUIT DESCRIPTION
Figure 1 shows a simplified schematic of a DAC8043. The
current from the V
REF
pin is switched between I
OUT
and GND
by 12 single-pole double-throw CMOS switches. This main-
tains a constant current in each leg of the ladder regardless of
the input code. The input resistance at V
REF
is therefore
constant and can be driven by either a voltage or current, AC
or DC, positive or negative polarity, and have a voltage range
up to
20V.
A CMOS switch transistor, included in series with the ladder
terminating resistor and in series with the feedback resistor,
R
FB
, compensates for the temperature drift of the ON resis-
tance of the ladder switches.
Figure 2 shows an equivalent circuit for the DAC. C
OUT
is the
output capacitance due to the N-channel switches and varies
from about 80pF to 110pF with digital input code. The current
source I
LKG
is the combination of surface and junction leak-
ages to the substrate. I
LKG
approximately doubles every 10
C.
R
O
is the equivalent output resistance of the D/A and it varies
with input code.
FB
R
OUT
I
V
REF
I
LKG
R
OUT
C
O
R
GND
D
IN
4096
x
V
REF
R
R
FIGURE 2. Equivalent Circuit for the DAC.
INSTALLATION
ESD PROTECTION
All digital inputs of the DAC8043 incorporate on-chip ESD
protection circuitry. This protection is designed to withstand
2.5kV (using the Human Body Model, 100pF and 1500
).
However, industry standard ESD protection methods should
be used when handling or storing these components. When
not in use, devices should be stored in conductive foam or
rails. The foam or rails should be discharged to the destina-
tion socket potential before devices are removed.
POWER SUPPLY CONNECTIONS
The DAC8043 is designed to operate on V
DD
= +5V
5%.
For optimum performance and noise rejection, power supply
decoupling capacitors C
D
should be added as shown in the
application circuits. These capacitors (1
F tantalum recom-
mended) should be located close to the D/A. Output op amp
analog common (+ input) should be connected as near to the
GND pins of the DAC8043 as possible.
WIRING PRECAUTIONS
To minimize AC feedthrough when designing a PC board,
care should be taken to minimize capacitive coupling be-
tween the V
REF
lines and the I
OUT
lines. Coupling from any
of the digital control or data lines might degrade the glitch
performance. Solder the DAC8043 directly into the
PC
board
without a socket. Sockets add parasitic capacitance (which
can degrade AC performance).
OUT
I
GND
FB
R
2R
2R
2R
2R
2R
R
R
R
V
REF
Bit 1
(MSB)
Bit 2
Bit 3
Bit 12
(LSB)
R
FIGURE 1. Simplified Circuit Diagram for the DAC.
7
DAC8043
AMPLIFIER OFFSET VOLTAGE
The output amplifier used with the DAC8043 should have
low input offset voltage to preserve the transfer function
linearity. The voltage output of the amplifier has an error
component which is the offset voltage of the op amp multi-
plied by the "noise gain" of the circuit. This "noise gain" is
equal to (R
F
/ R
O
+ 1) where R
O
is the output impedance of the
D/A I
OUT
terminal and R
F
is the feedback network imped-
ance. The nonlinearity occurs due to the output impedance
varying with code. If the 0 code case is excluded (where
R
O
= infinity), the R
O
will vary from R to 3R providing a
"noise gain" variation between 4/3 and 2. In addition, the
variation of R
O
is nonlinear with code, and the largest steps
in R
O
occur at major code transitions where the worst
differential nonlinearity is also likely to be experienced. The
nonlinearity seen at the amplifier output is
2V
OS
4V
OS
/3 = 2V
OS
/3.
Thus, to maintain good nonlinearity the op amp offset should
be much less than 1/2LSB.
UNIPOLAR CONFIGURATION
Figure 3 shows DAC8043 in a typical unipolar (two-quad-
rant) multiplying configuration. The analog output values
versus digital input code are listed in Table I. The operational
amplifiers used in this circuit can be single amplifiers such as
the OPA602, or a dual amplifier such as the OPA2107. C1
provides phase compensation to minimize settling time and
overshoot when using a high speed operational amplifier.
If an application requires the D/A to have zero gain error, the
circuit shown in Figure 4 may be used. Resistor R2 induces
a positive gain error greater than worst-case initial negative
gain error. Trim resistor R1 provides a variable negative gain
error and have sufficient trim range to correct for the worst-
case initial positive gain error plus the error produced by R2.
BIPOLAR CONFIGURATION
Figure 5 shows the DAC8043 in a typical bipolar (four-
quadrant) multiplying configuration. The analog output val-
ues versus digital input code are listed in Table II.
The operational amplifiers used in this circuit can be single
amplifiers such as the OPA602 or a dual amplifier such as
the OPA2107. C1 provides phase compensation to minimize
settling time and overshoot when using a high speed opera-
tional amplifier. The bipolar offset resistors R1R2 should
be ratio-matched to 0.01% to ensure the specified gain error
performance.
DATA INPUT
ANALOG OUTPUT
MSB
LSB
1111 1111 1111
V
REF
(4095/4096)
1000 0000 0000
V
REF
(2048/4096) = 1/2V
REF
0000 0000 0001
V
REF
(1/4096)
0000 0000 0000
0 Volts
TABLE I. Unipolar Output Code.
DATA INPUT
ANALOG OUTPUT
MSB
LSB
1111 1111 1111
+V
REF
(2047/2048)
1000 0000 0001
+V
REF
(1/2048)
1000 0000 0000
0 Volts
0111 1111 1111
V
REF
(1/2048)
0000 0000 0000
V
REF
(2048/2048)
TABLE II. Bipolar Output Code.
R
2
47
DAC
I
OUT
GND
R
FB
C
1
10pF
V
OUT
+
A1
V
DD
+5V
C
D
A1 OPA602 or 1/2 OPA2107.
+
1F
V
IN
R
100
1
REF
V
DAC8043
FIGURE 4. Unipolar Configuration with Gain Trim.
FIGURE 3. Unipolar Configuration.
DAC
I
OUT
GND
R
FB
C
1
10pF
DAC8043
V
OUT
+
A1
V
REF
V
DD
+5V
C
D
A1 OPA602 or 1/2 OPA2107.
+
1F
FIGURE 5. Bipolar Configuration.
R
3
10k
1
C
10pF
DAC
V
REF
V
DD
+5V
C
D
R
2
20k
V
OUT
A1
A1A2, OPA602 or 1/2 OPA2107.
A2
+
R
1
20k
I
OUT
R
FB
+
GND
1F
+
DAC8043
PACKAGING INFORMATION
ORDERABLE DEVICE
STATUS(1)
PACKAGE TYPE
PACKAGE DRAWING
PINS
PACKAGE QTY
DAC8043U
ACTIVE
SOIC
D
8
100
DAC8043U/2K5
ACTIVE
SOIC
D
8
2500
DAC8043UC
ACTIVE
SOIC
D
8
100
DAC8043UC/2K5
ACTIVE
SOIC
D
8
2500
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
PACKAGE OPTION ADDENDUM
www.ti.com
3-Oct-2003
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enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
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and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
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