www.ti.com
FEATURES
DESCRIPTION
APPLICATIONS
Input
Register
Input
Register
Input
Register
Input
Register
DAC
Register
DAC
Register
DAC
Register
DAC
Register
String
DAC A
String
DAC B
String
DAC C
String
DAC D
Interface
Logic
Power-On
Reset
Power-Down
Logic
Buffer
Buffer
Buffer
Buffer
V
DD
REFIN
SCLK
SYNC
DIN
GND
V
OUT
A
V
OUT
B
V
OUT
C
V
OUT
D
DAC7554
DAC7554
SLAS399A OCTOBER 2004 REVISED NOVEMBER 2004
12-BIT, QUAD, ULTRALOW GLITCH, VOLTAGE OUTPUT
DIGITAL-TO-ANALOG CONVERTER
2.7-V to 5.5-V Single Supply
The DAC7554 is a quad-channel, voltage-output DAC
with exceptional linearity and monotonicity. Its pro-
12-Bit Linearity and Monotonicity
prietary architecture minimizes undesired transients
Rail-to-Rail Voltage Output
such as code to code glitch and channel to channel
Settling Time: 5 s (Max)
crosstalk. The low-power DAC7554 operates from a
Ultralow Glitch Energy: 0.1 nVs
single 2.7-V to 5.5-V supply. The DAC7554 output
amplifiers can drive a 2-k
, 200-pF load rail-to-rail
Ultralow Crosstalk: 100 dB
with 5-s settling time; the output range is set using
Low Power: 880 A (Max)
an external voltage reference.
Per-Channel Power Down: 2 A (Max)
The 3-wire serial interface operates at clock rates up
Power-On Reset to Zero Scale
to 50 MHz and is compatible with SPI, QSPI,
SPI-Compatible Serial Interface: Up to 50 MHz
Microwire, and DSP interface standards. The outputs
of all DACs may be updated simultaneously or
Simultaneous or Sequential Update
sequentially. The parts incorporate a power-on-reset
Specified Temperature Range: 40
C to 105
C
circuit to ensure that the DAC outputs power up to
Small 10-Lead MSOP Package
zero volts and remain there until a valid write cycle to
the
device
takes
place.
The
parts
contain
a
power-down feature that reduces the current con-
sumption of the device to under 1 A.
Portable Battery-Powered Instruments
Digital Gain and Offset Adjustment
The small size and low-power operation makes the
DAC7554 ideally suited for battery-operated portable
Programmable Voltage and Current Sources
applications. The power consumption is typically 3.5
Programmable Attenuators
mW at 5 V, 1.65 mW at 3 V, and reduces to 1 W in
Industrial Process Control
power-down mode.
The DAC7554 is available in a 10-lead MSOP pack-
age and is specified over 40
C to 105
C.
FUNCTIONAL BLOCK DIAGRAM
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright 2004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
www.ti.com
ABSOLUTE MAXIMUM RATINGS
DAC7554
SLAS399A OCTOBER 2004 REVISED NOVEMBER 2004
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
ORDERING INFORMATION
SPECIFIED
PACKAGE
PACKAGE
ORDERING
TRANSPORT
PRODUCT
PACKAGE
TEMPERATURE
DESIGNATOR
MARKING
NUMBER
MEDIA
RANGE
DAC7554IDGS
80-piece Tube
DAC7554
10 MSOP
DGS
40
C TO 105
C
D754
DAC7554IDGSR
2500-piece Tape
and Reel
over operating free-air temperature range (unless otherwise noted)
(1)
UNIT
V
DD
to GND
0.3 V to 6 V
Digital input voltage to GND
0.3 V to V
DD
+ 0.3 V
V
out
to GND
0.3 V to V
DD
+ 0.3 V
Operating temperature range
40
C to 105
C
Storage temperature range
65
C to 150
C
Junction temperature (T
J
Max)
150
C
(1)
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
2
www.ti.com
ELECTRICAL CHARACTERISTICS
DAC7554
SLAS399A OCTOBER 2004 REVISED NOVEMBER 2004
V
DD
= 2.7 V to 5.5 V, REFIN = VDD, R
L
= 2 k
to GND; C
L
= 200 pF to GND; all specifications 40
C to 105
C, unless
otherwise specified
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE
(1)
Resolution
12
Bits
Relative accuracy
0.35
1
LSB
Differential nonlinearity
Specified monotonic by design
0.08
0.5
LSB
Offset error
12
mV
Zero-scale error
All zeroes loaded to DAC register
12
mV
Gain error
0.15
%FSR
Full-scale error
0.5
%FSR
Zero-scale error drift
7
V/
C
Gain temperature coefficient
3
ppm of FSR/
C
PSRR
V
DD
= 5 V
0.75
mV/V
OUTPUT CHARACTERISTICS
(2)
Output voltage range
0
REFIN
V
Output voltage settling time
R
L
= 2 k
; 0 pF < C
L
< 200 pF
5
s
Slew rate
1
V/s
Capacitive load stability
R
L
=
470
pF
R
L
= 2 k
1000
Digital-to-analog glitch impulse
1 LSB change around major carry
0.1
nV-s
Channel-to-channel crosstalk
1-kHz full-scale sine wave, outputs unloaded
100
dB
Digital feedthrough
0.1
nV-s
Output noise density (10-kHz offset fre-
70
nV/rtHz
quency)
Total harmonic distortion
F
OUT
= 1 kHz, F
S
= 1 MSPS, BW = 20 kHz
85
dB
DC output impedance
1
Short-circuit current
V
DD
= 5 V
50
mA
V
DD
= 3 V
20
Power-up time
Coming out of power-down mode, V
DD
= 5 V
15
s
Coming out of power-down mode, V
DD
= 3 V
15
LOGIC INPUTS
(2)
Input current
1
A
V
IN_L
, Input low voltage
V
DD
= 5 V
0.3 V
DD
V
V
IN_H
, Input high voltage
V
DD
= 3 V
0.7 V
DD
V
Pin capacitance
3
pF
POWER REQUIREMENTS
V
DD
2.7
5.5
V
I
DD
(normal operation)
DAC active and excluding load current
V
DD
= 3.6 V to 5.5 V
V
IH
= V
DD
and V
IL
= GND
700
880
A
V
DD
= 2.7 V to 3.6 V
550
830
I
DD
(all power-down modes)
V
DD
= 3.6 V to 5.5 V
V
IH
= V
DD
and V
IL
= GND
0.2
2
A
V
DD
= 2.7 V to 3.6 V
0.05
2
Reference input impedance
25
k
POWER EFFICIENCY
I
OUT
/I
DD
I
LOAD
= 2 mA, V
DD
= 5 V
93%
(1)
Linearity tested using a reduced code range of 48 to 4048; output unloaded.
(2)
Specified by design and characterization, not production tested.
3
www.ti.com
TIMING CHARACTERISTICS
(1) (2)
SCLK
SYNC
DIN
LD1
LD0
SEL1
SEL1
SEL1
SEL1
SEL0
D11
D1
D0
X
t
8
t
4
t
3
t
2
t
1
t
7
t
6
t
5
DAC7554
SLAS399A OCTOBER 2004 REVISED NOVEMBER 2004
V
DD
= 2.7 V to 5.5 V, R
L
= 2 k
to GND; all specifications 40
C to 105
C, unless otherwise specified
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
V
DD
= 2.7 V to 3.6 V
20
t
1
(3)
SCLK cycle time
ns
V
DD
= 3.6 V to 5.5 V
20
V
DD
= 2.7 V to 3.6 V
10
t
2
SCLK HIGH time
ns
V
DD
= 3.6 V to 5.5 V
10
V
DD
= 2.7 V to 3.6 V
10
t
3
SCLK LOW time
ns
V
DD
= 3.6 V to 5.5 V
10
V
DD
= 2.7 V to 3.6 V
4
SYNC falling edge to SCLK falling edge setup
t
4
ns
time
V
DD
= 3.6 V to 5.5 V
4
V
DD
= 2.7 V to 3.6 V
5
t
5
Data setup time
ns
V
DD
= 3.6 V to 5.5 V
5
V
DD
= 2.7 V to 3.6 V
4.5
t
6
Data hold time
ns
V
DD
= 3.6 V to 5.5 V
4.5
V
DD
= 2.7 V to 3.6 V
0
t
7
SCLK falling edge to SYNC rising edge
ns
V
DD
= 3.6 V to 5.5 V
0
V
DD
= 2.7 V to 3.6 V
20
t
8
Minimum SYNC HIGH time
ns
V
DD
= 3.6 V to 5.5 V
20
(1)
All input signals are specified with t
R
= t
F
= 1 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
(2)
See Serial Write Operation timing diagram Figure 1.
(3)
Maximum SCLK frequency is 50 MHz at V
DD
= 2.7 V to 5.5 V.
Figure 1. Serial Write Operation
4
www.ti.com
PIN DESCRIPTION
REFIN
SYNC
VDD
DIN
SCLK
10
9
8
7
6
1
2
3
4
5
V
OUT
A
V
OUT
B
GND
V
OUT
C
V
OUT
D
DAC7554
SLAS399A OCTOBER 2004 REVISED NOVEMBER 2004
DGS Package
(Top View)
Terminal Functions
TERMINAL
DESCRIPTION
NO.
NAME
1
VOUTA
Analog output voltage from DAC A
2
VOUTB
Analog output voltage from DAC B
3
GND
Ground
4
VOUTC
Analog output voltage from DAC C
5
VOUTD
Analog output voltage from DAC D
6
SCLK
Serial clock input
7
DIN
Serial data input
8
VDD
Analog voltage supply input
9
SYNC
Frame synchronization input. The falling edge of the FS pulse indicates the start of a serial data frame shifted out to
the DAC7554
10
REFIN
Analog input. External reference
5
www.ti.com
TYPICAL CHARACTERISTICS
-1
-0.5
0
0.5
1
Channel B
V
REF
= 4.096 V
V
DD
= 5 V
Linearity Error - LSB
Differential Linearity Error - LSB
Digital Input Code
-0.5
-0.25
0
0.25
0.5
0
512
1024
1536
2048
2560
3072
3584
4096
-1
-0.5
0
0.5
1
Channel A
V
REF
= 4.096 V
V
DD
= 5 V
-0.5
-0.25
0
0.25
0.5
0
512
1024
1536
2048
2560
3072
3584
4096
Linearity Error - LSB
Differential Linearity Error - LSB
Digital Input Code
-1
-0.5
0
0.5
1
-0.5
-0.25
0
0.25
0.5
0
512
1024
1536
2048
2560
3072
3584
4096
Channel C
V
REF
= 4.096 V
V
DD
= 5 V
Linearity Error - LSB
Differential Linearity Error - LSB
Digital Input Code
-1
-0.5
0
0.5
1
-0.5
-0.25
0
0.25
0.5
0
512
1024
1536
2048
2560
3072
3584
4096
Channel D
V
REF
= 4.096 V
V
DD
= 5 V
Linearity Error - LSB
Differential Linearity Error - LSB
Digital Input Code
DAC7554
SLAS399A OCTOBER 2004 REVISED NOVEMBER 2004
LINEARITY ERROR AND
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
DIFFERENTIAL LINEARITY ERROR
vs
vs
DIGITAL INPUT CODE
DIGITAL INPUT CODE
Figure 2.
Figure 3.
LINEARITY ERROR AND
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
DIFFERENTIAL LINEARITY ERROR
vs
vs
DIGITAL INPUT CODE
DIGITAL INPUT CODE
Figure 4.
Figure 5.
6
www.ti.com
-1
-0.5
0
0.5
1
Channel A
V
REF
= 2.5 V
V
DD
= 2.7 V
-0.5
-0.25
0
0.25
0.5
0
512
1024
1536
2048
2560
3072
3584
4096
Linearity Error - LSB
Differential Linearity Error - LSB
Digital Input Code
-1
-0.5
0
0.5
1
Channel B
V
REF
= 2.5 V
V
DD
= 2.7 V
-0.5
-0.25
0
0.25
0.5
0
512
1024
1536
2048
2560
3072
3584
4096
Linearity Error - LSB
Differential Linearity Error - LSB
Digital Input Code
-1
-0.5
0
0.5
1
Channel C
V
REF
= 2.5 V
V
DD
= 2.7 V
-0.5
-0.25
0
0.25
0.5
0
512
1024
1536
2048
2560
3072
3584
4096
Linearity Error - LSB
Differential Linearity Error - LSB
Digital Input Code
-1
-0.5
0
0.5
1
Channel D
V
REF
= 2.5 V
V
DD
= 2.7 V
-0.5
-0.25
0
0.25
0.5
0
512
1024
1536
2048
2560
3072
3584
4096
Linearity Error - LSB
Differential Linearity Error - LSB
Digital Input Code
DAC7554
SLAS399A OCTOBER 2004 REVISED NOVEMBER 2004
TYPICAL CHARACTERISTICS (continued)
LINEARITY ERROR AND
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
DIFFERENTIAL LINEARITY ERROR
vs
vs
DIGITAL INPUT CODE
DIGITAL INPUT CODE
Figure 6.
Figure 7.
LINEARITY ERROR AND
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
DIFFERENTIAL LINEARITY ERROR
vs
vs
DIGITAL INPUT CODE
DIGITAL INPUT CODE
Figure 8.
Figure 9.
7
www.ti.com
-5
0
5
10
-40
-10
20
50
80
Zero-Scale Error - mV
Channel A
Channel C
Channel D
Channel B
T
A
- Free-Air Temperature -
C
V
DD
= 5 V,
V
REF
= 4.096 V
-5
0
5
10
-40
-10
20
50
80
Zero-Scale Error - mV
Channel A
Channel C
Channel D
Channel B
T
A
- Free-Air Temperature -
C
V
DD
= 2.7 V,
V
REF
= 2.5 V
-10
-5
0
5
-40
-10
20
50
80
Full-Scale Error - mV
Channel A
Channel C
Channel D
Channel B
T
A
- Free-Air Temperature -
C
V
DD
= 5 V,
V
REF
= 4.096 V
-10
-5
0
5
-40
-10
20
50
80
Full-Scale Error - mV
Channel A
Channel C
Channel D
Channel B
T
A
- Free-Air Temperature -
C
V
DD
= 2.7 V,
V
REF
= 2.5 V
DAC7554
SLAS399A OCTOBER 2004 REVISED NOVEMBER 2004
TYPICAL CHARACTERISTICS (continued)
ZERO-SCALE ERROR
ZERO-SCALE ERROR
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
Figure 10.
Figure 11.
FULL-SCALE ERROR
FULL-SCALE ERROR
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
Figure 12.
Figure 13.
8
www.ti.com
0
0.05
0.1
0.15
0.2
0
5
10
15
Typical for All Channels
V
DD
= 2.7 V,
V
ref
= 2.5 V
V
DD
= 5.5 V,
V
ref
= 4.096 V
- Output V
oltage - V
V
O
I
SINK
- Sink Current - mA
DAC Loaded with 000h
5.20
5.30
5.40
5.50
0
5
10
15
Typical for All Channels
V
DD
= V
ref
= 5.5 V
- Output V
oltage - V
V
O
I
SOURCE
- Source Current - mA
DAC Loaded with FFFh
2.4
2.5
2.6
2.7
0
5
10
15
Typical for All Channels
V
DD
= V
ref
= 2.7 V
- Output V
oltage - V
V
O
I
SOURCE
- Source Current - mA
DAC Loaded with FFFh
0
100
200
300
400
500
600
700
0
512 1024 1536 2048
2560 3072 3584 4096
Digital Input Code
V
DD
= 5.5 V,
V
ref
= 4.096 V
V
DD
= 2.7 V,
V
ref
= 2.5 V
DDI
Supply Current -
-
A
All Channels Powered, No Load
DAC7554
SLAS399A OCTOBER 2004 REVISED NOVEMBER 2004
TYPICAL CHARACTERISTICS (continued)
SINK CURRENT AT NEGATIVE RAIL
SOURCE CURRENT AT POSITIVE RAIL
Figure 14.
Figure 15.
SUPPLY CURRENT
vs
SOURCE CURRENT AT POSITIVE RAIL
DIGITAL INPUT CODE
Figure 16.
Figure 17.
9
www.ti.com
0
100
200
300
400
500
600
700
800
-40
-10
20
50
80
110
V
DD
= 5.5 V,
V
ref
= 4.096 V
V
DD
= 2.7 V,
V
ref
= 2.5 V
DDI
Supply Current -
-
A
All Channels Powered, No Load
T
A
- Free-Air Temperature -
C
400
450
500
550
600
650
700
2.7
3.1
3.4
3.8
4.1
4.5
4.8
5.2
5.5
DDI
Supply Current -
-
A
V
DD
- Supply Voltage - V
All DACs Powered,
No Load,
V
ref
= 2.5 V
200
600
1000
1400
1800
2200
0
1
2
3
4
5
V
DD
= 5.5 V,
V
ref
= 4.096 V
V
DD
= 2.7 V,
V
ref
= 2.5 V
DDI
Supply Current -
-
A
T
A
= 25
5
C,
SCL Input (All Other Inputs = GND)
V
LOGIC
- Logic Input Voltage - V
0
500
1000
1500
2000
282 339 395 452 508 565 621 678 734 791
f - Frequency - Hz
I
DD
- Current Consumption -
m
A
V
DD
= 5.5 V,
V
ref
= 4.096 V
DAC7554
SLAS399A OCTOBER 2004 REVISED NOVEMBER 2004
TYPICAL CHARACTERISTICS (continued)
SUPPLY CURRENT
SUPPLY CURRENT
vs
vs
FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
Figure 18.
Figure 19.
SUPPLY CURRENT
vs
LOGIC INPUT VOLTAGE
HISTOGRAM OF CURRENT CONSUMPTION - 5.5 V
Figure 20.
Figure 21.
10
www.ti.com
-6
-4
-2
0
2
4
6
0
512
1024 1536 2048 2560 3072 3584 4095
Channel B Output
Channel C Output
Channel A Output
Channel D Output
V
DD
= 5 V,
V
ref
= 4.096 V,
T
A
= 25
5
C
T
otal Error - mV
Digital Input Code
0
500
1000
1500
2000
280 327 373 420 467 513 560 607 653 700
f - Frequency - Hz
I
DD
- Current Consumption -
m
A
V
DD
= 2.7 V,
V
ref
= 2.5 V
-6
-4
-2
0
2
4
6
0
512
1024 1536 2048 2560 3072 3584 4095
Channel A Output
Channel D Output
V
DD
= 2.7 V,
V
ref
= 2.5 V,
T
A
= 25
5
C
Channel C Output
Channel B Output
T
otal Error - mV
Digital Input Code
0
1
2
3
4
5
- Output V
oltage - V
V
O
t - Time - 4
m
s/div
V
DD
= 5 V,
V
ref
= 4.096 V,
Power-Up Code 4000
DAC7554
SLAS399A OCTOBER 2004 REVISED NOVEMBER 2004
TYPICAL CHARACTERISTICS (continued)
HISTOGRAM OF CURRENT CONSUMPTION - 2.7 V
TOTAL ERROR - 5 V
Figure 22.
Figure 23.
TOTAL ERROR - 2.7 V
EXITING POWER-DOWN MODE
Figure 24.
Figure 25.
11
www.ti.com
0
1
2
3
4
5
V
DD
= 5 V,
Output Loaded With 200 pF to GND
Code 41 to 4055
- Output V
oltage - V
V
O
t - Time - 5
m
s/div
V
ref
= 4.096 V
0
1
2
3
V
DD
= 2.7 V,
Output Loaded With 200 pF to GND
Code 41 to 4055
- Output V
oltage - V
V
O
t - Time - 5
m
s/div
V
ref
= 2.5 V
Time - (400 nS/Div)
Trigger Pulse
V
O
(5 mV/Div)
-
Trigger Pulse
V
O
(5 mV/Div)
-
Time - (400 nS/Div)
DAC7554
SLAS399A OCTOBER 2004 REVISED NOVEMBER 2004
TYPICAL CHARACTERISTICS (continued)
LARGE-SIGNAL SETTLING TIME - 5 V
LARGE-SIGNAL SETTLING TIME - 2.7 V
Figure 26.
Figure 27.
MIDSCALE GLITCH
WORST-CASE GLITCH
Figure 28.
Figure 29.
12
www.ti.com
Time - (400 nS/Div)
Trigger Pulse
V
O
(5 mV/Div)
-
Time - (400 nS/Div)
Trigger Pulse
V
O
(5 mV/Div)
-
-100
-90
-80
-70
-60
-50
-40
0
1
2
3
4
5
6
7
8
9
10
V
DD
= 5 V, V
ref
= 4.096 V
-1 dB FSR Digital Input, Fs = 1 Msps
Measurement Bandwidth = 20 kHz
2nd Harmonic
3rd Harmonic
THD - T
otal Harmonic Distortion - dB
Output Frequency (Tone) - kHz
THD
DAC7554
SLAS399A OCTOBER 2004 REVISED NOVEMBER 2004
TYPICAL CHARACTERISTICS (continued)
CHANNEL-TO-CHANNEL CROSSTALK
DIGITAL FEEDTHROUGH ERROR
FOR A FULL-SCALE SWING
Figure 30.
Figure 31.
TOTAL HARMONIC DISTORTION
vs
OUTPUT FREQUENCY
Figure 32.
13
www.ti.com
3-Wire Serial Interface
DAC7554
SLAS399A OCTOBER 2004 REVISED NOVEMBER 2004
The DAC7554 digital interface is a standard 3-wire SPI/QSPI/Microwire/DSP-compatible interface.
Table 1. Serial Interface Programming
CONTROL
DATA BITS
DAC(s)
FUNCTION
LD1
LD0
Sel1
Sel0
DB11-DB0
0
0
0
0
data
A
Input register updated
0
0
0
1
data
B
Input register updated
0
0
1
0
data
C
Input register updated
0
0
1
1
data
D
Input register updated
0
1
0
0
data
A
DAC register updated, output updated
0
1
0
1
data
B
DAC register updated, output updated
0
1
1
0
data
C
DAC register updated, output updated
0
1
1
1
data
D
DAC register updated, output updated
1
0
0
0
data
A
Input register and DAC register updated, output updated
1
0
0
1
data
B
Input register and DAC register updated, output updated
1
0
1
0
data
C
Input register and DAC register updated, output updated
1
0
1
1
data
D
Input register and DAC register updated, output updated
1
1
0
0
data
A-D
Input register updated
1
1
0
1
data
A-D
DAC register updated, output updated
1
1
1
0
data
A-D
Input register and DAC register updated, output updated
1
1
1
1
data
--
Power-Down Mode - See Table 2
Sel1
Sel0
CHANNEL SELECT
0
0
Channel A
0
1
Channel B
1
0
Channel C
1
1
Channel D
LD1
LD0
FUNCTION
0
0
Single channel store. The selected input register is updated.
0
1
Single channel DAC update. The selected DAC register is updated with input register information.
1
0
Single channel update. The selected input and DAC register is updated.
1
1
Depends on the Sel1 and Sel0 Bits
14
www.ti.com
POWER-DOWN MODE
DAC7554
SLAS399A OCTOBER 2004 REVISED NOVEMBER 2004
In power-down mode, the DAC outputs are programmed to one of three output impedances, 1 k
, 100 k
, or
floating.
Table 2. Power-Down Mode Control
EXTENDED CONTROL
DATA BITS
FUNCTION
LD1
LD0
Sel1
Sel0
DB11
DB10
DB9
DB8
DB7
DB6-DB0
1
1
1
1
0
0
0
0
0
X
PWD Hi-Z (selected channel = A)
1
1
1
1
0
0
0
0
1
X
PWD 1 k
(selected channel = A)
1
1
1
1
0
0
0
1
0
X
PWD 100 k
(selected channel = A)
1
1
1
1
0
0
0
1
1
X
PWD Hi-Z (selected channel = A)
1
1
1
1
0
0
1
0
0
X
PWD Hi-Z (selected channel = B)
1
1
1
1
0
0
1
0
1
X
PWD 1 k
(selected channel = B)
1
1
1
1
0
0
1
1
0
X
PWD 100 k
(selected channel = B)
1
1
1
1
0
0
1
1
1
X
PWD Hi-Z (selected channel = B)
1
1
1
1
0
1
0
0
0
X
PWD Hi-Z (selected channel = C)
1
1
1
1
0
1
0
0
1
X
PWD 1 k
(selected channel = C)
1
1
1
1
0
1
0
1
0
X
PWD 100 k
(selected channel = C)
1
1
1
1
0
1
0
1
1
X
PWD Hi-Z (selected channel = C)
1
1
1
1
0
1
1
0
0
X
PWD Hi-Z (selected channel = D)
1
1
1
1
0
1
1
0
1
X
PWD 1 k
(selected channel = D)
1
1
1
1
0
1
1
1
0
X
PWD 100 k
(selected channel = D)
1
1
1
1
0
1
1
1
1
X
PWD Hi-Z (selected channel = D)
1
1
1
1
1
X
X
0
0
X
PWD Hi-Z (all channels)
1
1
1
1
1
X
X
0
1
X
PWD 1 k
(all channels)
1
1
1
1
1
X
X
1
0
X
PWD 100 k
(all channels)
1
1
1
1
1
X
X
1
1
X
PWD Hi-Z (all channels)
DB11
ALL CHANNELS FLAG
0
See DB7DB10
1
DB10 and DB9 are Don't Care
DB10
DB9
Channel Select
0
0
Channel A
0
1
Channel B
1
0
Channel C
1
1
Channel D
DB8
DB7
Power-Down Mode
0
0
Power-down Hi-Z
0
1
Power-down 1 k
1
0
Power-down 100 k
1
1
Power-down Hi-Z
15
www.ti.com
THEORY OF OPERATION
DAC External Reference Input
D/A SECTION
Power-On Reset
_
+
Resistor String
Ref +
Ref -
DAC Register
V
OUT
REFIN
GND
Power Down
REFIN
To Output
Amplifier
R
R
R
R
GND
SERIAL INTERFACE
RESISTOR STRING
16-Bit Word and Input Shift Register
OUTPUT BUFFER AMPLIFIERS
DAC7554
SLAS399A OCTOBER 2004 REVISED NOVEMBER 2004
There is a single reference input pin for the four
The architecture of the DAC7554 consists of a string
DACs. The reference input is unbuffered. The user
DAC followed by an output buffer amplifier. Figure 33
can have a reference voltage as low as 0.25 V and
shows a generalized block diagram of the DAC
as high as V
DD
because there is no restriction due to
architecture.
headroom and footroom of any reference amplifier.
It is recommended to use a buffered reference in the
external circuit (e.g., REF3140). The input impedance
is typically 25 k
.
On power up, all internal registers are cleared and all
Figure 33. Typical DAC Architecture
channels are updated with zero-scale voltages. Until
valid data is written, all DAC outputs remain in this
state. This is particularly useful in applications where
The input coding to the DAC7554 is unsigned binary,
it is important to know the state of the DAC outputs
which gives the ideal output voltage as:
while the device is powering up. In order not to turn
V
OUT
= REFIN
D/4096
on ESD protection devices, V
DD
should be applied
Where D = decimal equivalent of the binary code that
before any other pin is brought high.
is loaded to the DAC register which can range from 0
to 4095.
The DAC7554 has a flexible power-down capability
as described in Table 2. Individual channels could be
powered down separately or all channels could be
powered down simultaneously. During a power-down
condition, the user has flexibility to select the output
impedance of each channel. During power-down
operation, each channel can have either 1-k
,
100-k
, or Hi-Z output impedance to ground.
Figure 34. Typical Resistor String
The DAC7554 is controlled over a versatile 3-wire
serial interface, which operates at clock rates up to
The resistor string section is shown in Figure 34. It is
50 MHz and is compatible with SPI, QSPI, Microwire,
simply a string of resistors, each of value R. The
and DSP interface standards.
digital code loaded to the DAC register determines at
which node on the string the voltage is tapped off to
be fed into the output amplifier. The voltage is tapped
off by closing one of the switches connecting the
The input shift register is 16 bits wide. DAC data is
string to the amplifier. Because it is a string of
loaded into the device as a 16-bit word under the
resistors, it is specified monotonic. The DAC7554
control of a serial clock input, SCLK, as shown in the
architecture uses four separate resistor strings to
Figure 1 timing diagram. The 16-bit word, illustrated
minimize channel-to-channel crosstalk.
in Table 1, consists of four control bits followed by 12
bits of DAC data. The data format is straight binary
with all zeroes corresponding to 0-V output and all
ones corresponding to full-scale output (V
REF
1
The output buffer amplifier is capable of generating
LSB). Data is loaded MSB first (Bit 15) where the first
rail-to-rail voltages on its output, which gives an
two bits (LD1 and LD0) determine if the input register,
output range of 0 V to V
DD
. It is capable of driving a
DAC register, or both are updated with shift register
load of 2 k
in parallel with up to 1000 pF to GND.
input data. Bit 13 and bit 12 (Sel1 and Sel0)
The source and sink capabilities of the output ampli-
determine whether the data is for DAC A, DAC B,
fier can be seen in the typical curves. The slew rate is
DAC C, DAC D, or all DACs. All channels are
1 V/s with a half-scale settling time of 3 s with the
updated when bits 15 and 14 (LD1 and LD0) are
output unloaded.
high.
16
www.ti.com
Generating
5-V,
10-V, and
12-V Outputs For
INTEGRAL AND DIFFERENTIAL LINEARITY
GLITCH ENERGY
CHANNEL-TO-CHANNEL CROSSTALK
APPLICATION INFORMATION
Waveform Generation
DAC7554
SLAS399A OCTOBER 2004 REVISED NOVEMBER 2004
The SYNC input is a level-triggered input that acts as
can exceed 1 MSPS if the waveform to be generated
a frame synchronization signal and chip enable. Data
consists of small voltage steps between consecutive
can only be transferred into the device while SYNC is
DAC updates. To obtain a high dynamic range,
low. To start the serial data transfer, SYNC should be
REF3140 (4.096 V) or REF02 (5.0 V) are rec-
taken low, observing the minimum SYNC to SCLK
ommended for reference voltage generation.
falling edge setup time, t
4
. After SYNC goes low,
serial data is shifted into the device's input shift
Precision Industrial Control
register on the falling edges of SCLK for 16 clock
pulses. Any data and clock pulses after the sixteenth
Industrial control applications can require multiple
falling edge of SCLK are ignored. No further serial
feedback loops consisting of sensors, ADCs, MCUs,
data transfer occurs until SYNC is taken high and low
DACs, and actuators. Loop accuracy and loop speed
again.
are the two important parameters of such control
loops.
SYNC may be taken high after the falling edge of the
sixteenth SCLK pulse, observing the minimum SCLK
Loop Accuracy:
falling edge to SYNC rising edge time, t
7
.
In a control loop, the ADC has to be accurate. Offset,
After the end of serial data transfer, data is automati-
gain, and the integral linearity errors of the DAC are
cally transferred from the input shift register to the
not factors in determining the accuracy of the loop.
input register of the selected DAC. If SYNC is taken
As long as a voltage exists in the transfer curve of a
high before the sixteenth falling edge of SCLK, the
monotonic DAC, the loop can find it and settle to it.
data transfer is aborted and the DAC input registers
On the other hand, DAC resolution and differential
are not updated.
linearity do determine the loop accuracy, because
each DAC step determines the minimum incremental
change the loop can generate. A DNL error less than
1 LSB (non-monotonicity) can create loop instability.
The DAC7554 uses precision thin-film resistors pro-
A DNL error greater than +1 LSB implies unnecess-
viding exceptional linearity and monotonicity. Integral
arily large voltage steps and missed voltage targets.
linearity error is typically within (+/-) 0.35 LSBs, and
With high DNL errors, the loop looses its stability,
differential linearity error is typically within (+/-) 0.08
resolution, and accuracy. Offering 12-bit ensured
LSBs.
monotonicity and
0.08 LSB typical DNL error, 755X
DACs are great choices for precision control loops.
Loop Speed:
The DAC7554 uses a proprietary architecture that
minimizes glitch energy. The code-to-code glitches
Many factors determine control loop speed. Typically,
are so low, they are usually buried within the
the ADC's conversion time, and the MCU's compu-
wide-band noise and cannot be easily detected. The
tation time are the two major factors that dominate
DAC7554 glitch is typically well under 0.1 nV-s. Such
the time constant of the loop. DAC settling time is
low glitch energy provides more than 10X improve-
rarely a dominant factor because ADC conversion
ment over industry alternatives.
times usually exceed DAC conversion times. DAC
offset, gain, and linearity errors can slow the loop
down only during the start-up. Once the loop reaches
its steady-state operation, these errors do not affect
The DAC7554 architecture is designed to minimize
loop speed any further. Depending on the ringing
channel-to-channel crosstalk. The voltage change in
characteristics of the loop's transfer function, DAC
one channel does not affect the voltage output in
glitches can also slow the loop down. With its 1
another channel. The DC crosstalk is in the order of a
MSPS (small-signal) maximum data update rate,
few microvolts. AC crosstalk is also less than 100
DAC7554 can support high-speed control loops.
dBs. This provides orders of magnitude improvement
Ultra-low glitch energy of the DAC7554 significantly
over certain competing architectures.
improves loop stability and loop settling time.
Generating Industrial Voltage Ranges:
For control loop applications, DAC gain and offset
errors are not important parameters. This could be
Due to its exceptional linearity, low glitch, and low
exploited to lower trim and calibration costs in a
crosstalk, the DAC7554 is well suited for waveform
high-voltage control circuit design. Using a quad
generation (from DC to 10 kHz). The DAC7554
operational amplifier (OPA4130), and a voltage refer-
large-signal settling time is 5 s, supporting an
ence (REF3140), the DAC7554 can generate the
update rate of 200 KSPS. However, the update rates
wide voltage swings required by the control loop.
17
www.ti.com
V
out
+
V
ref
R2
R1
)
1
Din
4096
*
V
tail
R2
R1
(1)
DAC7554
REFIN
DAC7554
_
+
V
dac
R2
R1
REF3140
V
ref
V
tail
V
OUT
OPA4130
DAC7554
SLAS399A OCTOBER 2004 REVISED NOVEMBER 2004
Fixed R1 and R2 resistors can be used to coarsely
set the gain required in the first term of the equation.
Once R2 and R1 set the gain to include some
minimal over-range, a DAC7554 channel could be
used to set the required offset voltages. Residual
errors are not an issue for loop accuracy because
offset and gain errors could be tolerated. One
DAC7554 channel can provide the Vtail voltage, while
the other three DAC7554 channels can provide Vdac
Figure 35. Low-cost, Wide-swing Voltage Gener-
voltages to help generate three high-voltage outputs.
ator for Control Loop Applications
For
5-V operation: R1=10 k
, R2 = 15 k
, Vtail =
3.33 V, Vref = 4.096 V
The output voltage of the configuration is given by:
For
10-V operation: R1=10 k
, R2 = 39 k
, Vtail =
2.56 V, Vref = 4.096 V
For
12-V operation: R1=10 k
, R2 = 49 k
, Vtail =
2.45 V, Vref = 4.096 V
18
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
DAC7554IDGS
ACTIVE
MSOP
DGS
10
100
TBD
CU NIPDAU
Level-1-220C-UNLIM
DAC7554IDGSR
ACTIVE
MSOP
DGS
10
2500
TBD
CU NIPDAU
Level-1-220C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco
Plan
-
The
planned
eco-friendly
classification:
Pb-Free
(RoHS)
or
Green
(RoHS
&
no
Sb/Br)
-
please
check
http://www.ti.com/productcontent
for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
Addendum-Page 1
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI's terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
Telephony
www.ti.com/telephony
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright
2005, Texas Instruments Incorporated
PDF 
ZIP